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git01.mediatek.com / filogic / uboot / 2911d1935feac8bb0d27e84dbecae4103327ad9b / arch / riscv / dts / jh7110.dtsi
  1. 1345c9e riscv: dts: jh7110: Add clock source from PLL by Xingyu Wu · Fri Jul 07 18:50:09 2023 +0800
  2. 7ae81bb riscv: dts: jh7110: Add PLL clock controller node by Xingyu Wu · Fri Jul 07 18:50:08 2023 +0800
  3. 7f63bd9 riscv: dts: jh7110: Add ethernet device tree nodes by Yanhong Wang · Thu Jun 15 17:36:44 2023 +0800
  4. 96c3eb72 riscv: dts: jh7110: Add initial StarFive JH7110 device tree by Yanhong Wang · Wed Mar 29 11:42:21 2023 +0800