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git01.mediatek.com / filogic / uboot / 219e52c44cd21f75636527fc583d9fe9379792be / drivers / fpga / zynqpl.c
  1. dec7ea0 Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet" by Tom Rini · Mon May 20 13:35:03 2024 -0600
  2. abb9a04 Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" by Tom Rini · Sat May 18 20:20:43 2024 -0600
  3. 10d301b fpga: Remove <common.h> and add needed includes by Tom Rini · Wed May 01 19:30:47 2024 -0600
  4. 364d002 global: Finish CONFIG -> CFG migration by Tom Rini · Tue Jan 10 11:19:45 2023 -0500
  5. 6a5dccc global: Move remaining CONFIG_SYS_* to CFG_SYS_* by Tom Rini · Wed Nov 16 13:10:41 2022 -0500
  6. fb7fcc2 fpga: zynq: Remove post config info message for SPL by Stefan Herbrechtsmeier · Mon Aug 08 16:53:31 2022 +0200
  7. c0806cc fpga: xilinx: pass compatible flags to load() callback by Oleksandr Suvorov · Fri Jul 22 17:16:10 2022 +0300
  8. 36eca7c fpga: zynqpl: fix buffer alignment by Michael Walle · Wed Feb 10 22:42:29 2021 +0100
  9. 1fa7cbe fpga: zynqpl: Flush dcache only for non-bitstream data by T Karthik Reddy · Tue Mar 12 20:20:23 2019 +0530
  10. 59d9ab7 fpga: zynqpl: Check if aes engine is enabled by Ibai Erkiaga · Thu Apr 05 05:19:27 2018 -0700
  11. f3b078f fpga: zynqpl: Check fpga config completion by T Karthik Reddy · Tue Mar 12 20:20:20 2019 +0530
  12. c575058 fpga: zynqpl: Correct PL bitstream loading sequence for zynqaes by Siva Durga Prasad Paladugu · Wed Dec 09 18:46:43 2015 +0530
  13. dbd7954 common: Drop linux/delay.h from common header by Simon Glass · Sun May 10 11:40:11 2020 -0600
  14. 0f2af88 common: Drop log.h from common header by Simon Glass · Sun May 10 11:40:05 2020 -0600
  15. 274e0b0 common: Drop net.h from common header by Simon Glass · Sun May 10 11:39:56 2020 -0600
  16. 1d91ba7 common: Move some cache and MMU functions out of common.h by Simon Glass · Thu Nov 14 12:57:37 2019 -0700
  17. 9bf652d arm: zynq: Add an info message about post config by Siva Durga Prasad Paladugu · Sat Mar 23 16:01:36 2019 +0530
  18. 3b45f6b fpga: Replace char * with const char * for filename by Tien Fong Chee · Fri Feb 15 15:57:07 2019 +0800
  19. 4397602 drivers: fpga: zynqpl: fix compilation with SPL by Luis Araneda · Thu Jul 19 03:10:17 2018 -0400
  20. e460352 xilinx: zynq: Add support to secure images by Siva Durga Prasad Paladugu · Tue Jun 26 15:02:19 2018 +0530
  21. 10e4779 SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · Sun May 06 17:58:06 2018 -0400
  22. eac0cd1 fpga: zynq: Add delay after PCFG_PROG_B change by Siva Durga Prasad Paladugu · Tue Mar 06 17:37:09 2018 +0530
  23. 117b6ca fpga: zynqmp: Remove empty functions by Michal Simek · Fri Dec 16 10:01:45 2016 +0100
  24. a73bda4 Move console definitions into a new console.h file by Simon Glass · Sun Nov 08 23:47:45 2015 -0700
  25. 96171fb fs: API changes enabling extra parameter to return size of type loff_t by Suriyan Ramasami · Mon Nov 17 14:39:38 2014 -0800
  26. 9112b4c fpga: Added support to load bit stream from SD/MMC by Siva Durga Prasad Paladugu · Fri Mar 14 16:35:37 2014 +0530
  27. f46ccf4 fpga: zynqpl: Clean partial bitstream handling by Michal Simek · Fri May 02 14:15:27 2014 +0200
  28. 1466365 fpga: Define bitstream type based on command selection by Michal Simek · Fri May 02 14:09:30 2014 +0200
  29. 7857c72 fpga: zynq: Use helper function zynq_validate_bitstream by Siva Durga Prasad Paladugu · Thu Mar 13 11:57:34 2014 +0530
  30. 2f72618 fpga: zynq: Use helper functions for zynq dma by Siva Durga Prasad Paladugu · Wed Mar 12 17:09:26 2014 +0530
  31. 15f156a fpga: zynq: Remove sparse warnings by Michal Simek · Fri Apr 25 13:51:58 2014 +0200
  32. 75fafac fpga: xilinx: Simplify load/dump/info function handling by Michal Simek · Thu Mar 13 13:07:57 2014 +0100
  33. 25e1e2e fpga: xilinx: Avoid CamelCase for in Xilinx_desc by Michal Simek · Thu Mar 13 12:49:21 2014 +0100
  34. 267d8e2 sizes.h - consolidate for all architectures by Alexey Brodkin · Wed Feb 26 17:47:58 2014 +0400
  35. cbe4b09 fpga: zynq: Correct fpga load when buf is not aligned by Novasys Ingenierie · Wed Nov 27 09:03:01 2013 +0100
  36. 94dc92f fpga: zynqpl: Do not place bitstream below 1MB by Michal Simek · Fri Oct 04 10:48:59 2013 +0200
  37. 8cfb246 fpga: zynqpl: Add dcache flush support by Jagannadha Sutradharudu Teki · Fri Sep 20 18:39:47 2013 +0530
  38. bd8ec7e Coding Style cleanup: remove trailing white space by Wolfgang Denk · Mon Oct 07 13:07:26 2013 +0200
  39. 5577585 fpga: zynqpl: Clear loopback mode during device init by Soren Brinkmann · Fri Jun 14 17:43:24 2013 -0700
  40. 52f91b5 fpga: zynqpl: Add support for zc7100 device. by Michal Simek · Mon Jun 17 13:54:07 2013 +0200
  41. d79de1d Add GPL-2.0+ SPDX-License-Identifier to source files by Wolfgang Denk · Mon Jul 08 09:37:19 2013 +0200
  42. 15d654c fpga: zynq: Add support for loading bitstream by Michal Simek · Mon Apr 22 15:43:02 2013 +0200