| commit | f3b078fb2e0d97e2d66d68960c44489f81980fc0 | [log] [tgz] |
|---|---|---|
| author | T Karthik Reddy <t.karthik.reddy@xilinx.com> | Tue Mar 12 20:20:20 2019 +0530 |
| committer | Michal Simek <michal.simek@xilinx.com> | Wed Jun 24 13:07:58 2020 +0200 |
| tree | 80c8905ca178e44b698da0bb1bc3adb0befa558e | |
| parent | c575058d964d86557071d1bc9a9c965c5f1d5aaa [diff] |
fpga: zynqpl: Check fpga config completion This patch checks fpga config completion when a bitstream is loaded into PL. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>