| commit | cbe4b09a7379bc4d8f3c0900f48c62a1e19a193b | [log] [tgz] |
|---|---|---|
| author | Novasys Ingenierie <xilinx@novasys-ingenierie.com> | Wed Nov 27 09:03:01 2013 +0100 |
| committer | Michal Simek <michal.simek@xilinx.com> | Thu Feb 06 10:08:03 2014 +0100 |
| tree | 16897cb24add276f1939a6de6283bc11e4de8a0e | |
| parent | 7e782781283c3785bbcdd102cbe07ba13bdbc33c [diff] |
fpga: zynq: Correct fpga load when buf is not aligned When ARCH_DMA_MINALIGN is greater than header size of the bit file, and buf is not aligned, new_buf address became greater then buf_start address and the load_word loop corrupts bit file data. A work around is to decrease new_buf of ARCH_DMA_MINALIGN, it might corrupt data before buf but permits to load correctly. Signed-off-by: Stany MARCEL <smarcel@novasys-ingenierie.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>