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git01.mediatek.com / filogic / uboot / 20964b681580f5dbf16824ff2c02e3521b83f999 / arch / riscv / Kconfig
  1. 20964b6 riscv: enable CONFIG_DEBUG_UART by default by Heinrich Schuchardt · Sat Sep 23 01:35:26 2023 +0200
  2. 03a885b riscv: set fdtfile on VisionFive 2 by Heinrich Schuchardt · Thu Sep 07 13:21:28 2023 +0200
  3. d1a3254 riscv: Kconfig: Add SPL_ZERO_MEM_BEFORE_USE by Shengyu Qu · Wed Aug 09 21:11:31 2023 +0800
  4. 5dfa901 riscv: t-head: licheepi4a: initial support added by Yixun Lan · Sat Jul 08 19:24:32 2023 +0800
  5. b5f0372 riscv: Rename SiFive CLINT to RISC-V ALINT by Bin Meng · Wed Jun 21 23:11:46 2023 +0800
  6. 08b8d26 riscv: clint: Update the sifive clint ipi driver to support aclint by Bin Meng · Wed Jun 21 23:11:45 2023 +0800
  7. 3867879 board: starfive: Add TARGET_STARFIVE_VISIONFIVE2 to Kconfig by Yanhong Wang · Wed Mar 29 11:42:20 2023 +0800
  8. 249ce73 riscv: Rename Andes cpu and board names by Leo Yu-Chi Liang · Tue Feb 14 20:42:49 2023 +0800
  9. 693baee riscv: clarify meaning of CONFIG_SBI_V02 by Heinrich Schuchardt · Tue Nov 08 15:53:12 2022 +0100
  10. 739cd6f riscv: Rename Andes PLIC to PLICSW by Yu Chien Peter Lin · Tue Oct 25 23:03:50 2022 +0800
  11. c66c950 riscv: support building double-float modules by Heinrich Schuchardt · Wed Oct 12 14:59:51 2022 +0200
  12. 9c4d5c1 riscv: Introduce AVAILABLE_HARTS by Rick Chen · Wed Sep 21 14:34:54 2022 +0800
  13. 7e5e029 spl: introduce SPL_XIP to config by Nikita Shubin · Fri Sep 02 11:47:39 2022 +0300
  14. ea14390 riscv: alloc space exhausted by Heinrich Schuchardt · Tue Apr 05 16:47:15 2022 +0200
  15. 17a2907 Merge tag 'v2021.10-rc4' into next by Tom Rini · Thu Sep 16 10:29:40 2021 -0400
  16. c39544c riscv: lib: implement enable_caches for sifive cache by Zong Li · Wed Sep 01 15:01:41 2021 +0800
  17. 4b198e3 Kconfig: Remove all default n/no options by Michal Simek · Fri Aug 27 08:48:10 2021 +0200
  18. 3ef67ae Finish converting CONFIG_SYS_CACHELINE_SIZE to Kconfig by Tom Rini · Thu Aug 26 11:47:59 2021 -0400
  19. 2ef594d board: riscv: add openpiton-riscv64 SoC support by Tianrui Wei · Thu Jul 01 12:54:19 2021 +0800
  20. 2e5da52 board: sifive: add HiFive Unmatched board support by Green Wan · Thu May 27 06:52:13 2021 -0700
  21. 7f33743 riscv: cpu: fu740: Add support for cpu fu740 by Green Wan · Thu May 27 06:52:07 2021 -0700
  22. ce64bd3 riscv: Group assembly optimized implementation of memory routines into a submenu by Bin Meng · Thu May 13 16:46:18 2021 +0800
  23. 614b1d8 riscv: Split SiFive CLINT support between SPL and U-Boot proper by Bin Meng · Tue May 11 20:04:12 2021 +0800
  24. 23caf66 riscv: assembler versions of memcpy, memmove, memset by Heinrich Schuchardt · Sat Mar 27 12:37:04 2021 +0100
  25. e9ead4a riscv: sifive: Rename fu540 board to unleashed by Bin Meng · Wed Mar 17 11:10:58 2021 +0800
  26. a235d43 riscv: Add DMA 64-bit address support by Padmarao Begari · Fri Jan 15 08:20:35 2021 +0530
  27. 5abf1f3 riscv: Move Andes PLMT driver to drivers/timer by Sean Anderson · Sun Oct 25 21:46:56 2020 -0400
  28. 584a5ee riscv: Only enable OF_BOARD_FIXUP for S-Mode by Sean Anderson · Sat Sep 05 09:22:11 2020 -0400
  29. 272ab20 riscv: Rework Sifive CLINT as UCLASS_TIMER driver by Sean Anderson · Mon Sep 28 10:52:26 2020 -0400
  30. 87e6ce5 riscv: Rework Andes PLMT as a UCLASS_TIMER driver by Sean Anderson · Mon Sep 28 10:52:24 2020 -0400
  31. 9baaaef riscv: Rework riscv timer driver to only support S-mode by Sean Anderson · Mon Sep 28 10:52:21 2020 -0400
  32. 90fa4e9 Merge branch 'next' by Tom Rini · Mon Jul 06 15:46:38 2020 -0400
  33. 2bdcd05 riscv: Enable CONFIG_OF_BOARD_FIXUP by default for OF_SEPARATE by Bin Meng · Thu Jun 25 18:16:08 2020 -0700
  34. edc32ab riscv: Add Sipeed Maix support by Sean Anderson · Wed Jun 24 06:41:25 2020 -0400
  35. 7f4b666 riscv: Add option to support RISC-V privileged spec 1.9 by Sean Anderson · Wed Jun 24 06:41:19 2020 -0400
  36. 25269c0 riscv: cpu: fu540: Add support for cpu fu540 by Pragnesh Patel · Fri May 29 11:33:34 2020 +0530
  37. 3aecc4b riscv: Make SBI v0.2 the default SBI version by Bin Meng · Thu Apr 16 08:09:33 2020 -0700
  38. a75325e riscv: Add Kconfig option for SBI v0.2 by Bin Meng · Thu Apr 16 08:09:32 2020 -0700
  39. 4997522 riscv: Add SMP Kconfig option dependency for U-Boot proper by Bin Meng · Thu Apr 16 08:09:31 2020 -0700
  40. b161f90 riscv: Introduce SPL_SMP Kconfig option for U-Boot SPL by Bin Meng · Thu Apr 16 08:09:30 2020 -0700
  41. b9d856f Merge branch 'next' of git://git.denx.de/u-boot-usb into next by Tom Rini · Tue Mar 31 17:24:19 2020 -0400
  42. 887d809 riscv: Introduce a new config for SBI v0.1 by Bin Meng · Mon Mar 09 19:35:30 2020 -0700
  43. ee3bcd0 riscv: Add basic support for SBI v0.2 by Bin Meng · Mon Mar 09 19:35:28 2020 -0700
  44. 8798f9c Kconfig: Remove redundant variable sets by Tom Rini · Wed Mar 11 18:11:12 2020 -0400
  45. e8b46a1 riscv: Add option to print registers on exception by Sean Anderson · Wed Dec 25 00:27:44 2019 -0500
  46. 0381370 riscv: increase stack size to avoid a stack overflow during distro boot by Lukas Auer · Sun Oct 20 20:53:47 2019 +0200
  47. 396f0bd riscv: add SPL support by Lukas Auer · Wed Aug 21 21:14:45 2019 +0200
  48. 6134659 riscv: add run mode configuration for SPL by Lukas Auer · Wed Aug 21 21:14:43 2019 +0200
  49. 4216f34 riscv: Add Microchip MPFS Icicle board support by Padmarao Begari · Tue May 28 15:47:51 2019 +0530
  50. 43ec7e0 CONFIG_SPL_SYS_[DI]CACHE_OFF: add by Trevor Woerner · Fri May 03 09:41:00 2019 -0400
  51. ba64b8b CONFIG_SYS_[DI]CACHE_OFF: convert to Kconfig by Trevor Woerner · Fri May 03 09:40:59 2019 -0400
  52. e5e6c36 riscv: Introduce CONFIG_XIP to support booting from flash by Rick Chen · Tue Apr 30 13:49:33 2019 +0800
  53. 7376677 riscv: Add a SYSCON driver for Andestech's PLMT by Rick Chen · Tue Apr 02 15:56:40 2019 +0800
  54. 6df4ed0 riscv: Add a SYSCON driver for Andestech's PLIC by Rick Chen · Tue Apr 02 15:56:39 2019 +0800
  55. a359665 riscv: add support for multi-hart systems by Lukas Auer · Sun Mar 17 19:28:37 2019 +0100
  56. e79178b riscv: implement IPI platform functions using SBI by Lukas Auer · Sun Mar 17 19:28:34 2019 +0100
  57. 83d573d riscv: add infrastructure for calling functions on other harts by Lukas Auer · Sun Mar 17 19:28:32 2019 +0100
  58. 7a167f2 riscv: Add SiFive FU540 board support by Anup Patel · Mon Feb 25 08:15:19 2019 +0000
  59. 1240cd6 riscv: Rename cpu/qemu to cpu/generic by Anup Patel · Mon Feb 25 08:14:10 2019 +0000
  60. dada2d1 riscv: Enlarge the default SYS_MALLOC_F_LEN by Bin Meng · Wed Dec 12 06:12:33 2018 -0800
  61. 8fa4478 riscv: qemu: Add platform-specific Kconfig options by Bin Meng · Wed Dec 12 06:12:32 2018 -0800
  62. f3c8479 riscv: Implement riscv_get_time() API using rdtime instruction by Anup Patel · Wed Dec 12 06:12:31 2018 -0800
  63. b6ee5e1 riscv: Add a SYSCON driver for SiFive's Core Local Interruptor by Bin Meng · Wed Dec 12 06:12:30 2018 -0800
  64. 2788177 riscv: Introduce a Kconfig option for machine mode by Anup Patel · Wed Dec 12 06:12:29 2018 -0800
  65. ecc5d83 riscv: add Kconfig entries for the code model by Lukas Auer · Wed Dec 12 06:12:23 2018 -0800
  66. 89b3934 riscv: Add kconfig option to run U-Boot in S-mode by Anup Patel · Mon Dec 03 10:57:40 2018 +0530
  67. 842d580 riscv: cache: Implement i/dcache [status, enable, disable] by Rick Chen · Wed Nov 07 09:34:06 2018 +0800
  68. 002012f riscv: add Kconfig entries for the C and A ISA extensions by Lukas Auer · Thu Nov 22 11:26:14 2018 +0100
  69. 7ab1df0 riscv: select CONFIG_PHYS_64BIT on RV64I systems by Lukas Auer · Thu Nov 22 11:26:13 2018 +0100
  70. 54ebfe7 riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I by Lukas Auer · Thu Nov 22 11:26:12 2018 +0100
  71. 8a8694d riscv: Add QEMU virt board support by Bin Meng · Wed Sep 26 06:55:21 2018 -0700
  72. 6b69775 riscv: kconfig: Normalize architecture name spelling by Bin Meng · Wed Sep 26 06:55:06 2018 -0700
  73. b66af37 riscv: cpu: nx25: Rename as ax25 by Rick Chen · Tue May 29 09:54:40 2018 +0800
  74. 64d4ead riscv: Add Kconfig to support RISC-V by Rick Chen · Tue Dec 26 13:55:52 2017 +0800