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filogic
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uboot
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1e26864b5a0cc69abaa2c88634bb3f807e6cd60c
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arch
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riscv
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cpu
111b804
riscv: Provide a mechanism to fix DT for reserved memory
by Atish Patra
· Tue Apr 21 11:15:01 2020 -0700
b161f90
riscv: Introduce SPL_SMP Kconfig option for U-Boot SPL
by Bin Meng
· Thu Apr 16 08:09:30 2020 -0700
88fc2a5
riscv: Merge unnecessary SMP ifdefs in start.S
by Bin Meng
· Thu Apr 16 08:09:29 2020 -0700
6c1e6dd
riscv: qemu: Remove the simple-bus driver for the SoC node
by Bin Meng
· Thu Apr 16 08:09:28 2020 -0700
d12b55b
riscv: ax25: cache: Remove SPL_RISCV_MMODE config check
by Pragnesh Patel
· Sat Mar 14 19:12:28 2020 +0530
750fee5
riscv: Remove unnecessary instruction
by Sean Anderson
· Mon Jan 27 16:39:44 2020 -0500
e8b46a1
riscv: Add option to print registers on exception
by Sean Anderson
· Wed Dec 25 00:27:44 2019 -0500
5e75a27
riscv: Fix breakage caused by linker relaxation
by Sean Anderson
· Tue Dec 17 21:35:32 2019 -0500
284f71b
common: Move relocate_code() to init.h
by Simon Glass
· Sat Dec 28 10:44:45 2019 -0700
c308e01
riscv: add option to wait for ack from secondary harts in smp functions
by Lukas Auer
· Sun Dec 08 23:28:51 2019 +0100
55bc1bd
riscv: Fix clear bss loop in the start-up code
by Rick Chen
· Thu Nov 14 13:52:27 2019 +0800
883275d
riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL
by Rick Chen
· Thu Nov 14 13:52:25 2019 +0800
276292a
riscv: ax25: add SPL support
by Rick Chen
· Thu Nov 14 13:52:21 2019 +0800
6980b6b
common: Move board_get_usable_ram_top() out of common.h
by Simon Glass
· Thu Nov 14 12:57:45 2019 -0700
8f3f761
common: Move enable/disable_interrupts out of common.h
by Simon Glass
· Thu Nov 14 12:57:42 2019 -0700
6333448
common: Move ARM cache operations out of common.h
by Simon Glass
· Thu Nov 14 12:57:39 2019 -0700
1d91ba7
common: Move some cache and MMU functions out of common.h
by Simon Glass
· Thu Nov 14 12:57:37 2019 -0700
49cb706
riscv: cache: use CCTL to flush d-cache
by Rick Chen
· Wed Aug 28 18:46:11 2019 +0800
05a684e
riscv: cache: Flush L2 cache before jump to linux
by Rick Chen
· Wed Aug 28 18:46:09 2019 +0800
19117d2
riscv: ax25: add imply v5l2 cache controller
by Rick Chen
· Thu Aug 29 10:30:13 2019 +0800
b9ad45d
riscv: update fix_rela_dyn
by Marcus Comstedt
· Sun Aug 11 14:45:29 2019 +0200
2a2a925
riscv: support SPL stack and global data relocation
by Lukas Auer
· Wed Aug 21 21:14:46 2019 +0200
396f0bd
riscv: add SPL support
by Lukas Auer
· Wed Aug 21 21:14:45 2019 +0200
6134659
riscv: add run mode configuration for SPL
by Lukas Auer
· Wed Aug 21 21:14:43 2019 +0200
f942636
riscv: Access CSRs using CSR numbers
by Bin Meng
· Wed Jul 10 23:43:13 2019 -0700
43ec7e0
CONFIG_SPL_SYS_[DI]CACHE_OFF: add
by Trevor Woerner
· Fri May 03 09:41:00 2019 -0400
3043b90
riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is enabled
by Rick Chen
· Tue Apr 30 13:49:35 2019 +0800
e5e6c36
riscv: Introduce CONFIG_XIP to support booting from flash
by Rick Chen
· Tue Apr 30 13:49:33 2019 +0800
f71410a
riscv: ax25: Andes specific cache shall only support in M-mode
by Rick Chen
· Tue Apr 02 15:56:42 2019 +0800
14a1075
riscv: ax25: Add platform-specific Kconfig options
by Rick Chen
· Tue Apr 02 15:56:41 2019 +0800
cddde09
riscv: hang if relocation of secondary harts fails
by Lukas Auer
· Sun Mar 17 19:28:40 2019 +0100
9ebf294
riscv: do not rely on hart ID passed by previous boot stage
by Lukas Auer
· Sun Mar 17 19:28:39 2019 +0100
a359665
riscv: add support for multi-hart systems
by Lukas Auer
· Sun Mar 17 19:28:37 2019 +0100
8de4b3e
riscv: save hart ID in register tp instead of s0
by Lukas Auer
· Sun Mar 17 19:28:36 2019 +0100
01558e2
riscv: delay initialization of caches and debug UART
by Lukas Auer
· Sun Mar 17 19:28:35 2019 +0100
0bbe9cf
riscv: generic: Ensure that U-Boot runs within 4GB for 64bit systems
by Anup Patel
· Mon Feb 25 08:14:30 2019 +0000
1240cd6
riscv: Rename cpu/qemu to cpu/generic
by Anup Patel
· Mon Feb 25 08:14:10 2019 +0000
6280e32
riscv: move the AX25-specific implementation of flush_dcache_all
by Lukas Auer
· Fri Jan 04 01:37:29 2019 +0100
89681a7
riscv: Save boot hart id to the global data
by Bin Meng
· Wed Dec 12 06:12:45 2018 -0800
1f46f6d
riscv: Return to previous privilege level after trap handling
by Bin Meng
· Wed Dec 12 06:12:43 2018 -0800
ea95452
riscv: Fix context restore before returning from trap handler
by Bin Meng
· Wed Dec 12 06:12:42 2018 -0800
2e128a7
riscv: Move trap handler codes to mtrap.S
by Bin Meng
· Wed Dec 12 06:12:41 2018 -0800
a7544ed
riscv: Do some basic architecture level cpu initialization
by Bin Meng
· Wed Dec 12 06:12:40 2018 -0800
edfe9a9
riscv: Update supports_extension() to use desc from cpu driver
by Bin Meng
· Wed Dec 12 06:12:38 2018 -0800
2caa1ee
riscv: Remove non-DM version of print_cpuinfo()
by Bin Meng
· Wed Dec 12 06:12:35 2018 -0800
7a3bbfb
riscv: Probe cpus during boot
by Bin Meng
· Wed Dec 12 06:12:34 2018 -0800
8fa4478
riscv: qemu: Add platform-specific Kconfig options
by Bin Meng
· Wed Dec 12 06:12:32 2018 -0800
4b284ad
riscv: ax25: Hide the ax25-specific Kconfig option
by Bin Meng
· Wed Dec 12 06:12:28 2018 -0800
66c6935
riscv: qemu: Create a simple-bus driver for the soc node
by Bin Meng
· Wed Dec 12 06:12:25 2018 -0800
2a21815
riscv: ax25-ae350: Pass dtb address to u-boot with a1 register
by Rick Chen
· Mon Dec 03 17:48:20 2018 +0800
89b3934
riscv: Add kconfig option to run U-Boot in S-mode
by Anup Patel
· Mon Dec 03 10:57:40 2018 +0530
842d580
riscv: cache: Implement i/dcache [status, enable, disable]
by Rick Chen
· Wed Nov 07 09:34:06 2018 +0800
39a652b
riscv: save hart ID and device tree passed by prior boot stage
by Lukas Auer
· Thu Nov 22 11:26:29 2018 +0100
8598e6b
riscv: do not blindly modify the mstatus CSR
by Lukas Auer
· Thu Nov 22 11:26:28 2018 +0100
230ab8a
riscv: remove unused labels in start.S
by Lukas Auer
· Thu Nov 22 11:26:27 2018 +0100
ccd035a
Drop CONFIG_INIT_CRITICAL
by Bin Meng
· Thu Nov 22 11:26:26 2018 +0100
af51285
riscv: align mtvec on a 4-byte boundary
by Lukas Auer
· Thu Nov 22 11:26:25 2018 +0100
7cf4368
riscv: fix inconsistent use of spaces and tabs in start.S
by Lukas Auer
· Thu Nov 22 11:26:24 2018 +0100
de8d80e
riscv: Move do_reset() to a common place
by Bin Meng
· Wed Sep 26 06:55:22 2018 -0700
8a8694d
riscv: Add QEMU virt board support
by Bin Meng
· Wed Sep 26 06:55:21 2018 -0700
bcb3843
riscv: Make start.S available for all targets
by Bin Meng
· Wed Sep 26 06:55:17 2018 -0700
055700e
riscv: Add a helper routine to print CPU information
by Bin Meng
· Wed Sep 26 06:55:14 2018 -0700
c7feb19
riscv: Fix coding style issues in the linker script
by Bin Meng
· Wed Sep 26 06:55:12 2018 -0700
a28e0f5
riscv: Move the linker script to the CPU root directory
by Bin Meng
· Wed Sep 26 06:55:11 2018 -0700
b28f7b3
riscv: Include bss subsections in linker script
by Alexander Graf
· Mon Aug 20 14:25:49 2018 +0200
94a10f2
efi_loader: Rename sections to allow for implicit data
by Alexander Graf
· Tue Jun 12 07:48:37 2018 +0200
b66af37
riscv: cpu: nx25: Rename as ax25
by Rick Chen
· Tue May 29 09:54:40 2018 +0800
9677a37
efi_loader: Enable RISC-V support
by Rick Chen
· Mon May 28 19:06:37 2018 +0800
10e4779
SPDX: Convert all of our single license tags to Linux Kernel style
by Tom Rini
· Sun May 06 17:58:06 2018 -0400
40a6fe7
riscv: ae250: Support DT provided by the board at runtime
by Rick Chen
· Thu Mar 29 10:08:33 2018 +0800
e76b804
riscv: cpu: Add nx25 to support RISC-V
by Rick Chen
· Tue Dec 26 13:55:48 2017 +0800