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git01.mediatek.com / filogic / uboot / 1c478c29c1c753cbe11c8e4d0eccf3582270aa27 / drivers / clk / rockchip / clk_rk3328.c
  1. 432976f rockchip: clk: bind reset driver by Elaine Zhang · Tue Dec 19 18:22:38 2017 +0800
  2. 4fbb6c2 rockchip: clock: update sysreset driver binding by Kever Yang · Fri Nov 03 15:16:13 2017 +0800
  3. a942223 rockchip: clk: Add rk3328 SARADC clock support by David Wu · Wed Sep 20 14:35:44 2017 +0800
  4. 99b546d rockchip: clk: update dwmmc clock div by Kever Yang · Thu Jul 27 12:54:01 2017 +0800
  5. ba1dea4 dm: Rename dev_addr..() functions by Simon Glass · Wed May 17 17:18:05 2017 -0600
  6. 5a02763 rockchip: clk: rk3328: add ciu_clk entry for eMMC/SDMMC by Xu Ziyuan · Sun Apr 16 17:44:46 2017 +0800
  7. 1cfd550 rockchip: rk3328: add clock driver by Kever Yang · Thu Feb 23 15:37:52 2017 +0800