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git01.mediatek.com / filogic / uboot / 0f30f0cd4a8f3c49a29a8af7391f6fdcfb630b3d / arch / riscv / cpu / start.S
  1. 604a0c5 riscv: spl: Remove relocation sections by Bin Meng · Thu Apr 13 14:20:07 2023 +0800
  2. 8615b1d riscv: Avoid updating the link register by Bin Meng · Thu Apr 13 14:20:06 2023 +0800
  3. 63d0fe4 riscv: Change to use positive offset to access relocation entries by Bin Meng · Thu Apr 13 14:20:05 2023 +0800
  4. 73449c9 riscv: Optimize loading relocation type by Bin Meng · Thu Apr 13 14:20:01 2023 +0800
  5. 3ccd29e riscv: Optimize source end address calculation in start.S by Bin Meng · Thu Apr 13 14:20:00 2023 +0800
  6. 9c4d5c1 riscv: Introduce AVAILABLE_HARTS by Rick Chen · Wed Sep 21 14:34:54 2022 +0800
  7. 7e5e029 spl: introduce SPL_XIP to config by Nikita Shubin · Fri Sep 02 11:47:39 2022 +0300
  8. 4150eec riscv: ae350: Fix XIP config boot failure by Leo Yu-Chi Liang · Wed Jun 01 10:01:49 2022 +0800
  9. 66ae7fe riscv: cpu: set gp before board_init_f_init_reserve by Nikita Shubin · Fri May 20 14:41:17 2022 +0300
  10. 4ddbade Migrate CUSTOM_SYS_INIT_SP_ADDR to Kconfig using system-constants.h by Tom Rini · Wed May 25 12:16:03 2022 -0400
  11. dc35df4 riscv: Remove OF_PRIOR_STAGE from RISC-V boards by Ilias Apalodimas · Tue Oct 12 00:00:13 2021 +0300
  12. 2612080 riscv: cpu: Add callback to init each core by Green Wan · Sun May 02 23:23:04 2021 -0700
  13. 4b96c88 riscv: fix the wrong swap value register by Brad Kim · Fri Nov 13 20:47:51 2020 +0900
  14. 5bdad9f riscv: Add some comments to start.S by Sean Anderson · Mon Sep 21 07:51:41 2020 -0400
  15. 2c4c7d1 riscv: Ensure gp is NULL or points to valid data by Sean Anderson · Mon Sep 21 07:51:40 2020 -0400
  16. 934b24a riscv: Consolidate fences into AMOs for available_harts_lock by Sean Anderson · Mon Sep 21 07:51:39 2020 -0400
  17. e8de08b Revert "riscv: Clear pending interrupts before enabling IPIs" by Sean Anderson · Mon Sep 21 07:51:35 2020 -0400
  18. 4e3ba2a riscv: Fix linking error when building u-boot-spl with no SMP support by Leo Yu-Chi Liang · Mon Jun 29 16:27:28 2020 +0800
  19. 84df2e1 riscv: Clear pending interrupts before enabling IPIs by Sean Anderson · Wed Jun 24 06:41:17 2020 -0400
  20. 111b804 riscv: Provide a mechanism to fix DT for reserved memory by Atish Patra · Tue Apr 21 11:15:01 2020 -0700
  21. b161f90 riscv: Introduce SPL_SMP Kconfig option for U-Boot SPL by Bin Meng · Thu Apr 16 08:09:30 2020 -0700
  22. 88fc2a5 riscv: Merge unnecessary SMP ifdefs in start.S by Bin Meng · Thu Apr 16 08:09:29 2020 -0700
  23. 750fee5 riscv: Remove unnecessary instruction by Sean Anderson · Mon Jan 27 16:39:44 2020 -0500
  24. 284f71b common: Move relocate_code() to init.h by Simon Glass · Sat Dec 28 10:44:45 2019 -0700
  25. c308e01 riscv: add option to wait for ack from secondary harts in smp functions by Lukas Auer · Sun Dec 08 23:28:51 2019 +0100
  26. 55bc1bd riscv: Fix clear bss loop in the start-up code by Rick Chen · Thu Nov 14 13:52:27 2019 +0800
  27. b9ad45d riscv: update fix_rela_dyn by Marcus Comstedt · Sun Aug 11 14:45:29 2019 +0200
  28. 2a2a925 riscv: support SPL stack and global data relocation by Lukas Auer · Wed Aug 21 21:14:46 2019 +0200
  29. 396f0bd riscv: add SPL support by Lukas Auer · Wed Aug 21 21:14:45 2019 +0200
  30. 6134659 riscv: add run mode configuration for SPL by Lukas Auer · Wed Aug 21 21:14:43 2019 +0200
  31. f942636 riscv: Access CSRs using CSR numbers by Bin Meng · Wed Jul 10 23:43:13 2019 -0700
  32. 3043b90 riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is enabled by Rick Chen · Tue Apr 30 13:49:35 2019 +0800
  33. e5e6c36 riscv: Introduce CONFIG_XIP to support booting from flash by Rick Chen · Tue Apr 30 13:49:33 2019 +0800
  34. cddde09 riscv: hang if relocation of secondary harts fails by Lukas Auer · Sun Mar 17 19:28:40 2019 +0100
  35. 9ebf294 riscv: do not rely on hart ID passed by previous boot stage by Lukas Auer · Sun Mar 17 19:28:39 2019 +0100
  36. a359665 riscv: add support for multi-hart systems by Lukas Auer · Sun Mar 17 19:28:37 2019 +0100
  37. 8de4b3e riscv: save hart ID in register tp instead of s0 by Lukas Auer · Sun Mar 17 19:28:36 2019 +0100
  38. 01558e2 riscv: delay initialization of caches and debug UART by Lukas Auer · Sun Mar 17 19:28:35 2019 +0100
  39. 89681a7 riscv: Save boot hart id to the global data by Bin Meng · Wed Dec 12 06:12:45 2018 -0800
  40. 2e128a7 riscv: Move trap handler codes to mtrap.S by Bin Meng · Wed Dec 12 06:12:41 2018 -0800
  41. 2a21815 riscv: ax25-ae350: Pass dtb address to u-boot with a1 register by Rick Chen · Mon Dec 03 17:48:20 2018 +0800
  42. 89b3934 riscv: Add kconfig option to run U-Boot in S-mode by Anup Patel · Mon Dec 03 10:57:40 2018 +0530
  43. 842d580 riscv: cache: Implement i/dcache [status, enable, disable] by Rick Chen · Wed Nov 07 09:34:06 2018 +0800
  44. 39a652b riscv: save hart ID and device tree passed by prior boot stage by Lukas Auer · Thu Nov 22 11:26:29 2018 +0100
  45. 8598e6b riscv: do not blindly modify the mstatus CSR by Lukas Auer · Thu Nov 22 11:26:28 2018 +0100
  46. 230ab8a riscv: remove unused labels in start.S by Lukas Auer · Thu Nov 22 11:26:27 2018 +0100
  47. ccd035a Drop CONFIG_INIT_CRITICAL by Bin Meng · Thu Nov 22 11:26:26 2018 +0100
  48. af51285 riscv: align mtvec on a 4-byte boundary by Lukas Auer · Thu Nov 22 11:26:25 2018 +0100
  49. 7cf4368 riscv: fix inconsistent use of spaces and tabs in start.S by Lukas Auer · Thu Nov 22 11:26:24 2018 +0100
  50. bcb3843 riscv: Make start.S available for all targets by Bin Meng · Wed Sep 26 06:55:17 2018 -0700[Renamed from arch/riscv/cpu/ax25/start.S]
  51. b66af37 riscv: cpu: nx25: Rename as ax25 by Rick Chen · Tue May 29 09:54:40 2018 +0800[Renamed from arch/riscv/cpu/nx25/start.S]
  52. 10e4779 SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · Sun May 06 17:58:06 2018 -0400
  53. 40a6fe7 riscv: ae250: Support DT provided by the board at runtime by Rick Chen · Thu Mar 29 10:08:33 2018 +0800
  54. e76b804 riscv: cpu: Add nx25 to support RISC-V by Rick Chen · Tue Dec 26 13:55:48 2017 +0800