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git01.mediatek.com / filogic / uboot / 0c827a9b86d404846665826e29f596f22dae475e / arch / riscv / dts / jh7110-u-boot.dtsi
  1. ee037f5 Revert "riscv: dts: jh7110: Enable PLL node in SPL" by Leo Yu-Chi Liang · Mon Jul 22 11:15:58 2024 +0800
  2. 9d82440 riscv: dts: jh7110: Enable PLL node in SPL by Bo Gan · Tue Mar 05 19:00:11 2024 -0800
  3. 1345c9e riscv: dts: jh7110: Add clock source from PLL by Xingyu Wu · Fri Jul 07 18:50:09 2023 +0800
  4. 94817bf riscv: dts: jh7110: Add initial u-boot device tree by Yanhong Wang · Wed Mar 29 11:42:22 2023 +0800