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git01.mediatek.com / filogic / uboot / 084d88f3889a6dd8de0506a9ad66db34325486f7 / arch / arm / mach-socfpga / include / mach
  1. 977071e arch: arm: Agilex5 enablement by Jit Loon Lim · Tue Mar 12 22:01:03 2024 +0800
  2. 40575d7 mach-socfpga: do not overlap defines with lwip by Maxim Uvarov · Tue Dec 26 21:46:16 2023 +0600
  3. adc079f arm: socfpga: arria10: Enable double peripheral RBF configuration by Tien Fong Chee · Sun Nov 07 23:08:56 2021 +0800
  4. 8ca1708 arm: socfpga: arria10: Reset MPFE NoC after program periph / combined RBF by Tien Fong Chee · Sun Nov 07 23:08:55 2021 +0800
  5. b26072a arm: socfpga: arria10: Setting image magic value to romcode initswstate reg by Tien Fong Chee · Sun Nov 07 23:08:54 2021 +0800
  6. 62fb2b4 WS cleanup: remove SPACE(s) followed by TAB by Wolfgang Denk · Mon Sep 27 17:42:39 2021 +0200
  7. f8e2eab ddr: altera: Add SDRAM driver for Intel N5X device by Tien Fong Chee · Tue Aug 10 11:26:37 2021 +0800
  8. 4d7b6dc arm: socfpga: Add clock manager for Intel N5X device by Siew Chin Lim · Tue Aug 10 11:26:34 2021 +0800
  9. 8596188 arm: socfpga: Move cm_get_mpu_clk_hz function declaration to clock_manager.h by Siew Chin Lim · Tue Aug 10 11:26:33 2021 +0800
  10. df89b50 arm: socfpga: Add handoff data support for Intel N5X device by Tien Fong Chee · Tue Aug 10 11:26:29 2021 +0800
  11. b89899f arm: socfpga: Add base address for Intel N5X device by Siew Chin Lim · Tue Aug 10 11:26:28 2021 +0800
  12. 142d9c0 arm: socfpga: Changed base_addr_s10.h to base_addr_soc64.h by Siew Chin Lim · Tue Aug 10 11:26:27 2021 +0800
  13. 5474457 arm: socfpga: smc: Add function to get usercode by Siew Chin Lim · Thu Mar 25 14:07:45 2021 +0800
  14. c1888b0 arm: socfpga: Changed to store QSPI reference clock in kHz by Siew Chin Lim · Wed Mar 24 17:16:50 2021 +0800
  15. fa2cc49 arm: socfpga: Move Stratix10 and Agilex clock manager common code by Siew Chin Lim · Wed Mar 24 17:16:49 2021 +0800
  16. ff1eec3 arm: socfpga: Restructure Stratix10 and Agilex handoff code by Siew Chin Lim · Wed Mar 24 13:11:38 2021 +0800
  17. 02d2500 arm: socfpga: Rearrange sequence of macros in handoff_soc64.h by Siew Chin Lim · Wed Mar 24 13:11:37 2021 +0800
  18. 954d599 arm: socfpga: Rename Stratix10 and Agilex handoff common macros by Siew Chin Lim · Wed Mar 24 13:11:34 2021 +0800
  19. d280d81 Merge tag 'v2021.04-rc4' into next by Tom Rini · Mon Mar 15 12:15:38 2021 -0400
  20. 2492d59 arm: socfpga: soc64: Support Vendor Authorized Boot (VAB) by Siew Chin Lim · Mon Mar 01 20:04:11 2021 +0800
  21. 8a71416 arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64 by Siew Chin Lim · Mon Mar 01 20:04:10 2021 +0800
  22. 6f14d5f reset: Remove addr parameter from reset_cpu() by Harald Seiler · Tue Dec 15 16:47:52 2020 +0100
  23. c984e1f arm: socfpga: Add secure register access helper functions for SoC 64bits by Siew Chin Lim · Thu Dec 24 18:21:02 2020 +0800
  24. b5ddb91 arm: socfpga: soc64: Add SMC helper function for Intel SOCFPGA (64bits) by Chee Hong Ang · Thu Dec 24 18:21:00 2020 +0800
  25. 8227bc9 arm: socfpga: fix Gen5 enable of EMAC via FPGA by Ralph Siemsen · Tue Sep 29 14:52:05 2020 -0400
  26. 69b7ab9 arm: socfpga: mailbox: Update mailbox response codes by Ley Foon Tan · Wed Aug 12 09:56:24 2020 +0800
  27. 8a98105 arm: socfpga: soc64: Document down boot_scratch_cold register usage by Chin Liang See · Mon Aug 10 10:55:56 2020 +0800
  28. 6cf193c arm: socfpga: soc64: Show reset state in SPL by Chee Hong Ang · Wed Aug 05 21:15:57 2020 +0800
  29. 75ba0aa arm: socfpga: soc64: Add SDM triggered warm reset bit mask by Chee Hong Ang · Wed Aug 05 21:15:56 2020 +0800
  30. 61e9199 arm: socfpga: soc64: Check FPGA Config status register before bridge reset by Chee Hong Ang · Thu Aug 06 11:56:29 2020 +0800
  31. ea84ae6 socfpga: Mark socfpga_fpga_add() as static inline in the non-FPGA case by Tom Rini · Thu May 14 08:30:05 2020 -0400
  32. 4dcacfc common: Drop linux/bitops.h from common header by Simon Glass · Sun May 10 11:40:13 2020 -0600
  33. 559f1a8 Use __ASSEMBLY__ as the assembly macros by Simon Glass · Sun May 10 11:40:12 2020 -0600
  34. 5d489bf arm: socfpga: stratix10: Fix incorrect CLKMGR_S10_PERPLL_BYPASS offset by Ley Foon Tan · Mon Apr 20 16:17:27 2020 +0800
  35. 8f1552e arm: socfpga: Add onchip RAM size macro by Ley Foon Tan · Fri Mar 06 16:55:18 2020 +0800
  36. 6bccacf ddr: altera: Add DDR2 support to Gen5 driver by Marek Vasut · Fri Oct 18 00:22:31 2019 +0200
  37. 6e762d8 arm: socfpga: stratix10: Enable SMMU access by Thor Thayer · Fri Dec 06 13:47:31 2019 -0600
  38. 0767f8d arm: agilex: Add clock handoff offset for Agilex by Ley Foon Tan · Wed Nov 27 15:55:25 2019 +0800
  39. b7d95b7 arm: socfpga: agilex: Add clock wrapper functions by Ley Foon Tan · Wed Nov 27 15:55:23 2019 +0800
  40. a9ebd2a arm: socfpga: Fix CLKMGR_INTOSC_HZ to 400MHz by Ley Foon Tan · Wed Nov 27 15:55:21 2019 +0800
  41. 9c25671 arm: socfpga: Move Stratix10 and Agilex clock manager common code by Ley Foon Tan · Wed Nov 27 15:55:20 2019 +0800
  42. 905bae1 arm: socfpga: agilex: Add system manager support by Ley Foon Tan · Wed Nov 27 15:55:19 2019 +0800
  43. 0b1680e arm: socfpga: Move Stratix10 and Agilex system manager common code by Ley Foon Tan · Wed Nov 27 15:55:18 2019 +0800
  44. ef9805a arm: socfpga: agilex: Add reset manager support by Ley Foon Tan · Wed Nov 27 15:55:17 2019 +0800
  45. 89700b4 arm: socfpga: Move Stratix10 and Agilex reset manager common code by Ley Foon Tan · Wed Nov 27 15:55:16 2019 +0800
  46. f1c4bd5 arm: socfpga: Move firewall code to firewall file by Ley Foon Tan · Wed Nov 27 15:55:15 2019 +0800
  47. 65d25a6 arm: socfpga: agilex: Add base address for Intel Agilex SoC by Ley Foon Tan · Wed Nov 27 15:55:14 2019 +0800
  48. 2669591 arm: socfpga: Convert clock manager from struct to defines by Ley Foon Tan · Fri Nov 08 10:38:21 2019 +0800
  49. 3d3a860 arm: socfpga: Convert system manager from struct to defines by Ley Foon Tan · Fri Nov 08 10:38:20 2019 +0800
  50. fed4c95 arm: socfpga: Convert reset manager from struct to defines by Ley Foon Tan · Fri Nov 08 10:38:19 2019 +0800
  51. 5216671 socfpga: fix include guard in misc.h (arch vs. global) by Simon Goldschmidt · Wed Oct 23 22:32:30 2019 +0200
  52. b32e1e8 arm: socfpga: rst: add register definition for cold reset by Simon Goldschmidt · Mon Jul 15 21:47:52 2019 +0200
  53. b6ba490 ARM: socfpga: Pull PL310 clearing into common code by Marek Vasut · Thu Mar 21 23:05:38 2019 +0100
  54. c8ff687 arm: sofcpga: s10: remove unused ad-hoc reset code by Simon Goldschmidt · Mon May 13 21:16:44 2019 +0200
  55. 635e250 arm: socfpga: remove re-added ad-hoc reset code by Simon Goldschmidt · Mon May 13 21:16:43 2019 +0200
  56. fe03d80 spl: socfpga: Implement fpga bitstream loading with socfpga loadfs by Tien Fong Chee · Tue May 07 17:42:30 2019 +0800
  57. ca99a8a ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading by Tien Fong Chee · Tue May 07 17:42:28 2019 +0800
  58. fadf65b ARM: socfpga: stratix10: Disable FPGA2SOC reset by Ang, Chee Hong · Fri May 03 01:19:08 2019 -0700
  59. 3fdf436 arm: socfpga: Move Stratix 10 SDRAM driver to DM by Ley Foon Tan · Mon May 06 09:56:01 2019 +0800
  60. 713a8a2 ARM: socfpga: Add support for selecting bridges in bridge command by Marek Vasut · Tue Apr 16 22:28:08 2019 +0200
  61. 79a5b2c ARM: socfpga: Factor out handoff register configuration by Marek Vasut · Tue Apr 16 23:05:24 2019 +0200
  62. 9799a67 ddr: altera: Stratix10: Add ECC memory scrubbing by Ley Foon Tan · Fri Mar 22 01:24:05 2019 +0800
  63. 3e263c7 arm: socfpga: stratix10: Add cpu_has_been_warmreset() by Ley Foon Tan · Fri Mar 22 01:24:04 2019 +0800
  64. 24910c3 arm: socfpga: move gen5 SDR driver to DM by Simon Goldschmidt · Tue Apr 16 22:04:39 2019 +0200
  65. 54d329b arm: socfpga: gen5: remove hacked ETH RST handling by Simon Goldschmidt · Sun Jan 13 19:58:42 2019 +0100
  66. ff14f16 arm: socfpga: stratix10: Add Stratix10 FPGA into FPGA device table by Ang, Chee Hong · Wed Dec 19 18:35:15 2018 -0800
  67. 11f4644 arm: socfpga: stratix10: Add macros for mailbox's arguments by Ang, Chee Hong · Wed Dec 19 18:35:13 2018 -0800
  68. 31b7963 arm: socfpga: stratix10: Add generic FPGA reconfig mailbox API for S10 by Ang, Chee Hong · Wed Dec 19 18:35:12 2018 -0800
  69. da13a0a arm: socfpga: fix SPL booting from fpga OnChip RAM by Simon Goldschmidt · Wed Oct 10 14:55:23 2018 +0200
  70. 2e75a74 arm: socfpga: Remove unused function socfpga_emac_manage_reset() by Ley Foon Tan · Fri Sep 21 00:22:14 2018 +0800
  71. 897dbd7 socfpga: stratix10: fix sdram_calculate_size by Dalon Westergreen · Tue Sep 11 10:06:14 2018 -0700
  72. 8fdb419 ARM: socfpga: Reorder Arria10 SPL by Marek Vasut · Sat Aug 18 19:11:52 2018 +0200
  73. 7ebd938 arm: socfpga: Fix SYSMGR_FPGAINTF_EMACx bit mask by Ley Foon Tan · Thu Aug 16 02:20:17 2018 +0800
  74. 71b1637 ARM: socfpga: clk: Convert to clock framework by Marek Vasut · Mon Aug 06 21:42:05 2018 +0200
  75. 40ca091 ARM: socfpga: Zap unused reset code by Marek Vasut · Mon Aug 13 18:57:08 2018 +0200
  76. 8b73c87 ARM: socfpga: Zap all the UART handling complexity by Marek Vasut · Sun Apr 15 16:29:12 2018 +0200
  77. 8e30203 arm: socfpga: gen5: combine some init code for SPL and U-Boot by Simon Goldschmidt · Mon Aug 13 21:34:35 2018 +0200
  78. f9c7f79 ddr: altera: stratix10: Add DDR support for Stratix10 SoC by Ley Foon Tan · Thu May 24 00:17:30 2018 +0800
  79. 975e496 arm: socfpga: stratix10: Add SPL driver for Stratix10 SoC by Ley Foon Tan · Thu May 24 00:17:28 2018 +0800
  80. e5b6a66 arm: socfpga: stratix10: Add mailbox support for Stratix10 SoC by Ley Foon Tan · Thu May 24 00:17:25 2018 +0800
  81. 4cc6b58 arm: socfpga: misc: Move bridge command to misc common by Ley Foon Tan · Thu May 24 00:17:23 2018 +0800
  82. 4606fc7 SPDX: Fixup SPDX tags in a few new files by Tom Rini · Sun May 20 09:47:45 2018 -0400
  83. 7cdb912 arm: socfpga: stratix10: Add pinmux support for Stratix10 SoC by Ley Foon Tan · Fri May 18 22:05:24 2018 +0800
  84. 449cbae arm: socfpga: stratix10: Add reset manager driver for Stratix10 SoC by Ley Foon Tan · Fri May 18 22:05:23 2018 +0800
  85. 6751e7d arm: socfpga: stratix10: Add clock manager driver for Stratix10 SoC by Ley Foon Tan · Fri May 18 22:05:22 2018 +0800
  86. a61fd02 arm: socfpga: stratix10: Add watchdog and firewall base addresses by Ley Foon Tan · Fri May 18 22:05:21 2018 +0800
  87. d5fba89 ARM: socfpga: Fix Documentation errors in scu_registers by Ben Kalo · Tue May 15 19:45:37 2018 +0300
  88. 402735b ARM: socfpga: Add DDR driver for Arria 10 by Tien Fong Chee · Tue Dec 05 15:58:02 2017 +0800
  89. 38fad17 ARM: socfpga: Rename the gen5 sdram driver to more specific name by Tien Fong Chee · Tue Dec 05 15:58:00 2017 +0800
  90. 3386c85 ARM: socfpga: Repair A10 EMAC reset handling by Marek Vasut · Mon Apr 23 22:49:31 2018 +0200
  91. ec472e0 ARM: socfpga: Sync A10 clock manager binding parser by Marek Vasut · Sat May 12 00:09:21 2018 +0200
  92. 0d5abc9 ARM: socfpga: Zap CONFIG_SOCFPGA_VIRTUAL_TARGET by Marek Vasut · Mon Apr 23 01:26:10 2018 +0200
  93. 323f9de ARM: socfpga: Add boot trampoline for Arria10 by Marek Vasut · Sun Apr 15 13:15:33 2018 +0200
  94. 10e4779 SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · Sun May 06 17:58:06 2018 -0400
  95. 2c828e3 arm: socfpga: stratix10: Add base address map for Statix10 SoC by Chin Liang See · Thu Mar 08 21:39:24 2018 -0600
  96. 85bd93d socfpga: boot0 hook: adjust to unified boot0 semantics by Philipp Tomsich · Tue Oct 10 16:21:07 2017 +0200
  97. 1d675f3 arm: socfpga: Add FPGA driver support for Arria 10 by Tien Fong Chee · Wed Jul 26 13:05:43 2017 +0800
  98. 31e50f4 arm: socfpga: Restructure FPGA driver in the preparation to support A10 by Tien Fong Chee · Wed Jul 26 13:05:38 2017 +0800
  99. 7b7b625 arm: socfpga: Remove unused passing parameter of socfpga_bridges_reset by Tien Fong Chee · Wed Jul 26 13:05:37 2017 +0800
  100. cfd0c54 arm: socfpga: Add misc support for Arria 10 by Ley Foon Tan · Wed Apr 26 02:44:43 2017 +0800