Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Copyright 2014 Freescale Semiconductor, Inc. |
Gaurav Jain | 476c639 | 2022-03-24 11:50:35 +0530 | [diff] [blame] | 4 | * Copyright 2019, 2021 NXP |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <common.h> |
Simon Glass | 85d6531 | 2019-12-28 10:44:58 -0700 | [diff] [blame] | 8 | #include <clock_legacy.h> |
Simon Glass | 3bbe70c | 2019-12-28 10:44:54 -0700 | [diff] [blame] | 9 | #include <fdt_support.h> |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 10 | #include <i2c.h> |
Simon Glass | a7b5130 | 2019-11-14 12:57:46 -0700 | [diff] [blame] | 11 | #include <init.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 12 | #include <log.h> |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 13 | #include <asm/io.h> |
| 14 | #include <asm/arch/immap_ls102xa.h> |
| 15 | #include <asm/arch/clock.h> |
| 16 | #include <asm/arch/fsl_serdes.h> |
Yao Yuan | e0f8f54 | 2015-12-05 14:59:10 +0800 | [diff] [blame] | 17 | #include <asm/arch/ls102xa_soc.h> |
Zhuoyu Zhang | fe4f288 | 2015-08-17 18:55:12 +0800 | [diff] [blame] | 18 | #include <asm/arch/ls102xa_devdis.h> |
Shiji Yang | bb11234 | 2023-08-03 09:47:16 +0800 | [diff] [blame] | 19 | #include <asm/sections.h> |
Yao Yuan | fec6aa0 | 2014-11-26 14:54:33 +0800 | [diff] [blame] | 20 | #include <hwconfig.h> |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 21 | #include <mmc.h> |
Mingkai Hu | 5b0df8a | 2015-10-26 19:47:41 +0800 | [diff] [blame] | 22 | #include <fsl_csu.h> |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 23 | #include <fsl_ifc.h> |
Alison Wang | 9da5178 | 2014-12-03 15:00:47 +0800 | [diff] [blame] | 24 | #include <spl.h> |
Zhuoyu Zhang | fe4f288 | 2015-08-17 18:55:12 +0800 | [diff] [blame] | 25 | #include <fsl_devdis.h> |
Aneesh Bansal | 39d5b3b | 2016-01-22 16:37:26 +0530 | [diff] [blame] | 26 | #include <fsl_validate.h> |
Shengzhou Liu | 15875a5 | 2016-11-21 11:36:48 +0800 | [diff] [blame] | 27 | #include <fsl_ddr.h> |
Stephen Carlson | f179092 | 2021-06-22 16:38:21 -0700 | [diff] [blame] | 28 | #include "../common/i2c_mux.h" |
tang yuantian | 57296e7 | 2014-12-17 12:58:05 +0800 | [diff] [blame] | 29 | #include "../common/sleep.h" |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 30 | #include "../common/qixis.h" |
| 31 | #include "ls1021aqds_qixis.h" |
Zhao Qiang | 9fc2f30 | 2014-09-26 16:25:32 +0800 | [diff] [blame] | 32 | #ifdef CONFIG_U_QE |
Qianyu Gong | ae6a758 | 2016-02-18 13:01:59 +0800 | [diff] [blame] | 33 | #include <fsl_qe.h> |
Zhao Qiang | 9fc2f30 | 2014-09-26 16:25:32 +0800 | [diff] [blame] | 34 | #endif |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 35 | |
Yao Yuan | fec6aa0 | 2014-11-26 14:54:33 +0800 | [diff] [blame] | 36 | #define PIN_MUX_SEL_CAN 0x03 |
| 37 | #define PIN_MUX_SEL_IIC2 0xa0 |
| 38 | #define PIN_MUX_SEL_RGMII 0x00 |
| 39 | #define PIN_MUX_SEL_SAI 0x0c |
| 40 | #define PIN_MUX_SEL_SDHC 0x00 |
| 41 | |
| 42 | #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0x0f) | value) |
| 43 | #define SET_EC_MUX_SEL(reg, value) ((reg & 0xf0) | value) |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 44 | enum { |
Yao Yuan | fec6aa0 | 2014-11-26 14:54:33 +0800 | [diff] [blame] | 45 | MUX_TYPE_CAN, |
| 46 | MUX_TYPE_IIC2, |
| 47 | MUX_TYPE_RGMII, |
| 48 | MUX_TYPE_SAI, |
| 49 | MUX_TYPE_SDHC, |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 50 | MUX_TYPE_SD_PCI4, |
| 51 | MUX_TYPE_SD_PC_SA_SG_SG, |
| 52 | MUX_TYPE_SD_PC_SA_PC_SG, |
| 53 | MUX_TYPE_SD_PC_SG_SG, |
| 54 | }; |
| 55 | |
Alison Wang | 29d7543 | 2014-12-09 17:38:23 +0800 | [diff] [blame] | 56 | enum { |
| 57 | GE0_CLK125, |
| 58 | GE2_CLK125, |
| 59 | GE1_CLK125, |
| 60 | }; |
| 61 | |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 62 | int checkboard(void) |
| 63 | { |
Alison Wang | 34de5e4 | 2016-02-02 15:16:23 +0800 | [diff] [blame] | 64 | #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 65 | char buf[64]; |
Alison Wang | 2145a37 | 2014-12-09 17:38:02 +0800 | [diff] [blame] | 66 | #endif |
Alison Wang | 9da5178 | 2014-12-03 15:00:47 +0800 | [diff] [blame] | 67 | #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT) |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 68 | u8 sw; |
Alison Wang | 9da5178 | 2014-12-03 15:00:47 +0800 | [diff] [blame] | 69 | #endif |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 70 | |
| 71 | puts("Board: LS1021AQDS\n"); |
| 72 | |
Alison Wang | 9da5178 | 2014-12-03 15:00:47 +0800 | [diff] [blame] | 73 | #ifdef CONFIG_SD_BOOT |
| 74 | puts("SD\n"); |
| 75 | #elif CONFIG_QSPI_BOOT |
| 76 | puts("QSPI\n"); |
| 77 | #else |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 78 | sw = QIXIS_READ(brdcfg[0]); |
| 79 | sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; |
| 80 | |
| 81 | if (sw < 0x8) |
| 82 | printf("vBank: %d\n", sw); |
| 83 | else if (sw == 0x8) |
| 84 | puts("PromJet\n"); |
| 85 | else if (sw == 0x9) |
| 86 | puts("NAND\n"); |
| 87 | else if (sw == 0x15) |
| 88 | printf("IFCCard\n"); |
| 89 | else |
| 90 | printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); |
Alison Wang | 9da5178 | 2014-12-03 15:00:47 +0800 | [diff] [blame] | 91 | #endif |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 92 | |
Alison Wang | 34de5e4 | 2016-02-02 15:16:23 +0800 | [diff] [blame] | 93 | #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 94 | printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n", |
| 95 | QIXIS_READ(id), QIXIS_READ(arch)); |
| 96 | |
| 97 | printf("FPGA: v%d (%s), build %d\n", |
| 98 | (int)QIXIS_READ(scver), qixis_read_tag(buf), |
| 99 | (int)qixis_read_minor()); |
Alison Wang | 2145a37 | 2014-12-09 17:38:02 +0800 | [diff] [blame] | 100 | #endif |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 101 | |
| 102 | return 0; |
| 103 | } |
| 104 | |
Tom Rini | aea2a99 | 2021-12-14 13:36:39 -0500 | [diff] [blame] | 105 | #ifdef CONFIG_DYNAMIC_SYS_CLK_FREQ |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 106 | unsigned long get_board_sys_clk(void) |
| 107 | { |
| 108 | u8 sysclk_conf = QIXIS_READ(brdcfg[1]); |
| 109 | |
| 110 | switch (sysclk_conf & 0x0f) { |
| 111 | case QIXIS_SYSCLK_64: |
| 112 | return 64000000; |
| 113 | case QIXIS_SYSCLK_83: |
| 114 | return 83333333; |
| 115 | case QIXIS_SYSCLK_100: |
| 116 | return 100000000; |
| 117 | case QIXIS_SYSCLK_125: |
| 118 | return 125000000; |
| 119 | case QIXIS_SYSCLK_133: |
| 120 | return 133333333; |
| 121 | case QIXIS_SYSCLK_150: |
| 122 | return 150000000; |
| 123 | case QIXIS_SYSCLK_160: |
| 124 | return 160000000; |
| 125 | case QIXIS_SYSCLK_166: |
| 126 | return 166666666; |
| 127 | } |
| 128 | return 66666666; |
| 129 | } |
Tom Rini | aea2a99 | 2021-12-14 13:36:39 -0500 | [diff] [blame] | 130 | #endif |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 131 | |
Tom Rini | f7246c2 | 2021-08-21 13:50:17 -0400 | [diff] [blame] | 132 | #ifdef CONFIG_DYNAMIC_DDR_CLK_FREQ |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 133 | unsigned long get_board_ddr_clk(void) |
| 134 | { |
| 135 | u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); |
| 136 | |
| 137 | switch ((ddrclk_conf & 0x30) >> 4) { |
| 138 | case QIXIS_DDRCLK_100: |
| 139 | return 100000000; |
| 140 | case QIXIS_DDRCLK_125: |
| 141 | return 125000000; |
| 142 | case QIXIS_DDRCLK_133: |
| 143 | return 133333333; |
| 144 | } |
| 145 | return 66666666; |
| 146 | } |
Tom Rini | f7246c2 | 2021-08-21 13:50:17 -0400 | [diff] [blame] | 147 | #endif |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 148 | |
| 149 | int dram_init(void) |
| 150 | { |
Chenhui Zhao | 5096694 | 2014-11-06 10:51:59 +0800 | [diff] [blame] | 151 | /* |
| 152 | * When resuming from deep sleep, the I2C channel may not be |
| 153 | * in the default channel. So, switch to the default channel |
| 154 | * before accessing DDR SPD. |
Biwen Li | d15aa9f | 2019-12-31 15:33:44 +0800 | [diff] [blame] | 155 | * |
| 156 | * PCA9547(0x77) mount on I2C1 bus |
Chenhui Zhao | 5096694 | 2014-11-06 10:51:59 +0800 | [diff] [blame] | 157 | */ |
Biwen Li | d15aa9f | 2019-12-31 15:33:44 +0800 | [diff] [blame] | 158 | select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); |
Simon Glass | 0e0ac20 | 2017-04-06 12:47:04 -0600 | [diff] [blame] | 159 | return fsl_initdram(); |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 160 | } |
| 161 | |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 162 | int board_early_init_f(void) |
| 163 | { |
Tom Rini | 376b88a | 2022-10-28 20:27:13 -0400 | [diff] [blame] | 164 | struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 165 | |
| 166 | #ifdef CONFIG_TSEC_ENET |
Claudiu Manoil | 51b503e | 2015-08-12 13:29:14 +0300 | [diff] [blame] | 167 | /* clear BD & FR bits for BE BD's and frame data */ |
| 168 | clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 169 | #endif |
| 170 | |
| 171 | #ifdef CONFIG_FSL_IFC |
| 172 | init_early_memctl_regs(); |
| 173 | #endif |
| 174 | |
Yao Yuan | e0f8f54 | 2015-12-05 14:59:10 +0800 | [diff] [blame] | 175 | arch_soc_init(); |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 176 | |
tang yuantian | 57296e7 | 2014-12-17 12:58:05 +0800 | [diff] [blame] | 177 | #if defined(CONFIG_DEEP_SLEEP) |
| 178 | if (is_warm_boot()) |
| 179 | fsl_dp_disable_console(); |
| 180 | #endif |
| 181 | |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 182 | return 0; |
| 183 | } |
Alison Wang | 9da5178 | 2014-12-03 15:00:47 +0800 | [diff] [blame] | 184 | |
| 185 | #ifdef CONFIG_SPL_BUILD |
| 186 | void board_init_f(ulong dummy) |
| 187 | { |
Alison Wang | ab98bb5 | 2014-12-09 17:38:14 +0800 | [diff] [blame] | 188 | #ifdef CONFIG_NAND_BOOT |
Tom Rini | 376b88a | 2022-10-28 20:27:13 -0400 | [diff] [blame] | 189 | struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; |
Alison Wang | ab98bb5 | 2014-12-09 17:38:14 +0800 | [diff] [blame] | 190 | u32 porsr1, pinctl; |
| 191 | |
| 192 | /* |
| 193 | * There is LS1 SoC issue where NOR, FPGA are inaccessible during |
| 194 | * NAND boot because IFC signals > IFC_AD7 are not enabled. |
| 195 | * This workaround changes RCW source to make all signals enabled. |
| 196 | */ |
| 197 | porsr1 = in_be32(&gur->porsr1); |
| 198 | pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) | |
| 199 | DCFG_CCSR_PORSR1_RCW_SRC_I2C); |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 200 | out_be32((unsigned int *)(CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), |
Alison Wang | ab98bb5 | 2014-12-09 17:38:14 +0800 | [diff] [blame] | 201 | pinctl); |
| 202 | #endif |
| 203 | |
Alison Wang | 9da5178 | 2014-12-03 15:00:47 +0800 | [diff] [blame] | 204 | /* Clear the BSS */ |
| 205 | memset(__bss_start, 0, __bss_end - __bss_start); |
| 206 | |
| 207 | #ifdef CONFIG_FSL_IFC |
| 208 | init_early_memctl_regs(); |
| 209 | #endif |
| 210 | |
| 211 | get_clocks(); |
| 212 | |
tang yuantian | 57296e7 | 2014-12-17 12:58:05 +0800 | [diff] [blame] | 213 | #if defined(CONFIG_DEEP_SLEEP) |
| 214 | if (is_warm_boot()) |
| 215 | fsl_dp_disable_console(); |
| 216 | #endif |
| 217 | |
Alison Wang | 9da5178 | 2014-12-03 15:00:47 +0800 | [diff] [blame] | 218 | preloader_console_init(); |
| 219 | |
Simon Glass | bccfc2e | 2021-07-10 21:14:36 -0600 | [diff] [blame] | 220 | #ifdef CONFIG_SPL_I2C |
Alison Wang | 9da5178 | 2014-12-03 15:00:47 +0800 | [diff] [blame] | 221 | i2c_init_all(); |
| 222 | #endif |
Alison Wang | 6027eb4 | 2015-03-12 11:31:44 +0800 | [diff] [blame] | 223 | |
Alison Wang | 2825303 | 2018-10-16 16:19:22 +0800 | [diff] [blame] | 224 | timer_init(); |
Alison Wang | 9da5178 | 2014-12-03 15:00:47 +0800 | [diff] [blame] | 225 | dram_init(); |
| 226 | |
Alison Wang | 5dec9d7 | 2015-07-09 10:50:07 +0800 | [diff] [blame] | 227 | /* Allow OCRAM access permission as R/W */ |
Mingkai Hu | 5b0df8a | 2015-10-26 19:47:41 +0800 | [diff] [blame] | 228 | #ifdef CONFIG_LAYERSCAPE_NS_ACCESS |
| 229 | enable_layerscape_ns_access(); |
Alison Wang | 5dec9d7 | 2015-07-09 10:50:07 +0800 | [diff] [blame] | 230 | #endif |
| 231 | |
Alison Wang | 9da5178 | 2014-12-03 15:00:47 +0800 | [diff] [blame] | 232 | board_init_r(NULL, 0); |
| 233 | } |
| 234 | #endif |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 235 | |
Alison Wang | 29d7543 | 2014-12-09 17:38:23 +0800 | [diff] [blame] | 236 | void config_etseccm_source(int etsec_gtx_125_mux) |
| 237 | { |
Tom Rini | 376b88a | 2022-10-28 20:27:13 -0400 | [diff] [blame] | 238 | struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; |
Alison Wang | 29d7543 | 2014-12-09 17:38:23 +0800 | [diff] [blame] | 239 | |
| 240 | switch (etsec_gtx_125_mux) { |
| 241 | case GE0_CLK125: |
| 242 | out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125); |
| 243 | debug("etseccm set to GE0_CLK125\n"); |
| 244 | break; |
| 245 | |
| 246 | case GE2_CLK125: |
| 247 | out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); |
| 248 | debug("etseccm set to GE2_CLK125\n"); |
| 249 | break; |
| 250 | |
| 251 | case GE1_CLK125: |
| 252 | out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125); |
| 253 | debug("etseccm set to GE1_CLK125\n"); |
| 254 | break; |
| 255 | |
| 256 | default: |
| 257 | printf("Error! trying to set etseccm to invalid value\n"); |
| 258 | break; |
| 259 | } |
| 260 | } |
| 261 | |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 262 | int config_board_mux(int ctrl_type) |
| 263 | { |
Yao Yuan | fec6aa0 | 2014-11-26 14:54:33 +0800 | [diff] [blame] | 264 | u8 reg12, reg14; |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 265 | |
| 266 | reg12 = QIXIS_READ(brdcfg[12]); |
Yao Yuan | fec6aa0 | 2014-11-26 14:54:33 +0800 | [diff] [blame] | 267 | reg14 = QIXIS_READ(brdcfg[14]); |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 268 | |
| 269 | switch (ctrl_type) { |
Yao Yuan | fec6aa0 | 2014-11-26 14:54:33 +0800 | [diff] [blame] | 270 | case MUX_TYPE_CAN: |
Alison Wang | 29d7543 | 2014-12-09 17:38:23 +0800 | [diff] [blame] | 271 | config_etseccm_source(GE2_CLK125); |
Yao Yuan | fec6aa0 | 2014-11-26 14:54:33 +0800 | [diff] [blame] | 272 | reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN); |
| 273 | break; |
| 274 | case MUX_TYPE_IIC2: |
| 275 | reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2); |
| 276 | break; |
| 277 | case MUX_TYPE_RGMII: |
| 278 | reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII); |
| 279 | break; |
| 280 | case MUX_TYPE_SAI: |
Alison Wang | 29d7543 | 2014-12-09 17:38:23 +0800 | [diff] [blame] | 281 | config_etseccm_source(GE2_CLK125); |
Yao Yuan | fec6aa0 | 2014-11-26 14:54:33 +0800 | [diff] [blame] | 282 | reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI); |
| 283 | break; |
| 284 | case MUX_TYPE_SDHC: |
| 285 | reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC); |
| 286 | break; |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 287 | case MUX_TYPE_SD_PCI4: |
| 288 | reg12 = 0x38; |
| 289 | break; |
| 290 | case MUX_TYPE_SD_PC_SA_SG_SG: |
| 291 | reg12 = 0x01; |
| 292 | break; |
| 293 | case MUX_TYPE_SD_PC_SA_PC_SG: |
| 294 | reg12 = 0x01; |
| 295 | break; |
| 296 | case MUX_TYPE_SD_PC_SG_SG: |
| 297 | reg12 = 0x21; |
| 298 | break; |
| 299 | default: |
| 300 | printf("Wrong mux interface type\n"); |
| 301 | return -1; |
| 302 | } |
| 303 | |
| 304 | QIXIS_WRITE(brdcfg[12], reg12); |
Yao Yuan | fec6aa0 | 2014-11-26 14:54:33 +0800 | [diff] [blame] | 305 | QIXIS_WRITE(brdcfg[14], reg14); |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 306 | |
| 307 | return 0; |
| 308 | } |
| 309 | |
| 310 | int config_serdes_mux(void) |
| 311 | { |
Tom Rini | 376b88a | 2022-10-28 20:27:13 -0400 | [diff] [blame] | 312 | struct ccsr_gur *gur = (struct ccsr_gur *)CFG_SYS_FSL_GUTS_ADDR; |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 313 | u32 cfg; |
| 314 | |
| 315 | cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK; |
| 316 | cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT; |
| 317 | |
| 318 | switch (cfg) { |
| 319 | case 0x0: |
| 320 | config_board_mux(MUX_TYPE_SD_PCI4); |
| 321 | break; |
| 322 | case 0x30: |
| 323 | config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG); |
| 324 | break; |
| 325 | case 0x60: |
| 326 | config_board_mux(MUX_TYPE_SD_PC_SG_SG); |
| 327 | break; |
| 328 | case 0x70: |
| 329 | config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG); |
| 330 | break; |
| 331 | default: |
| 332 | printf("SRDS1 prtcl:0x%x\n", cfg); |
| 333 | break; |
| 334 | } |
| 335 | |
| 336 | return 0; |
| 337 | } |
| 338 | |
tang yuantian | 9f51db2 | 2015-10-16 16:06:05 +0800 | [diff] [blame] | 339 | #ifdef CONFIG_BOARD_LATE_INIT |
| 340 | int board_late_init(void) |
| 341 | { |
Aneesh Bansal | 39d5b3b | 2016-01-22 16:37:26 +0530 | [diff] [blame] | 342 | #ifdef CONFIG_CHAIN_OF_TRUST |
| 343 | fsl_setenv_chain_of_trust(); |
| 344 | #endif |
tang yuantian | 9f51db2 | 2015-10-16 16:06:05 +0800 | [diff] [blame] | 345 | |
| 346 | return 0; |
| 347 | } |
| 348 | #endif |
| 349 | |
Ruchika Gupta | 901ae76 | 2014-10-15 11:39:06 +0530 | [diff] [blame] | 350 | int misc_init_r(void) |
| 351 | { |
Yao Yuan | fec6aa0 | 2014-11-26 14:54:33 +0800 | [diff] [blame] | 352 | int conflict_flag; |
| 353 | |
| 354 | /* some signals can not enable simultaneous*/ |
| 355 | conflict_flag = 0; |
| 356 | if (hwconfig("sdhc")) |
| 357 | conflict_flag++; |
| 358 | if (hwconfig("iic2")) |
| 359 | conflict_flag++; |
| 360 | if (conflict_flag > 1) { |
| 361 | printf("WARNING: pin conflict !\n"); |
| 362 | return 0; |
| 363 | } |
| 364 | |
| 365 | conflict_flag = 0; |
| 366 | if (hwconfig("rgmii")) |
| 367 | conflict_flag++; |
| 368 | if (hwconfig("can")) |
| 369 | conflict_flag++; |
| 370 | if (hwconfig("sai")) |
| 371 | conflict_flag++; |
| 372 | if (conflict_flag > 1) { |
| 373 | printf("WARNING: pin conflict !\n"); |
| 374 | return 0; |
| 375 | } |
| 376 | |
| 377 | if (hwconfig("can")) |
| 378 | config_board_mux(MUX_TYPE_CAN); |
| 379 | else if (hwconfig("rgmii")) |
| 380 | config_board_mux(MUX_TYPE_RGMII); |
| 381 | else if (hwconfig("sai")) |
| 382 | config_board_mux(MUX_TYPE_SAI); |
| 383 | |
| 384 | if (hwconfig("iic2")) |
| 385 | config_board_mux(MUX_TYPE_IIC2); |
| 386 | else if (hwconfig("sdhc")) |
| 387 | config_board_mux(MUX_TYPE_SDHC); |
| 388 | |
Zhuoyu Zhang | fe4f288 | 2015-08-17 18:55:12 +0800 | [diff] [blame] | 389 | #ifdef CONFIG_FSL_DEVICE_DISABLE |
| 390 | device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl)); |
| 391 | #endif |
Yao Yuan | fec6aa0 | 2014-11-26 14:54:33 +0800 | [diff] [blame] | 392 | return 0; |
Ruchika Gupta | 901ae76 | 2014-10-15 11:39:06 +0530 | [diff] [blame] | 393 | } |
Ruchika Gupta | 901ae76 | 2014-10-15 11:39:06 +0530 | [diff] [blame] | 394 | |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 395 | int board_init(void) |
| 396 | { |
Hou Zhiqiang | 4b23ca8 | 2016-08-02 19:03:27 +0800 | [diff] [blame] | 397 | #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 |
| 398 | erratum_a010315(); |
| 399 | #endif |
Shengzhou Liu | 15875a5 | 2016-11-21 11:36:48 +0800 | [diff] [blame] | 400 | #ifdef CONFIG_SYS_FSL_ERRATUM_A009942 |
| 401 | erratum_a009942_check_cpo(); |
| 402 | #endif |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 403 | |
Biwen Li | d15aa9f | 2019-12-31 15:33:44 +0800 | [diff] [blame] | 404 | select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 405 | |
| 406 | #ifndef CONFIG_SYS_FSL_NO_SERDES |
| 407 | fsl_serdes_init(); |
| 408 | config_serdes_mux(); |
| 409 | #endif |
Zhao Qiang | 9fc2f30 | 2014-09-26 16:25:32 +0800 | [diff] [blame] | 410 | |
Alison Wang | 6936492 | 2016-02-05 12:48:17 +0800 | [diff] [blame] | 411 | ls102xa_smmu_stream_id_init(); |
Xiubo Li | 03d40aa | 2014-11-21 17:40:59 +0800 | [diff] [blame] | 412 | |
Zhao Qiang | 9fc2f30 | 2014-09-26 16:25:32 +0800 | [diff] [blame] | 413 | #ifdef CONFIG_U_QE |
| 414 | u_qe_init(); |
| 415 | #endif |
| 416 | |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 417 | return 0; |
| 418 | } |
tang yuantian | 57296e7 | 2014-12-17 12:58:05 +0800 | [diff] [blame] | 419 | |
| 420 | #if defined(CONFIG_DEEP_SLEEP) |
| 421 | void board_sleep_prepare(void) |
| 422 | { |
Mingkai Hu | 5b0df8a | 2015-10-26 19:47:41 +0800 | [diff] [blame] | 423 | #ifdef CONFIG_LAYERSCAPE_NS_ACCESS |
| 424 | enable_layerscape_ns_access(); |
tang yuantian | 57296e7 | 2014-12-17 12:58:05 +0800 | [diff] [blame] | 425 | #endif |
| 426 | } |
| 427 | #endif |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 428 | |
Masahiro Yamada | f7ed78b | 2020-06-26 15:13:33 +0900 | [diff] [blame] | 429 | int ft_board_setup(void *blob, struct bd_info *bd) |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 430 | { |
| 431 | ft_cpu_setup(blob, bd); |
Simon Glass | 2aec3cc | 2014-10-23 18:58:47 -0600 | [diff] [blame] | 432 | |
Minghuan Lian | 0c53524 | 2015-03-12 10:58:48 +0800 | [diff] [blame] | 433 | #ifdef CONFIG_PCI |
| 434 | ft_pci_setup(blob, bd); |
Minghuan Lian | a4d6b61 | 2014-10-31 13:43:44 +0800 | [diff] [blame] | 435 | #endif |
| 436 | |
Simon Glass | 2aec3cc | 2014-10-23 18:58:47 -0600 | [diff] [blame] | 437 | return 0; |
Wang Huan | f0ce7d6 | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 438 | } |
| 439 | |
| 440 | u8 flash_read8(void *addr) |
| 441 | { |
| 442 | return __raw_readb(addr + 1); |
| 443 | } |
| 444 | |
| 445 | void flash_write16(u16 val, void *addr) |
| 446 | { |
| 447 | u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); |
| 448 | |
| 449 | __raw_writew(shftval, addr); |
| 450 | } |
| 451 | |
| 452 | u16 flash_read16(void *addr) |
| 453 | { |
| 454 | u16 val = __raw_readw(addr); |
| 455 | |
| 456 | return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); |
| 457 | } |