| Simon Glass | b94dc89 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 1 | menu "PCI" |
| 2 | |
| 3 | config DM_PCI |
| 4 | bool "Enable driver mode for PCI" |
| 5 | depends on DM |
| 6 | help |
| 7 | Use driver model for PCI. Driver model is the new method for |
| 8 | orgnising devices in U-Boot. For PCI, driver model keeps track of |
| 9 | available PCI devices, allows scanning of PCI buses and provides |
| 10 | device configuration support. |
| 11 | |
| Simon Glass | eca7b0d | 2015-11-26 19:51:30 -0700 | [diff] [blame] | 12 | config DM_PCI_COMPAT |
| 13 | bool "Enable compatible functions for PCI" |
| 14 | depends on DM_PCI |
| 15 | help |
| 16 | Enable compatibility functions for PCI so that old code can be used |
| 17 | with CONFIG_DM_PCI enabled. This should be used as an interim |
| 18 | measure when porting a board to use driver model for PCI. Once the |
| 19 | board is fully supported, this option should be disabled. |
| 20 | |
| Simon Glass | 4d85755 | 2015-03-05 12:25:27 -0700 | [diff] [blame] | 21 | config PCI_SANDBOX |
| 22 | bool "Sandbox PCI support" |
| 23 | depends on SANDBOX && DM_PCI |
| 24 | help |
| 25 | Support PCI on sandbox, as an emulated bus. This permits testing of |
| 26 | PCI feature such as bus scanning, device configuration and device |
| 27 | access. The available (emulated) devices are defined statically in |
| 28 | the device tree but the normal PCI scan technique is used to find |
| 29 | then. |
| 30 | |
| Simon Glass | c78e327 | 2015-11-19 20:26:55 -0700 | [diff] [blame] | 31 | config PCI_TEGRA |
| 32 | bool "Tegra PCI support" |
| 33 | depends on TEGRA |
| Stephen Warren | 86f6a94 | 2016-08-05 16:10:34 -0600 | [diff] [blame] | 34 | depends on (TEGRA186 && POWER_DOMAIN) || (!TEGRA186) |
| Simon Glass | c78e327 | 2015-11-19 20:26:55 -0700 | [diff] [blame] | 35 | help |
| 36 | Enable support for the PCIe controller found on some generations of |
| 37 | Tegra. Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has |
| 38 | 3 root ports with a total of 6 lanes and Tegra124 has 2 root ports |
| 39 | with a total of 5 lanes. Some boards require this for Ethernet |
| 40 | support to work (e.g. beaver, jetson-tk1). |
| 41 | |
| Paul Burton | c893f21 | 2016-09-08 07:47:31 +0100 | [diff] [blame] | 42 | config PCI_XILINX |
| 43 | bool "Xilinx AXI Bridge for PCI Express" |
| 44 | depends on DM_PCI |
| 45 | help |
| 46 | Enable support for the Xilinx AXI bridge for PCI express, an IP block |
| 47 | which can be used on some generations of Xilinx FPGAs. |
| 48 | |
| Simon Glass | b94dc89 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 49 | endmenu |