wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 1 | /* |
wdenk | 1ebf41e | 2004-01-02 14:00:00 +0000 | [diff] [blame] | 2 | * (C) Copyright 2000-2004 |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #include <common.h> |
| 9 | #include <mpc8xx.h> |
| 10 | #include <asm/processor.h> |
| 11 | |
Wolfgang Denk | 6405a15 | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 12 | DECLARE_GLOBAL_DATA_PTR; |
| 13 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 14 | #if !defined(CONFIG_8xx_CPUCLK_DEFAULT) || defined(CONFIG_SYS_MEASURE_CPUCLK) || defined(DEBUG) |
wdenk | b50cde5 | 2004-01-24 20:25:54 +0000 | [diff] [blame] | 15 | |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 16 | #define PITC_SHIFT 16 |
| 17 | #define PITR_SHIFT 16 |
| 18 | /* pitc values to time for 58/8192 seconds (about 70.8 milliseconds) */ |
| 19 | #define SPEED_PIT_COUNTS 58 |
| 20 | #define SPEED_PITC ((SPEED_PIT_COUNTS - 1) << PITC_SHIFT) |
| 21 | #define SPEED_PITC_INIT ((SPEED_PIT_COUNTS + 1) << PITC_SHIFT) |
| 22 | |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 23 | /* Access functions for the Machine State Register */ |
| 24 | static __inline__ unsigned long get_msr(void) |
| 25 | { |
| 26 | unsigned long msr; |
| 27 | |
| 28 | asm volatile("mfmsr %0" : "=r" (msr) :); |
| 29 | return msr; |
| 30 | } |
| 31 | |
| 32 | static __inline__ void set_msr(unsigned long msr) |
| 33 | { |
| 34 | asm volatile("mtmsr %0" : : "r" (msr)); |
| 35 | } |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 36 | |
| 37 | /* ------------------------------------------------------------------------- */ |
| 38 | |
| 39 | /* |
| 40 | * Measure CPU clock speed (core clock GCLK1, GCLK2), |
| 41 | * also determine bus clock speed (checking bus divider factor) |
| 42 | * |
| 43 | * (Approx. GCLK frequency in Hz) |
| 44 | * |
| 45 | * Initializes timer 2 and PIT, but disables them before return. |
| 46 | * [Use timer 2, because MPC823 CPUs mask 0.x do not have timers 3 and 4] |
| 47 | * |
| 48 | * When measuring the CPU clock against the PIT, we count cpu clocks |
| 49 | * for 58/8192 seconds with a prescale divide by 177 for the cpu clock. |
| 50 | * These strange values for the timing interval and prescaling are used |
| 51 | * because the formula for the CPU clock is: |
| 52 | * |
wdenk | 88d73b5 | 2004-02-11 21:35:18 +0000 | [diff] [blame] | 53 | * CPU clock = count * (177 * (8192 / 58)) |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 54 | * |
wdenk | 88d73b5 | 2004-02-11 21:35:18 +0000 | [diff] [blame] | 55 | * = count * 24999.7241 |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 56 | * |
wdenk | 88d73b5 | 2004-02-11 21:35:18 +0000 | [diff] [blame] | 57 | * which is very close to |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 58 | * |
wdenk | 88d73b5 | 2004-02-11 21:35:18 +0000 | [diff] [blame] | 59 | * = count * 25000 |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 60 | * |
| 61 | * Since the count gives the CPU clock divided by 25000, we can get |
| 62 | * the CPU clock rounded to the nearest 0.1 MHz by |
| 63 | * |
wdenk | 88d73b5 | 2004-02-11 21:35:18 +0000 | [diff] [blame] | 64 | * CPU clock = ((count + 2) / 4) * 100000; |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 65 | * |
| 66 | * The rounding is important since the measurement is sometimes going |
| 67 | * to be high or low by 0.025 MHz, depending on exactly how the clocks |
| 68 | * and counters interact. By rounding we get the exact answer for any |
| 69 | * CPU clock that is an even multiple of 0.1 MHz. |
| 70 | */ |
| 71 | |
wdenk | 2bb1105 | 2003-07-17 23:16:40 +0000 | [diff] [blame] | 72 | unsigned long measure_gclk(void) |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 73 | { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 74 | volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 75 | volatile cpmtimer8xx_t *timerp = &immr->im_cpmtimer; |
| 76 | ulong timer2_val; |
| 77 | ulong msr_val; |
| 78 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 79 | #ifdef CONFIG_SYS_8XX_XIN |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 80 | /* dont use OSCM, only use EXTCLK/512 */ |
| 81 | immr->im_clkrst.car_sccr |= SCCR_RTSEL | SCCR_RTDIV; |
wdenk | 2bb1105 | 2003-07-17 23:16:40 +0000 | [diff] [blame] | 82 | #else |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 83 | immr->im_clkrst.car_sccr &= ~(SCCR_RTSEL | SCCR_RTDIV); |
wdenk | 2bb1105 | 2003-07-17 23:16:40 +0000 | [diff] [blame] | 84 | #endif |
| 85 | |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 86 | /* Reset + Stop Timer 2, no cascading |
| 87 | */ |
| 88 | timerp->cpmt_tgcr &= ~(TGCR_CAS2 | TGCR_RST2); |
| 89 | |
| 90 | /* Keep stopped, halt in debug mode |
| 91 | */ |
| 92 | timerp->cpmt_tgcr |= (TGCR_FRZ2 | TGCR_STP2); |
| 93 | |
| 94 | /* Timer 2 setup: |
| 95 | * Output ref. interrupt disable, int. clock |
| 96 | * Prescale by 177. Note that prescaler divides by value + 1 |
| 97 | * so we must subtract 1 here. |
| 98 | */ |
| 99 | timerp->cpmt_tmr2 = ((177 - 1) << TMR_PS_SHIFT) | TMR_ICLK_IN_GEN; |
| 100 | |
wdenk | 88d73b5 | 2004-02-11 21:35:18 +0000 | [diff] [blame] | 101 | timerp->cpmt_tcn2 = 0; /* reset state */ |
| 102 | timerp->cpmt_tgcr |= TGCR_RST2; /* enable timer 2 */ |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 103 | |
| 104 | /* |
| 105 | * PIT setup: |
| 106 | * |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 107 | * We want to time for SPEED_PITC_COUNTS counts (of 8192 Hz), |
| 108 | * so the count value would be SPEED_PITC_COUNTS - 1. |
| 109 | * But there would be an uncertainty in the start time of 1/4 |
| 110 | * count since when we enable the PIT the count is not |
| 111 | * synchronized to the 32768 Hz oscillator. The trick here is |
| 112 | * to start the count higher and wait until the PIT count |
| 113 | * changes to the required value before starting timer 2. |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 114 | * |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 115 | * One count high should be enough, but occasionally the start |
| 116 | * is off by 1 or 2 counts of 32768 Hz. With the start value |
| 117 | * set two counts high it seems very reliable. |
| 118 | */ |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 119 | |
| 120 | immr->im_sitk.sitk_pitck = KAPWR_KEY; /* PIT initialization */ |
| 121 | immr->im_sit.sit_pitc = SPEED_PITC_INIT; |
| 122 | |
| 123 | immr->im_sitk.sitk_piscrk = KAPWR_KEY; |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 124 | immr->im_sit.sit_piscr = CONFIG_SYS_PISCR; |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 125 | |
| 126 | /* |
| 127 | * Start measurement - disable interrupts, just in case |
| 128 | */ |
| 129 | msr_val = get_msr (); |
| 130 | set_msr (msr_val & ~MSR_EE); |
| 131 | |
| 132 | immr->im_sit.sit_piscr |= PISCR_PTE; |
| 133 | |
| 134 | /* spin until get exact count when we want to start */ |
| 135 | while (immr->im_sit.sit_pitr > SPEED_PITC); |
| 136 | |
wdenk | 88d73b5 | 2004-02-11 21:35:18 +0000 | [diff] [blame] | 137 | timerp->cpmt_tgcr &= ~TGCR_STP2; /* Start Timer 2 */ |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 138 | while ((immr->im_sit.sit_piscr & PISCR_PS) == 0); |
wdenk | 88d73b5 | 2004-02-11 21:35:18 +0000 | [diff] [blame] | 139 | timerp->cpmt_tgcr |= TGCR_STP2; /* Stop Timer 2 */ |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 140 | |
| 141 | /* re-enable external interrupts if they were on */ |
| 142 | set_msr (msr_val); |
| 143 | |
| 144 | /* Disable timer and PIT |
| 145 | */ |
| 146 | timer2_val = timerp->cpmt_tcn2; /* save before reset timer */ |
| 147 | |
| 148 | timerp->cpmt_tgcr &= ~(TGCR_RST2 | TGCR_FRZ2 | TGCR_STP2); |
| 149 | immr->im_sit.sit_piscr &= ~PISCR_PTE; |
| 150 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 151 | #if defined(CONFIG_SYS_8XX_XIN) |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 152 | /* not using OSCM, using XIN, so scale appropriately */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 153 | return (((timer2_val + 2) / 4) * (CONFIG_SYS_8XX_XIN/512))/8192 * 100000L; |
wdenk | 2bb1105 | 2003-07-17 23:16:40 +0000 | [diff] [blame] | 154 | #else |
wdenk | 88d73b5 | 2004-02-11 21:35:18 +0000 | [diff] [blame] | 155 | return ((timer2_val + 2) / 4) * 100000L; /* convert to Hz */ |
wdenk | 2bb1105 | 2003-07-17 23:16:40 +0000 | [diff] [blame] | 156 | #endif |
| 157 | } |
| 158 | |
wdenk | fde3704 | 2004-01-31 20:06:54 +0000 | [diff] [blame] | 159 | #endif |
| 160 | |
Bryan O'Donoghue | 86c8d74 | 2008-02-17 22:57:47 +0000 | [diff] [blame] | 161 | void get_brgclk(uint sccr) |
| 162 | { |
| 163 | uint divider = 0; |
| 164 | |
| 165 | switch((sccr&SCCR_DFBRG11)>>11){ |
| 166 | case 0: |
| 167 | divider = 1; |
| 168 | break; |
| 169 | case 1: |
| 170 | divider = 4; |
| 171 | break; |
| 172 | case 2: |
| 173 | divider = 16; |
| 174 | break; |
| 175 | case 3: |
| 176 | divider = 64; |
| 177 | break; |
| 178 | } |
Simon Glass | 34a194f | 2012-12-13 20:48:44 +0000 | [diff] [blame] | 179 | gd->arch.brg_clk = gd->cpu_clk/divider; |
Bryan O'Donoghue | 86c8d74 | 2008-02-17 22:57:47 +0000 | [diff] [blame] | 180 | } |
| 181 | |
wdenk | 20bddb3 | 2004-09-28 17:59:53 +0000 | [diff] [blame] | 182 | #if !defined(CONFIG_8xx_CPUCLK_DEFAULT) |
wdenk | fde3704 | 2004-01-31 20:06:54 +0000 | [diff] [blame] | 183 | |
wdenk | 2bb1105 | 2003-07-17 23:16:40 +0000 | [diff] [blame] | 184 | /* |
| 185 | * get_clocks() fills in gd->cpu_clock depending on CONFIG_8xx_GCLK_FREQ |
| 186 | * or (if it is not defined) measure_gclk() (which uses the ref clock) |
| 187 | * from above. |
| 188 | */ |
| 189 | int get_clocks (void) |
| 190 | { |
wdenk | a7556b2 | 2004-06-06 21:35:06 +0000 | [diff] [blame] | 191 | uint immr = get_immr (0); /* Return full IMMR contents */ |
| 192 | volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000); |
| 193 | uint sccr = immap->im_clkrst.car_sccr; |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 194 | /* |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 195 | * If for some reason measuring the gclk frequency won't |
| 196 | * work, we return the hardwired value. |
| 197 | * (For example, the cogent CMA286-60 CPU module has no |
| 198 | * separate oscillator for PITRTCLK) |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 199 | */ |
wdenk | a7556b2 | 2004-06-06 21:35:06 +0000 | [diff] [blame] | 200 | #if defined(CONFIG_8xx_GCLK_FREQ) |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 201 | gd->cpu_clk = CONFIG_8xx_GCLK_FREQ; |
wdenk | a7556b2 | 2004-06-06 21:35:06 +0000 | [diff] [blame] | 202 | #elif defined(CONFIG_8xx_OSCLK) |
| 203 | #define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT) |
| 204 | uint pll = immap->im_clkrst.car_plprcr; |
| 205 | uint clk; |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 206 | |
wdenk | a7556b2 | 2004-06-06 21:35:06 +0000 | [diff] [blame] | 207 | if ((immr & 0x0FFF) >= MPC8xx_NEW_CLK) { /* MPC866/87x/88x series */ |
| 208 | clk = ((CONFIG_8xx_OSCLK / (PLPRCR_val(PDF)+1)) * |
| 209 | (PLPRCR_val(MFI) + PLPRCR_val(MFN) / (PLPRCR_val(MFD)+1))) / |
| 210 | (1<<PLPRCR_val(S)); |
| 211 | } else { |
| 212 | clk = CONFIG_8xx_OSCLK * (PLPRCR_val(MF)+1); |
| 213 | } |
| 214 | if (pll & PLPRCR_CSRC) { /* Low frequency division factor is used */ |
| 215 | gd->cpu_clk = clk / (2 << ((sccr >> 8) & 7)); |
| 216 | } else { /* High frequency division factor is used */ |
| 217 | gd->cpu_clk = clk / (1 << ((sccr >> 5) & 7)); |
| 218 | } |
| 219 | #else |
| 220 | gd->cpu_clk = measure_gclk(); |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 221 | #endif /* CONFIG_8xx_GCLK_FREQ */ |
| 222 | |
wdenk | a7556b2 | 2004-06-06 21:35:06 +0000 | [diff] [blame] | 223 | if ((sccr & SCCR_EBDF11) == 0) { |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 224 | /* No Bus Divider active */ |
| 225 | gd->bus_clk = gd->cpu_clk; |
| 226 | } else { |
| 227 | /* The MPC8xx has only one BDF: half clock speed */ |
| 228 | gd->bus_clk = gd->cpu_clk / 2; |
| 229 | } |
| 230 | |
Bryan O'Donoghue | 86c8d74 | 2008-02-17 22:57:47 +0000 | [diff] [blame] | 231 | get_brgclk(sccr); |
| 232 | |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 233 | return (0); |
| 234 | } |
| 235 | |
wdenk | 20bddb3 | 2004-09-28 17:59:53 +0000 | [diff] [blame] | 236 | #else /* CONFIG_8xx_CPUCLK_DEFAULT defined, use dynamic clock setting */ |
wdenk | b50cde5 | 2004-01-24 20:25:54 +0000 | [diff] [blame] | 237 | |
| 238 | static long init_pll_866 (long clk); |
| 239 | |
| 240 | /* This function sets up PLL (init_pll_866() is called) and |
| 241 | * fills gd->cpu_clk and gd->bus_clk according to the environment |
wdenk | 20bddb3 | 2004-09-28 17:59:53 +0000 | [diff] [blame] | 242 | * variable 'cpuclk' or to CONFIG_8xx_CPUCLK_DEFAULT (if 'cpuclk' |
wdenk | b50cde5 | 2004-01-24 20:25:54 +0000 | [diff] [blame] | 243 | * contains invalid value). |
wdenk | 20bddb3 | 2004-09-28 17:59:53 +0000 | [diff] [blame] | 244 | * This functions requires an MPC866 or newer series CPU. |
wdenk | b50cde5 | 2004-01-24 20:25:54 +0000 | [diff] [blame] | 245 | */ |
Simon Glass | ffe0fb4 | 2017-03-28 10:27:20 -0600 | [diff] [blame^] | 246 | int get_clocks(void) |
wdenk | b50cde5 | 2004-01-24 20:25:54 +0000 | [diff] [blame] | 247 | { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 248 | volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; |
wdenk | 88d73b5 | 2004-02-11 21:35:18 +0000 | [diff] [blame] | 249 | char tmp[64]; |
| 250 | long cpuclk = 0; |
| 251 | long sccr_reg; |
wdenk | b50cde5 | 2004-01-24 20:25:54 +0000 | [diff] [blame] | 252 | |
Wolfgang Denk | 76af278 | 2010-07-24 21:55:43 +0200 | [diff] [blame] | 253 | if (getenv_f("cpuclk", tmp, sizeof (tmp)) > 0) |
wdenk | b50cde5 | 2004-01-24 20:25:54 +0000 | [diff] [blame] | 254 | cpuclk = simple_strtoul (tmp, NULL, 10) * 1000000; |
| 255 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 256 | if ((CONFIG_SYS_8xx_CPUCLK_MIN > cpuclk) || (CONFIG_SYS_8xx_CPUCLK_MAX < cpuclk)) |
wdenk | 20bddb3 | 2004-09-28 17:59:53 +0000 | [diff] [blame] | 257 | cpuclk = CONFIG_8xx_CPUCLK_DEFAULT; |
wdenk | b50cde5 | 2004-01-24 20:25:54 +0000 | [diff] [blame] | 258 | |
| 259 | gd->cpu_clk = init_pll_866 (cpuclk); |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 260 | #if defined(CONFIG_SYS_MEASURE_CPUCLK) |
wdenk | fde3704 | 2004-01-31 20:06:54 +0000 | [diff] [blame] | 261 | gd->cpu_clk = measure_gclk (); |
| 262 | #endif |
wdenk | b50cde5 | 2004-01-24 20:25:54 +0000 | [diff] [blame] | 263 | |
Bryan O'Donoghue | 86c8d74 | 2008-02-17 22:57:47 +0000 | [diff] [blame] | 264 | get_brgclk(immr->im_clkrst.car_sccr); |
| 265 | |
wdenk | 88d73b5 | 2004-02-11 21:35:18 +0000 | [diff] [blame] | 266 | /* if cpu clock <= 66 MHz then set bus division factor to 1, |
| 267 | * otherwise set it to 2 |
| 268 | */ |
| 269 | sccr_reg = immr->im_clkrst.car_sccr; |
| 270 | sccr_reg &= ~SCCR_EBDF11; |
Jens Gehrlein | 6b206d6 | 2007-09-26 17:55:54 +0200 | [diff] [blame] | 271 | |
wdenk | 88d73b5 | 2004-02-11 21:35:18 +0000 | [diff] [blame] | 272 | if (gd->cpu_clk <= 66000000) { |
| 273 | sccr_reg |= SCCR_EBDF00; /* bus division factor = 1 */ |
wdenk | b50cde5 | 2004-01-24 20:25:54 +0000 | [diff] [blame] | 274 | gd->bus_clk = gd->cpu_clk; |
wdenk | 88d73b5 | 2004-02-11 21:35:18 +0000 | [diff] [blame] | 275 | } else { |
| 276 | sccr_reg |= SCCR_EBDF01; /* bus division factor = 2 */ |
wdenk | b50cde5 | 2004-01-24 20:25:54 +0000 | [diff] [blame] | 277 | gd->bus_clk = gd->cpu_clk / 2; |
wdenk | 88d73b5 | 2004-02-11 21:35:18 +0000 | [diff] [blame] | 278 | } |
| 279 | immr->im_clkrst.car_sccr = sccr_reg; |
wdenk | b50cde5 | 2004-01-24 20:25:54 +0000 | [diff] [blame] | 280 | |
| 281 | return (0); |
| 282 | } |
| 283 | |
| 284 | /* Adjust sdram refresh rate to actual CPU clock. |
| 285 | */ |
| 286 | int sdram_adjust_866 (void) |
| 287 | { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 288 | volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; |
wdenk | 88d73b5 | 2004-02-11 21:35:18 +0000 | [diff] [blame] | 289 | long mamr; |
wdenk | b50cde5 | 2004-01-24 20:25:54 +0000 | [diff] [blame] | 290 | |
| 291 | mamr = immr->im_memctl.memc_mamr; |
| 292 | mamr &= ~MAMR_PTA_MSK; |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 293 | mamr |= ((gd->cpu_clk / CONFIG_SYS_PTA_PER_CLK) << MAMR_PTA_SHIFT); |
wdenk | b50cde5 | 2004-01-24 20:25:54 +0000 | [diff] [blame] | 294 | immr->im_memctl.memc_mamr = mamr; |
| 295 | |
| 296 | return (0); |
| 297 | } |
| 298 | |
wdenk | 20bddb3 | 2004-09-28 17:59:53 +0000 | [diff] [blame] | 299 | /* Configure PLL for MPC866/859/885 CPU series |
wdenk | b50cde5 | 2004-01-24 20:25:54 +0000 | [diff] [blame] | 300 | * PLL multiplication factor is set to the value nearest to the desired clk, |
| 301 | * assuming a oscclk of 10 MHz. |
| 302 | */ |
| 303 | static long init_pll_866 (long clk) |
| 304 | { |
| 305 | extern void plprcr_write_866 (long); |
| 306 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 307 | volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; |
wdenk | 88d73b5 | 2004-02-11 21:35:18 +0000 | [diff] [blame] | 308 | long n, plprcr; |
| 309 | char mfi, mfn, mfd, s, pdf; |
| 310 | long step_mfi, step_mfn; |
wdenk | b50cde5 | 2004-01-24 20:25:54 +0000 | [diff] [blame] | 311 | |
wdenk | fde3704 | 2004-01-31 20:06:54 +0000 | [diff] [blame] | 312 | if (clk < 20000000) { |
| 313 | clk *= 2; |
| 314 | pdf = 1; |
| 315 | } else { |
| 316 | pdf = 0; |
| 317 | } |
| 318 | |
| 319 | if (clk < 40000000) { |
| 320 | s = 2; |
wdenk | 20bddb3 | 2004-09-28 17:59:53 +0000 | [diff] [blame] | 321 | step_mfi = CONFIG_8xx_OSCLK / 4; |
wdenk | fde3704 | 2004-01-31 20:06:54 +0000 | [diff] [blame] | 322 | mfd = 7; |
wdenk | 20bddb3 | 2004-09-28 17:59:53 +0000 | [diff] [blame] | 323 | step_mfn = CONFIG_8xx_OSCLK / 30; |
wdenk | fde3704 | 2004-01-31 20:06:54 +0000 | [diff] [blame] | 324 | } else if (clk < 80000000) { |
wdenk | b50cde5 | 2004-01-24 20:25:54 +0000 | [diff] [blame] | 325 | s = 1; |
wdenk | 20bddb3 | 2004-09-28 17:59:53 +0000 | [diff] [blame] | 326 | step_mfi = CONFIG_8xx_OSCLK / 2; |
wdenk | b50cde5 | 2004-01-24 20:25:54 +0000 | [diff] [blame] | 327 | mfd = 14; |
wdenk | 20bddb3 | 2004-09-28 17:59:53 +0000 | [diff] [blame] | 328 | step_mfn = CONFIG_8xx_OSCLK / 30; |
wdenk | b50cde5 | 2004-01-24 20:25:54 +0000 | [diff] [blame] | 329 | } else { |
| 330 | s = 0; |
wdenk | 20bddb3 | 2004-09-28 17:59:53 +0000 | [diff] [blame] | 331 | step_mfi = CONFIG_8xx_OSCLK; |
wdenk | b50cde5 | 2004-01-24 20:25:54 +0000 | [diff] [blame] | 332 | mfd = 29; |
wdenk | 20bddb3 | 2004-09-28 17:59:53 +0000 | [diff] [blame] | 333 | step_mfn = CONFIG_8xx_OSCLK / 30; |
wdenk | b50cde5 | 2004-01-24 20:25:54 +0000 | [diff] [blame] | 334 | } |
| 335 | |
| 336 | /* Calculate integer part of multiplication factor |
| 337 | */ |
| 338 | n = clk / step_mfi; |
| 339 | mfi = (char)n; |
| 340 | |
| 341 | /* Calculate numerator of fractional part of multiplication factor |
| 342 | */ |
| 343 | n = clk - (n * step_mfi); |
| 344 | mfn = (char)(n / step_mfn); |
| 345 | |
| 346 | /* Calculate effective clk |
| 347 | */ |
wdenk | fde3704 | 2004-01-31 20:06:54 +0000 | [diff] [blame] | 348 | n = ((mfi * step_mfi) + (mfn * step_mfn)) / (pdf + 1); |
wdenk | b50cde5 | 2004-01-24 20:25:54 +0000 | [diff] [blame] | 349 | |
| 350 | immr->im_clkrstk.cark_plprcrk = KAPWR_KEY; |
| 351 | |
| 352 | plprcr = (immr->im_clkrst.car_plprcr & ~(PLPRCR_MFN_MSK |
| 353 | | PLPRCR_MFD_MSK | PLPRCR_S_MSK |
wdenk | fde3704 | 2004-01-31 20:06:54 +0000 | [diff] [blame] | 354 | | PLPRCR_MFI_MSK | PLPRCR_DBRMO |
| 355 | | PLPRCR_PDF_MSK)) |
wdenk | b50cde5 | 2004-01-24 20:25:54 +0000 | [diff] [blame] | 356 | | (mfn << PLPRCR_MFN_SHIFT) |
| 357 | | (mfd << PLPRCR_MFD_SHIFT) |
| 358 | | (s << PLPRCR_S_SHIFT) |
| 359 | | (mfi << PLPRCR_MFI_SHIFT) |
| 360 | | (pdf << PLPRCR_PDF_SHIFT); |
| 361 | |
| 362 | if( (mfn > 0) && ((mfd / mfn) > 10) ) |
| 363 | plprcr |= PLPRCR_DBRMO; |
| 364 | |
| 365 | plprcr_write_866 (plprcr); /* set value using SIU4/9 workaround */ |
| 366 | immr->im_clkrstk.cark_plprcrk = 0x00000000; |
| 367 | |
| 368 | return (n); |
| 369 | } |
| 370 | |
wdenk | 20bddb3 | 2004-09-28 17:59:53 +0000 | [diff] [blame] | 371 | #endif /* CONFIG_8xx_CPUCLK_DEFAULT */ |
wdenk | b50cde5 | 2004-01-24 20:25:54 +0000 | [diff] [blame] | 372 | |
Markus Klotzbuecher | 13af9f0 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 373 | #if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \ |
| 374 | && !defined(CONFIG_TQM885D) |
wdenk | c78bf13 | 2004-04-24 23:23:30 +0000 | [diff] [blame] | 375 | /* |
| 376 | * Adjust sdram refresh rate to actual CPU clock |
| 377 | * and set timebase source according to actual CPU clock |
| 378 | */ |
| 379 | int adjust_sdram_tbs_8xx (void) |
| 380 | { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 381 | volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; |
wdenk | c78bf13 | 2004-04-24 23:23:30 +0000 | [diff] [blame] | 382 | long mamr; |
| 383 | long sccr; |
| 384 | |
| 385 | mamr = immr->im_memctl.memc_mamr; |
| 386 | mamr &= ~MAMR_PTA_MSK; |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 387 | mamr |= ((gd->cpu_clk / CONFIG_SYS_PTA_PER_CLK) << MAMR_PTA_SHIFT); |
wdenk | c78bf13 | 2004-04-24 23:23:30 +0000 | [diff] [blame] | 388 | immr->im_memctl.memc_mamr = mamr; |
| 389 | |
| 390 | if (gd->cpu_clk < 67000000) { |
| 391 | sccr = immr->im_clkrst.car_sccr; |
| 392 | sccr |= SCCR_TBS; |
| 393 | immr->im_clkrst.car_sccr = sccr; |
| 394 | } |
| 395 | |
| 396 | return (0); |
| 397 | } |
Markus Klotzbuecher | 13af9f0 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 398 | #endif /* CONFIG_TQM8xxL/M, !TQM866M, !TQM885D */ |
wdenk | c78bf13 | 2004-04-24 23:23:30 +0000 | [diff] [blame] | 399 | |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 400 | /* ------------------------------------------------------------------------- */ |