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wdenk9b7f3842003-10-09 20:09:04 +00001/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * This file contains the configuration parameters for the dbau1x00 board.
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
32#define CONFIG_DBAU1X00 1
Shinya Kuribayashied49a6a2008-06-07 20:51:56 +090033#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
wdenk9b7f3842003-10-09 20:09:04 +000034
wdenk4ea537d2003-12-07 18:32:37 +000035#ifdef CONFIG_DBAU1000
wdenk9b7f3842003-10-09 20:09:04 +000036/* Also known as Merlot */
Shinya Kuribayashied49a6a2008-06-07 20:51:56 +090037#define CONFIG_SOC_AU1000 1
wdenk4ea537d2003-12-07 18:32:37 +000038#else
39#ifdef CONFIG_DBAU1100
Shinya Kuribayashied49a6a2008-06-07 20:51:56 +090040#define CONFIG_SOC_AU1100 1
wdenk4ea537d2003-12-07 18:32:37 +000041#else
42#ifdef CONFIG_DBAU1500
Shinya Kuribayashied49a6a2008-06-07 20:51:56 +090043#define CONFIG_SOC_AU1500 1
wdenk1ebf41e2004-01-02 14:00:00 +000044#else
wdenk96c7a8c2005-01-09 22:28:56 +000045#ifdef CONFIG_DBAU1550
46/* Cabernet */
Shinya Kuribayashied49a6a2008-06-07 20:51:56 +090047#define CONFIG_SOC_AU1550 1
wdenk96c7a8c2005-01-09 22:28:56 +000048#else
wdenk4ea537d2003-12-07 18:32:37 +000049#error "No valid board set"
50#endif
51#endif
52#endif
wdenk96c7a8c2005-01-09 22:28:56 +000053#endif
wdenk9b7f3842003-10-09 20:09:04 +000054
wdenk1ebf41e2004-01-02 14:00:00 +000055#define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */
wdenk9b7f3842003-10-09 20:09:04 +000056
57#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
58
59#define CONFIG_BAUDRATE 115200
60
61/* valid baudrates */
wdenk9b7f3842003-10-09 20:09:04 +000062
63#define CONFIG_TIMESTAMP /* Print image info with timestamp */
64#undef CONFIG_BOOTARGS
65
66#define CONFIG_EXTRA_ENV_SETTINGS \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010067 "addmisc=setenv bootargs ${bootargs} " \
68 "console=ttyS0,${baudrate} " \
wdenk9b7f3842003-10-09 20:09:04 +000069 "panic=1\0" \
70 "bootfile=/tftpboot/vmlinux.srec\0" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010071 "load=tftp 80500000 ${u-boot}\0" \
wdenk9b7f3842003-10-09 20:09:04 +000072 ""
wdenk96c7a8c2005-01-09 22:28:56 +000073
74#ifdef CONFIG_DBAU1550
75/* Boot from flash by default, revert to bootp */
76#define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm"
wdenk96c7a8c2005-01-09 22:28:56 +000077#else /* CONFIG_DBAU1550 */
Heiko Schocher65d4f8b2006-04-11 14:53:29 +020078#define CONFIG_BOOTCOMMAND "bootp;bootm"
wdenk96c7a8c2005-01-09 22:28:56 +000079#endif /* CONFIG_DBAU1550 */
80
Jon Loeligerb15a23b2007-07-04 22:32:03 -050081
82/*
Jon Loeligere54e77a2007-07-10 09:29:01 -050083 * BOOTP options
84 */
85#define CONFIG_BOOTP_BOOTFILESIZE
86#define CONFIG_BOOTP_BOOTPATH
87#define CONFIG_BOOTP_GATEWAY
88#define CONFIG_BOOTP_HOSTNAME
89
90
91/*
Jon Loeligerb15a23b2007-07-04 22:32:03 -050092 * Command line configuration.
93 */
94#include <config_cmd_default.h>
95
96#undef CONFIG_CMD_BDI
97#undef CONFIG_CMD_BEDBUG
98#undef CONFIG_CMD_ELF
Mike Frysinger78dcaf42009-01-28 19:08:14 -050099#undef CONFIG_CMD_SAVEENV
Jon Loeligerb15a23b2007-07-04 22:32:03 -0500100#undef CONFIG_CMD_FAT
101#undef CONFIG_CMD_FPGA
102#undef CONFIG_CMD_MII
103#undef CONFIG_CMD_RUN
104
105
106#ifdef CONFIG_DBAU1550
107
108#define CONFIG_CMD_FLASH
109#define CONFIG_CMD_LOADB
110#define CONFIG_CMD_NET
111
112#undef CONFIG_CMD_I2C
113#undef CONFIG_CMD_IDE
114#undef CONFIG_CMD_NFS
115#undef CONFIG_CMD_PCMCIA
116
117#else
118
119#define CONFIG_CMD_IDE
120#define CONFIG_CMD_DHCP
121
122#undef CONFIG_CMD_FLASH
123#undef CONFIG_CMD_LOADB
124#undef CONFIG_CMD_LOADS
125
126#endif
127
wdenk9b7f3842003-10-09 20:09:04 +0000128
129/*
130 * Miscellaneous configurable options
131 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200132#define CONFIG_SYS_LONGHELP /* undef to save memory */
wdenk96c7a8c2005-01-09 22:28:56 +0000133
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200134#define CONFIG_SYS_PROMPT "DbAu1xx0 # " /* Monitor Command Prompt */
wdenk96c7a8c2005-01-09 22:28:56 +0000135
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200136#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
137#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
138#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
wdenk9b7f3842003-10-09 20:09:04 +0000139
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200140#define CONFIG_SYS_MALLOC_LEN 128*1024
wdenk9b7f3842003-10-09 20:09:04 +0000141
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200142#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
wdenk9b7f3842003-10-09 20:09:04 +0000143
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200144#define CONFIG_SYS_MHZ 396
wdenk96c7a8c2005-01-09 22:28:56 +0000145
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200146#if (CONFIG_SYS_MHZ % 12) != 0
wdenk96c7a8c2005-01-09 22:28:56 +0000147#error "Invalid CPU frequency - must be multiple of 12!"
148#endif
149
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200150#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
Shinya Kuribayashi5d374e02008-06-05 22:29:00 +0900151
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200152#define CONFIG_SYS_HZ 1000
wdenk9b7f3842003-10-09 20:09:04 +0000153
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200154#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
wdenk9b7f3842003-10-09 20:09:04 +0000155
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200156#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */
wdenk9b7f3842003-10-09 20:09:04 +0000157
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200158#define CONFIG_SYS_MEMTEST_START 0x80100000
159#define CONFIG_SYS_MEMTEST_END 0x80800000
wdenk9b7f3842003-10-09 20:09:04 +0000160
161/*-----------------------------------------------------------------------
162 * FLASH and environment organization
163 */
wdenk96c7a8c2005-01-09 22:28:56 +0000164#ifdef CONFIG_DBAU1550
165
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200166#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
167#define CONFIG_SYS_MAX_FLASH_SECT (512) /* max number of sectors on one chip */
wdenk96c7a8c2005-01-09 22:28:56 +0000168
169#define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */
170#define PHYS_FLASH_2 0xbc000000 /* Flash Bank #2 */
171
wdenk96c7a8c2005-01-09 22:28:56 +0000172#else /* CONFIG_DBAU1550 */
173
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200174#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
175#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
wdenk9b7f3842003-10-09 20:09:04 +0000176
177#define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */
178#define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */
179
wdenk96c7a8c2005-01-09 22:28:56 +0000180#endif /* CONFIG_DBAU1550 */
181
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200182#define CONFIG_SYS_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2}
Heiko Schocher65d4f8b2006-04-11 14:53:29 +0200183
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200184#define CONFIG_SYS_FLASH_CFI 1
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200185#define CONFIG_FLASH_CFI_DRIVER 1
wdenk96c7a8c2005-01-09 22:28:56 +0000186
wdenk9b7f3842003-10-09 20:09:04 +0000187/* The following #defines are needed to get flash environment right */
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200188#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200189#define CONFIG_SYS_MONITOR_LEN (192 << 10)
wdenk9b7f3842003-10-09 20:09:04 +0000190
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200191#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
wdenk9b7f3842003-10-09 20:09:04 +0000192
193/* We boot from this flash, selected with dip switch */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200194#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2
wdenk9b7f3842003-10-09 20:09:04 +0000195
196/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200197#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
198#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
wdenk9b7f3842003-10-09 20:09:04 +0000199
Jean-Christophe PLAGNIOL-VILLARD68a87562008-09-10 22:48:00 +0200200#define CONFIG_ENV_IS_NOWHERE 1
wdenk9b7f3842003-10-09 20:09:04 +0000201
202/* Address and size of Primary Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200203#define CONFIG_ENV_ADDR 0xB0030000
204#define CONFIG_ENV_SIZE 0x10000
wdenk9b7f3842003-10-09 20:09:04 +0000205
206#define CONFIG_FLASH_16BIT
207
208#define CONFIG_NR_DRAM_BANKS 2
209
wdenk9b7f3842003-10-09 20:09:04 +0000210
wdenk96c7a8c2005-01-09 22:28:56 +0000211#ifdef CONFIG_DBAU1550
212#define MEM_SIZE 192
213#else
214#define MEM_SIZE 64
215#endif
216
wdenk9b7f3842003-10-09 20:09:04 +0000217#define CONFIG_MEMSIZE_IN_BYTES
218
wdenk96c7a8c2005-01-09 22:28:56 +0000219#ifndef CONFIG_DBAU1550
wdenk9b7f3842003-10-09 20:09:04 +0000220/*---ATA PCMCIA ------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200221#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
222#define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000
wdenk9b7f3842003-10-09 20:09:04 +0000223#define CONFIG_PCMCIA_SLOT_A
224
225#define CONFIG_ATAPI 1
226#define CONFIG_MAC_PARTITION 1
227
228/* We run CF in "true ide" mode or a harddrive via pcmcia */
229#define CONFIG_IDE_PCMCIA 1
230
231/* We only support one slot for now */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200232#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
233#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenk9b7f3842003-10-09 20:09:04 +0000234
235#undef CONFIG_IDE_LED /* LED for ide not supported */
236#undef CONFIG_IDE_RESET /* reset for ide not supported */
237
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200238#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenk9b7f3842003-10-09 20:09:04 +0000239
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200240#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenk9b7f3842003-10-09 20:09:04 +0000241
wdenk1ebf41e2004-01-02 14:00:00 +0000242/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200243#define CONFIG_SYS_ATA_DATA_OFFSET 8
wdenk9b7f3842003-10-09 20:09:04 +0000244
245/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200246#define CONFIG_SYS_ATA_REG_OFFSET 0
wdenk9b7f3842003-10-09 20:09:04 +0000247
248/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200249#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenk96c7a8c2005-01-09 22:28:56 +0000250#endif /* CONFIG_DBAU1550 */
wdenk9b7f3842003-10-09 20:09:04 +0000251
252/*-----------------------------------------------------------------------
253 * Cache Configuration
254 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200255#define CONFIG_SYS_DCACHE_SIZE 16384
256#define CONFIG_SYS_ICACHE_SIZE 16384
257#define CONFIG_SYS_CACHELINE_SIZE 32
wdenk9b7f3842003-10-09 20:09:04 +0000258
wdenk9b7f3842003-10-09 20:09:04 +0000259#endif /* __CONFIG_H */