blob: 28f067a2515f4b322103472ca0c2c196dd374ed9 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Michal Simek04b7e622015-01-15 10:01:51 +01002/*
3 * (C) Copyright 2014 - 2015 Xilinx, Inc.
4 * Michal Simek <michal.simek@xilinx.com>
Michal Simek04b7e622015-01-15 10:01:51 +01005 */
6
7#include <common.h>
Simon Glassed38aef2020-05-10 11:40:03 -06008#include <command.h>
Simon Glass370382c2019-11-14 12:57:35 -07009#include <cpu_func.h>
Michal Simek09a7d7d2020-01-07 09:02:52 +010010#include <debug_uart.h>
Simon Glass5e6201b2019-08-01 09:46:51 -060011#include <env.h>
Michal Simek8d4a8d42020-07-30 13:37:49 +020012#include <env_internal.h>
Simon Glassa7b51302019-11-14 12:57:46 -070013#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060014#include <log.h>
Simon Glass274e0b02020-05-10 11:39:56 -060015#include <net.h>
Michal Simekd54b1af2015-09-30 17:26:55 +020016#include <sata.h>
Michal Simekb216cc12015-07-23 13:27:40 +020017#include <ahci.h>
18#include <scsi.h>
Michal Simekecfb6dc2016-04-22 14:28:54 +020019#include <malloc.h>
Michal Simekbf0f9ca2018-04-19 15:43:38 +020020#include <wdt.h>
Michal Simekc23d3f82015-11-05 08:34:35 +010021#include <asm/arch/clk.h>
Michal Simek04b7e622015-01-15 10:01:51 +010022#include <asm/arch/hardware.h>
23#include <asm/arch/sys_proto.h>
Michal Simekf2f08642018-01-10 09:36:09 +010024#include <asm/arch/psu_init_gpl.h>
Simon Glass274e0b02020-05-10 11:39:56 -060025#include <asm/cache.h>
Michal Simek04b7e622015-01-15 10:01:51 +010026#include <asm/io.h>
Simon Glass6b9f0102020-05-10 11:40:06 -060027#include <asm/ptrace.h>
Michal Simekf183a982018-04-25 11:20:43 +020028#include <dm/device.h>
Michal Simekbf0f9ca2018-04-19 15:43:38 +020029#include <dm/uclass.h>
Siva Durga Prasad Paladuguba1f68e2015-08-04 13:03:26 +053030#include <usb.h>
31#include <dwc3-uboot.h>
Michal Simek8111aff2016-02-01 15:05:58 +010032#include <zynqmppl.h>
Ibai Erkiagac8a3efa2019-09-27 11:37:01 +010033#include <zynqmp_firmware.h>
Michal Simek76d0a772016-09-01 11:16:40 +020034#include <g_dnl.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060035#include <linux/bitops.h>
Simon Glassdbd79542020-05-10 11:40:11 -060036#include <linux/delay.h>
37#include <linux/sizes.h>
Michal Simek705d44a2020-03-31 12:39:37 +020038#include "../common/board.h"
Michal Simek04b7e622015-01-15 10:01:51 +010039
Luca Ceresoli23e65002019-05-21 18:06:43 +020040#include "pm_cfg_obj.h"
41
Ibai Erkiaga4f736182020-08-04 23:17:31 +010042#define ZYNQMP_VERSION_SIZE 7
43#define EFUSE_VCU_DIS_MASK 0x100
44#define EFUSE_VCU_DIS_SHIFT 8
45#define EFUSE_GPU_DIS_MASK 0x20
46#define EFUSE_GPU_DIS_SHIFT 5
47#define IDCODE2_PL_INIT_MASK 0x200
48#define IDCODE2_PL_INIT_SHIFT 9
49
Michal Simek04b7e622015-01-15 10:01:51 +010050DECLARE_GLOBAL_DATA_PTR;
51
Michal Simek1aab1142020-09-09 14:41:56 +020052#if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
Michal Simek8111aff2016-02-01 15:05:58 +010053static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
54
Ibai Erkiaga4f736182020-08-04 23:17:31 +010055enum {
56 ZYNQMP_VARIANT_EG = BIT(0U),
57 ZYNQMP_VARIANT_EV = BIT(1U),
58 ZYNQMP_VARIANT_CG = BIT(2U),
59 ZYNQMP_VARIANT_DR = BIT(3U),
60};
61
Michal Simek8111aff2016-02-01 15:05:58 +010062static const struct {
Michal Simek6908b862017-11-06 12:55:59 +010063 u32 id;
Ibai Erkiaga4f736182020-08-04 23:17:31 +010064 u8 device;
65 u8 variants;
Michal Simek8111aff2016-02-01 15:05:58 +010066} zynqmp_devices[] = {
67 {
Ibai Erkiaga4f736182020-08-04 23:17:31 +010068 .id = 0x04711093,
69 .device = 2,
70 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
Michal Simek50d8cef2017-08-22 14:58:53 +020071 },
72 {
Ibai Erkiaga4f736182020-08-04 23:17:31 +010073 .id = 0x04710093,
74 .device = 3,
75 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
Michal Simek8111aff2016-02-01 15:05:58 +010076 },
77 {
Ibai Erkiaga4f736182020-08-04 23:17:31 +010078 .id = 0x04721093,
79 .device = 4,
80 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
81 ZYNQMP_VARIANT_EV,
Michal Simek50d8cef2017-08-22 14:58:53 +020082 },
83 {
Ibai Erkiaga4f736182020-08-04 23:17:31 +010084 .id = 0x04720093,
85 .device = 5,
86 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
87 ZYNQMP_VARIANT_EV,
Michal Simek50d8cef2017-08-22 14:58:53 +020088 },
89 {
Ibai Erkiaga4f736182020-08-04 23:17:31 +010090 .id = 0x04739093,
91 .device = 6,
92 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
Michal Simek8111aff2016-02-01 15:05:58 +010093 },
94 {
Ibai Erkiaga4f736182020-08-04 23:17:31 +010095 .id = 0x04730093,
96 .device = 7,
97 .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
98 ZYNQMP_VARIANT_EV,
Michal Simek50d8cef2017-08-22 14:58:53 +020099 },
100 {
Ibai Erkiaga4f736182020-08-04 23:17:31 +0100101 .id = 0x04738093,
102 .device = 9,
103 .variants = ZYNQMP_VARIANT_EG,
Michal Simek50d8cef2017-08-22 14:58:53 +0200104 },
105 {
Ibai Erkiaga4f736182020-08-04 23:17:31 +0100106 .id = 0x04740093,
107 .device = 11,
108 .variants = ZYNQMP_VARIANT_EG,
Michal Simek8111aff2016-02-01 15:05:58 +0100109 },
110 {
Ibai Erkiaga4f736182020-08-04 23:17:31 +0100111 .id = 0x04750093,
112 .device = 15,
113 .variants = ZYNQMP_VARIANT_EG,
Michal Simek50d8cef2017-08-22 14:58:53 +0200114 },
115 {
Ibai Erkiaga4f736182020-08-04 23:17:31 +0100116 .id = 0x04759093,
117 .device = 17,
118 .variants = ZYNQMP_VARIANT_EG,
Michal Simek50d8cef2017-08-22 14:58:53 +0200119 },
120 {
Ibai Erkiaga4f736182020-08-04 23:17:31 +0100121 .id = 0x04758093,
122 .device = 19,
123 .variants = ZYNQMP_VARIANT_EG,
Michal Simek8111aff2016-02-01 15:05:58 +0100124 },
125 {
Ibai Erkiaga4f736182020-08-04 23:17:31 +0100126 .id = 0x047E1093,
127 .device = 21,
128 .variants = ZYNQMP_VARIANT_DR,
Michal Simek50d8cef2017-08-22 14:58:53 +0200129 },
130 {
Ibai Erkiaga4f736182020-08-04 23:17:31 +0100131 .id = 0x047E3093,
132 .device = 23,
133 .variants = ZYNQMP_VARIANT_DR,
Michal Simek8111aff2016-02-01 15:05:58 +0100134 },
135 {
Ibai Erkiaga4f736182020-08-04 23:17:31 +0100136 .id = 0x047E5093,
137 .device = 25,
138 .variants = ZYNQMP_VARIANT_DR,
Michal Simek50d8cef2017-08-22 14:58:53 +0200139 },
140 {
Ibai Erkiaga4f736182020-08-04 23:17:31 +0100141 .id = 0x047E4093,
142 .device = 27,
143 .variants = ZYNQMP_VARIANT_DR,
Michal Simek8111aff2016-02-01 15:05:58 +0100144 },
145 {
Ibai Erkiaga4f736182020-08-04 23:17:31 +0100146 .id = 0x047E0093,
147 .device = 28,
148 .variants = ZYNQMP_VARIANT_DR,
Michal Simek8111aff2016-02-01 15:05:58 +0100149 },
150 {
Ibai Erkiaga4f736182020-08-04 23:17:31 +0100151 .id = 0x047E2093,
152 .device = 29,
153 .variants = ZYNQMP_VARIANT_DR,
Michal Simek8111aff2016-02-01 15:05:58 +0100154 },
Michal Simekb510e532017-06-02 08:08:59 +0200155 {
Ibai Erkiaga4f736182020-08-04 23:17:31 +0100156 .id = 0x047E6093,
157 .device = 39,
158 .variants = ZYNQMP_VARIANT_DR,
Michal Simekb510e532017-06-02 08:08:59 +0200159 },
160 {
Michal Simek3fd2ed32020-09-11 09:22:15 +0200161 .id = 0x047FD093,
162 .device = 43,
163 .variants = ZYNQMP_VARIANT_DR,
Michal Simekb510e532017-06-02 08:08:59 +0200164 },
165 {
Michal Simek3fd2ed32020-09-11 09:22:15 +0200166 .id = 0x047F8093,
167 .device = 46,
168 .variants = ZYNQMP_VARIANT_DR,
Michal Simekb510e532017-06-02 08:08:59 +0200169 },
170 {
Michal Simek3fd2ed32020-09-11 09:22:15 +0200171 .id = 0x047FF093,
172 .device = 47,
173 .variants = ZYNQMP_VARIANT_DR,
Michal Simekb510e532017-06-02 08:08:59 +0200174 },
175 {
Ibai Erkiaga4f736182020-08-04 23:17:31 +0100176 .id = 0x047FB093,
177 .device = 48,
178 .variants = ZYNQMP_VARIANT_DR,
Michal Simekb510e532017-06-02 08:08:59 +0200179 },
180 {
Ibai Erkiaga4f736182020-08-04 23:17:31 +0100181 .id = 0x047FE093,
182 .device = 49,
183 .variants = ZYNQMP_VARIANT_DR,
Siva Durga Prasad Paladugu85f61a82019-07-23 11:56:17 +0530184 },
Michal Simek8111aff2016-02-01 15:05:58 +0100185};
Siva Durga Prasad Paladuguba2622d2018-03-02 16:20:10 +0530186
Michal Simek8111aff2016-02-01 15:05:58 +0100187static char *zynqmp_get_silicon_idcode_name(void)
188{
Ibai Erkiaga4f736182020-08-04 23:17:31 +0100189 u32 i;
190 u32 idcode, idcode2;
Michal Simek051b8bc2020-08-05 12:41:35 +0200191 char name[ZYNQMP_VERSION_SIZE];
Ibai Erkiagac318ecb2020-08-04 23:17:30 +0100192 u32 ret_payload[PAYLOAD_ARG_CNT];
193
194 xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0, ret_payload);
195
196 /*
197 * Firmware returns:
198 * payload[0][31:0] = status of the operation
199 * payload[1]] = IDCODE
200 * payload[2][19:0] = Version
201 * payload[2][28:20] = EXTENDED_IDCODE
202 * payload[2][29] = PL_INIT
203 */
204
Ibai Erkiaga4f736182020-08-04 23:17:31 +0100205 idcode = ret_payload[1];
206 idcode2 = ret_payload[2] >> ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
207 debug("%s, IDCODE: 0x%0X, IDCODE2: 0x%0X\r\n", __func__, idcode,
208 idcode2);
Michal Simek50d8cef2017-08-22 14:58:53 +0200209
Michal Simek8111aff2016-02-01 15:05:58 +0100210 for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
Ibai Erkiaga4f736182020-08-04 23:17:31 +0100211 if (zynqmp_devices[i].id == (idcode & 0x0FFFFFFF))
212 break;
Michal Simek8111aff2016-02-01 15:05:58 +0100213 }
Siva Durga Prasad Paladuguba2622d2018-03-02 16:20:10 +0530214
215 if (i >= ARRAY_SIZE(zynqmp_devices))
216 return "unknown";
217
Ibai Erkiaga4f736182020-08-04 23:17:31 +0100218 /* Add device prefix to the name */
Michal Simek051b8bc2020-08-05 12:41:35 +0200219 strncpy(name, "zu", ZYNQMP_VERSION_SIZE);
Ibai Erkiaga4f736182020-08-04 23:17:31 +0100220 strncat(&name[2], simple_itoa(zynqmp_devices[i].device), 2);
Siva Durga Prasad Paladuguba2622d2018-03-02 16:20:10 +0530221
Ibai Erkiaga4f736182020-08-04 23:17:31 +0100222 if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_EV) {
223 /* Devices with EV variant might be EG/CG/EV family */
224 if (idcode2 & IDCODE2_PL_INIT_MASK) {
225 u32 family = ((idcode2 & EFUSE_VCU_DIS_MASK) >>
226 EFUSE_VCU_DIS_SHIFT) << 1 |
227 ((idcode2 & EFUSE_GPU_DIS_MASK) >>
228 EFUSE_GPU_DIS_SHIFT);
Siva Durga Prasad Paladuguba2622d2018-03-02 16:20:10 +0530229
Ibai Erkiaga4f736182020-08-04 23:17:31 +0100230 /*
231 * Get family name based on extended idcode values as
232 * determined on UG1087, EXTENDED_IDCODE register
233 * description
234 */
235 switch (family) {
236 case 0x00:
237 strncat(name, "ev", 2);
238 break;
239 case 0x10:
240 strncat(name, "eg", 2);
241 break;
242 case 0x11:
243 strncat(name, "cg", 2);
244 break;
245 default:
246 /* Do not append family name*/
247 break;
248 }
249 } else {
250 /*
251 * When PL powered down the VCU Disable efuse cannot be
252 * read. So, ignore the bit and just findout if it is CG
253 * or EG/EV variant.
254 */
255 strncat(name, (idcode2 & EFUSE_GPU_DIS_MASK) ? "cg" :
256 "e", 2);
257 }
258 } else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_CG) {
259 /* Devices with CG variant might be EG or CG family */
260 strncat(name, (idcode2 & EFUSE_GPU_DIS_MASK) ? "cg" : "eg", 2);
261 } else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_EG) {
262 strncat(name, "eg", 2);
263 } else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_DR) {
264 strncat(name, "dr", 2);
265 } else {
266 debug("Variant not identified\n");
Siva Durga Prasad Paladuguba2622d2018-03-02 16:20:10 +0530267 }
268
Michal Simek051b8bc2020-08-05 12:41:35 +0200269 return strdup(name);
Michal Simek8111aff2016-02-01 15:05:58 +0100270}
271#endif
272
Michal Simek8b353302017-02-07 14:32:26 +0100273int board_early_init_f(void)
274{
Michal Simek1a1ab5a2018-01-15 12:52:59 +0100275#if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
Michal Simek09a7d7d2020-01-07 09:02:52 +0100276 int ret;
277
Michal Simekc8785f22018-01-10 11:48:48 +0100278 ret = psu_init();
Michal Simek09a7d7d2020-01-07 09:02:52 +0100279 if (ret)
280 return ret;
Michal Simek1f55e572020-03-20 08:59:02 +0100281
282 /* Delay is required for clocks to be propagated */
283 udelay(1000000);
Michal Simeke0f36102017-07-12 13:08:41 +0200284#endif
285
Michal Simek09a7d7d2020-01-07 09:02:52 +0100286#ifdef CONFIG_DEBUG_UART
287 /* Uart debug for sure */
288 debug_uart_init();
289 puts("Debug uart enabled\n"); /* or printch() */
290#endif
291
292 return 0;
Michal Simek8b353302017-02-07 14:32:26 +0100293}
294
Michal Simek46900462020-02-11 12:43:14 +0100295static int multi_boot(void)
296{
297 u32 multiboot;
298
299 multiboot = readl(&csu_base->multi_boot);
300
Michal Simekc55f2d52020-05-27 12:50:33 +0200301 printf("Multiboot:\t%d\n", multiboot);
Michal Simek46900462020-02-11 12:43:14 +0100302
303 return 0;
304}
305
Mike Looijmans9863e2f2019-10-18 07:34:13 +0200306#define PS_SYSMON_ANALOG_BUS_VAL 0x3210
307#define PS_SYSMON_ANALOG_BUS_REG 0xFFA50914
308
Michal Simek04b7e622015-01-15 10:01:51 +0100309int board_init(void)
310{
Michal Simek826d7eca2020-03-04 08:48:16 +0100311#if defined(CONFIG_ZYNQMP_FIRMWARE)
Ibai Erkiaga2d9b95b2019-09-27 11:37:04 +0100312 struct udevice *dev;
313
314 uclass_get_device_by_name(UCLASS_FIRMWARE, "zynqmp-power", &dev);
315 if (!dev)
316 panic("PMU Firmware device not found - Enable it");
Michal Simek826d7eca2020-03-04 08:48:16 +0100317#endif
Ibai Erkiaga2d9b95b2019-09-27 11:37:04 +0100318
Luca Ceresoli23e65002019-05-21 18:06:43 +0200319#if defined(CONFIG_SPL_BUILD)
320 /* Check *at build time* if the filename is an non-empty string */
321 if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1)
322 zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj,
323 zynqmp_pm_cfg_obj_size);
324#endif
325
Michal Simekfb7242d2015-06-22 14:31:06 +0200326 printf("EL Level:\tEL%d\n", current_el());
327
Mike Looijmans9863e2f2019-10-18 07:34:13 +0200328 /* Bug in ROM sets wrong value in this register */
329 writel(PS_SYSMON_ANALOG_BUS_VAL, PS_SYSMON_ANALOG_BUS_REG);
330
Michal Simek1aab1142020-09-09 14:41:56 +0200331#if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
Ibai Erkiagae91ca7c2020-08-04 23:17:29 +0100332 zynqmppl.name = zynqmp_get_silicon_idcode_name();
333 printf("Chip ID:\t%s\n", zynqmppl.name);
334 fpga_init();
335 fpga_add(fpga_xilinx, &zynqmppl);
Michal Simekbf0f9ca2018-04-19 15:43:38 +0200336#endif
337
Michal Simek46900462020-02-11 12:43:14 +0100338 if (current_el() == 3)
339 multi_boot();
340
Michal Simek04b7e622015-01-15 10:01:51 +0100341 return 0;
342}
343
344int board_early_init_r(void)
345{
346 u32 val;
347
Siva Durga Prasad Paladugu64d90002017-12-07 15:05:30 +0530348 if (current_el() != 3)
349 return 0;
350
Michal Simek245d5282017-07-12 10:32:18 +0200351 val = readl(&crlapb_base->timestamp_ref_ctrl);
352 val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
353
Siva Durga Prasad Paladugu64d90002017-12-07 15:05:30 +0530354 if (!val) {
Michal Simekc23d3f82015-11-05 08:34:35 +0100355 val = readl(&crlapb_base->timestamp_ref_ctrl);
356 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
357 writel(val, &crlapb_base->timestamp_ref_ctrl);
Michal Simek04b7e622015-01-15 10:01:51 +0100358
Michal Simekc23d3f82015-11-05 08:34:35 +0100359 /* Program freq register in System counter */
360 writel(zynqmp_get_system_timer_freq(),
361 &iou_scntr_secure->base_frequency_id_register);
362 /* And enable system counter */
363 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
364 &iou_scntr_secure->counter_control_register);
365 }
Michal Simek04b7e622015-01-15 10:01:51 +0100366 return 0;
367}
368
Nitin Jainb2eb59b2018-02-16 12:56:17 +0530369unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
Simon Glassed38aef2020-05-10 11:40:03 -0600370 char *const argv[])
Nitin Jainb2eb59b2018-02-16 12:56:17 +0530371{
372 int ret = 0;
373
374 if (current_el() > 1) {
375 smp_kick_all_cpus();
376 dcache_disable();
377 armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
378 ES_TO_AARCH64);
379 } else {
380 printf("FAIL: current EL is not above EL1\n");
381 ret = EINVAL;
382 }
383 return ret;
384}
385
Michal Simek8faa66a2016-02-08 09:34:53 +0100386#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
Simon Glass2f949c32017-03-31 08:40:32 -0600387int dram_init_banksize(void)
Michal Simek8faa66a2016-02-08 09:34:53 +0100388{
Nitin Jain9bcc76f2018-04-20 12:30:40 +0530389 int ret;
390
391 ret = fdtdec_setup_memory_banksize();
392 if (ret)
393 return ret;
394
395 mem_map_fill();
396
397 return 0;
Tom Riniedcfdbd2016-12-09 07:56:54 -0500398}
Michal Simek8faa66a2016-02-08 09:34:53 +0100399
Tom Riniedcfdbd2016-12-09 07:56:54 -0500400int dram_init(void)
401{
Siva Durga Prasad Paladugub3d55ea2018-07-16 15:56:11 +0530402 if (fdtdec_setup_mem_size_base() != 0)
Nathan Rossiac04bfa2016-12-19 00:03:34 +1000403 return -EINVAL;
Tom Riniedcfdbd2016-12-09 07:56:54 -0500404
405 return 0;
Michal Simek8faa66a2016-02-08 09:34:53 +0100406}
407#else
Nitin Jain9bcc76f2018-04-20 12:30:40 +0530408int dram_init_banksize(void)
409{
Nitin Jain9bcc76f2018-04-20 12:30:40 +0530410 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
411 gd->bd->bi_dram[0].size = get_effective_memsize();
Nitin Jain9bcc76f2018-04-20 12:30:40 +0530412
413 mem_map_fill();
414
415 return 0;
416}
417
Michal Simek04b7e622015-01-15 10:01:51 +0100418int dram_init(void)
419{
Michal Simek1b846212018-04-11 16:12:28 +0200420 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
421 CONFIG_SYS_SDRAM_SIZE);
Michal Simek04b7e622015-01-15 10:01:51 +0100422
423 return 0;
424}
Michal Simek8faa66a2016-02-08 09:34:53 +0100425#endif
Michal Simek04b7e622015-01-15 10:01:51 +0100426
Michal Simek04b7e622015-01-15 10:01:51 +0100427void reset_cpu(ulong addr)
428{
429}
430
Michal Simek8ec30042020-08-20 10:54:45 +0200431static u8 __maybe_unused zynqmp_get_bootmode(void)
432{
433 u8 bootmode;
434 u32 reg = 0;
435 int ret;
436
437 ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
438 if (ret)
439 return -EINVAL;
440
441 if (reg >> BOOT_MODE_ALT_SHIFT)
442 reg >>= BOOT_MODE_ALT_SHIFT;
443
444 bootmode = reg & BOOT_MODES_MASK;
445
446 return bootmode;
447}
448
Michal Simek342edfe2018-12-20 09:33:38 +0100449#if defined(CONFIG_BOARD_LATE_INIT)
Michal Simek29b9b712018-05-17 14:06:06 +0200450static const struct {
451 u32 bit;
452 const char *name;
453} reset_reasons[] = {
454 { RESET_REASON_DEBUG_SYS, "DEBUG" },
455 { RESET_REASON_SOFT, "SOFT" },
456 { RESET_REASON_SRST, "SRST" },
457 { RESET_REASON_PSONLY, "PS-ONLY" },
458 { RESET_REASON_PMU, "PMU" },
459 { RESET_REASON_INTERNAL, "INTERNAL" },
460 { RESET_REASON_EXTERNAL, "EXTERNAL" },
461 {}
462};
463
T Karthik Reddy09b6def2019-03-13 20:24:18 +0530464static int reset_reason(void)
Michal Simek29b9b712018-05-17 14:06:06 +0200465{
T Karthik Reddy09b6def2019-03-13 20:24:18 +0530466 u32 reg;
467 int i, ret;
Michal Simek29b9b712018-05-17 14:06:06 +0200468 const char *reason = NULL;
469
T Karthik Reddy09b6def2019-03-13 20:24:18 +0530470 ret = zynqmp_mmio_read((ulong)&crlapb_base->reset_reason, &reg);
471 if (ret)
472 return -EINVAL;
Michal Simek29b9b712018-05-17 14:06:06 +0200473
474 puts("Reset reason:\t");
475
476 for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
T Karthik Reddy09b6def2019-03-13 20:24:18 +0530477 if (reg & reset_reasons[i].bit) {
Michal Simek29b9b712018-05-17 14:06:06 +0200478 reason = reset_reasons[i].name;
479 printf("%s ", reset_reasons[i].name);
480 break;
481 }
482 }
483
484 puts("\n");
485
486 env_set("reset_reason", reason);
487
Michal Simek4c4efde2020-03-23 14:02:01 +0100488 ret = zynqmp_mmio_write((ulong)&crlapb_base->reset_reason, ~0, ~0);
T Karthik Reddy09b6def2019-03-13 20:24:18 +0530489 if (ret)
490 return -EINVAL;
Michal Simek29b9b712018-05-17 14:06:06 +0200491
492 return ret;
493}
494
Michal Simek1ca66d72019-02-14 13:14:30 +0100495static int set_fdtfile(void)
496{
497 char *compatible, *fdtfile;
498 const char *suffix = ".dtb";
499 const char *vendor = "xilinx/";
Igor Lantsmane167bac2020-06-24 14:33:46 +0200500 int fdt_compat_len;
Michal Simek1ca66d72019-02-14 13:14:30 +0100501
502 if (env_get("fdtfile"))
503 return 0;
504
Igor Lantsmane167bac2020-06-24 14:33:46 +0200505 compatible = (char *)fdt_getprop(gd->fdt_blob, 0, "compatible",
506 &fdt_compat_len);
507 if (compatible && fdt_compat_len) {
508 char *name;
509
Michal Simek1ca66d72019-02-14 13:14:30 +0100510 debug("Compatible: %s\n", compatible);
511
Igor Lantsmane167bac2020-06-24 14:33:46 +0200512 name = strchr(compatible, ',');
513 if (!name)
514 return -EINVAL;
Michal Simek1ca66d72019-02-14 13:14:30 +0100515
Igor Lantsmane167bac2020-06-24 14:33:46 +0200516 name++;
517
518 fdtfile = calloc(1, strlen(vendor) + strlen(name) +
Michal Simek1ca66d72019-02-14 13:14:30 +0100519 strlen(suffix) + 1);
520 if (!fdtfile)
521 return -ENOMEM;
522
Igor Lantsmane167bac2020-06-24 14:33:46 +0200523 sprintf(fdtfile, "%s%s%s", vendor, name, suffix);
Michal Simek1ca66d72019-02-14 13:14:30 +0100524
525 env_set("fdtfile", fdtfile);
526 free(fdtfile);
527 }
528
529 return 0;
530}
531
Michal Simek9c91e612020-04-08 11:04:41 +0200532int board_late_init(void)
533{
Michal Simek04b7e622015-01-15 10:01:51 +0100534 u8 bootmode;
Michal Simekf183a982018-04-25 11:20:43 +0200535 struct udevice *dev;
536 int bootseq = -1;
537 int bootseq_len = 0;
Michal Simek7410b142018-04-25 11:10:34 +0200538 int env_targets_len = 0;
Michal Simekecfb6dc2016-04-22 14:28:54 +0200539 const char *mode;
540 char *new_targets;
Siva Durga Prasad Paladugu245c5562017-12-20 16:35:06 +0530541 char *env_targets;
Siva Durga Prasad Paladugue6fd3bb2017-02-21 17:58:28 +0530542 int ret;
Michal Simekecfb6dc2016-04-22 14:28:54 +0200543
Michal Simek482f5492018-10-05 08:55:16 +0200544#if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
545 usb_ether_init();
546#endif
547
Michal Simekecfb6dc2016-04-22 14:28:54 +0200548 if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
549 debug("Saved variables - Skipping\n");
550 return 0;
551 }
Michal Simek04b7e622015-01-15 10:01:51 +0100552
Michal Simekbab07b62020-07-28 12:45:47 +0200553 if (!CONFIG_IS_ENABLED(ENV_VARS_UBOOT_RUNTIME_CONFIG))
554 return 0;
555
Michal Simek1ca66d72019-02-14 13:14:30 +0100556 ret = set_fdtfile();
557 if (ret)
558 return ret;
559
Michal Simek9c91e612020-04-08 11:04:41 +0200560 bootmode = zynqmp_get_bootmode();
Michal Simek04b7e622015-01-15 10:01:51 +0100561
Michal Simekc5d95232015-09-20 17:20:42 +0200562 puts("Bootmode: ");
Michal Simek04b7e622015-01-15 10:01:51 +0100563 switch (bootmode) {
Michal Simek12398ea2016-08-19 14:14:52 +0200564 case USB_MODE:
565 puts("USB_MODE\n");
566 mode = "usb";
Michal Simek43380352017-12-01 15:18:24 +0100567 env_set("modeboot", "usb_dfu_spl");
Michal Simek12398ea2016-08-19 14:14:52 +0200568 break;
Siva Durga Prasad Paladugu30f0fc72015-03-13 11:10:26 +0530569 case JTAG_MODE:
Michal Simekc5d95232015-09-20 17:20:42 +0200570 puts("JTAG_MODE\n");
Siva Durga Prasad Paladugu9c441702019-06-25 17:41:09 +0530571 mode = "jtag pxe dhcp";
Michal Simek43380352017-12-01 15:18:24 +0100572 env_set("modeboot", "jtagboot");
Siva Durga Prasad Paladugu30f0fc72015-03-13 11:10:26 +0530573 break;
574 case QSPI_MODE_24BIT:
575 case QSPI_MODE_32BIT:
Michal Simekecfb6dc2016-04-22 14:28:54 +0200576 mode = "qspi0";
Michal Simekc5d95232015-09-20 17:20:42 +0200577 puts("QSPI_MODE\n");
Michal Simek43380352017-12-01 15:18:24 +0100578 env_set("modeboot", "qspiboot");
Siva Durga Prasad Paladugu30f0fc72015-03-13 11:10:26 +0530579 break;
Michal Simek02d66cd2015-04-15 15:02:28 +0200580 case EMMC_MODE:
Michal Simekdf7ff0a2015-10-05 15:59:38 +0200581 puts("EMMC_MODE\n");
T Karthik Reddy19735c32019-12-17 06:41:42 -0700582 if (uclass_get_device_by_name(UCLASS_MMC,
583 "mmc@ff160000", &dev) &&
584 uclass_get_device_by_name(UCLASS_MMC,
585 "sdhci@ff160000", &dev)) {
586 puts("Boot from EMMC but without SD0 enabled!\n");
587 return -1;
588 }
589 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
590
591 mode = "mmc";
592 bootseq = dev->seq;
Michal Simekdf7ff0a2015-10-05 15:59:38 +0200593 break;
594 case SD_MODE:
Michal Simekc5d95232015-09-20 17:20:42 +0200595 puts("SD_MODE\n");
Michal Simekf183a982018-04-25 11:20:43 +0200596 if (uclass_get_device_by_name(UCLASS_MMC,
Siva Durga Prasad Paladugue91778d2019-01-03 15:44:24 +0530597 "mmc@ff160000", &dev) &&
598 uclass_get_device_by_name(UCLASS_MMC,
Michal Simekf183a982018-04-25 11:20:43 +0200599 "sdhci@ff160000", &dev)) {
600 puts("Boot from SD0 but without SD0 enabled!\n");
601 return -1;
602 }
603 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
604
605 mode = "mmc";
606 bootseq = dev->seq;
Michal Simek43380352017-12-01 15:18:24 +0100607 env_set("modeboot", "sdboot");
Michal Simek04b7e622015-01-15 10:01:51 +0100608 break;
Siva Durga Prasad Paladugu29a77d22016-09-21 11:45:05 +0530609 case SD1_LSHFT_MODE:
610 puts("LVL_SHFT_");
611 /* fall through */
Michal Simek108e1842015-10-05 10:51:12 +0200612 case SD_MODE1:
Michal Simekc5d95232015-09-20 17:20:42 +0200613 puts("SD_MODE1\n");
Michal Simekf183a982018-04-25 11:20:43 +0200614 if (uclass_get_device_by_name(UCLASS_MMC,
Siva Durga Prasad Paladugue91778d2019-01-03 15:44:24 +0530615 "mmc@ff170000", &dev) &&
616 uclass_get_device_by_name(UCLASS_MMC,
Michal Simekf183a982018-04-25 11:20:43 +0200617 "sdhci@ff170000", &dev)) {
618 puts("Boot from SD1 but without SD1 enabled!\n");
619 return -1;
620 }
621 debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
622
623 mode = "mmc";
624 bootseq = dev->seq;
Michal Simek43380352017-12-01 15:18:24 +0100625 env_set("modeboot", "sdboot");
Michal Simek108e1842015-10-05 10:51:12 +0200626 break;
627 case NAND_MODE:
Michal Simekc5d95232015-09-20 17:20:42 +0200628 puts("NAND_MODE\n");
Michal Simekecfb6dc2016-04-22 14:28:54 +0200629 mode = "nand0";
Michal Simek43380352017-12-01 15:18:24 +0100630 env_set("modeboot", "nandboot");
Michal Simek108e1842015-10-05 10:51:12 +0200631 break;
Michal Simek04b7e622015-01-15 10:01:51 +0100632 default:
Michal Simekecfb6dc2016-04-22 14:28:54 +0200633 mode = "";
Michal Simek04b7e622015-01-15 10:01:51 +0100634 printf("Invalid Boot Mode:0x%x\n", bootmode);
635 break;
636 }
637
Michal Simekf183a982018-04-25 11:20:43 +0200638 if (bootseq >= 0) {
639 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
640 debug("Bootseq len: %x\n", bootseq_len);
641 }
642
Michal Simekecfb6dc2016-04-22 14:28:54 +0200643 /*
644 * One terminating char + one byte for space between mode
645 * and default boot_targets
646 */
Siva Durga Prasad Paladugu245c5562017-12-20 16:35:06 +0530647 env_targets = env_get("boot_targets");
Michal Simek7410b142018-04-25 11:10:34 +0200648 if (env_targets)
649 env_targets_len = strlen(env_targets);
650
Michal Simekf183a982018-04-25 11:20:43 +0200651 new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
652 bootseq_len);
Michal Simek089b84d2018-06-13 09:42:41 +0200653 if (!new_targets)
654 return -ENOMEM;
Michal Simek7410b142018-04-25 11:10:34 +0200655
Michal Simekf183a982018-04-25 11:20:43 +0200656 if (bootseq >= 0)
657 sprintf(new_targets, "%s%x %s", mode, bootseq,
658 env_targets ? env_targets : "");
659 else
660 sprintf(new_targets, "%s %s", mode,
661 env_targets ? env_targets : "");
Michal Simekecfb6dc2016-04-22 14:28:54 +0200662
Simon Glass6a38e412017-08-03 12:22:09 -0600663 env_set("boot_targets", new_targets);
Michal Simekecfb6dc2016-04-22 14:28:54 +0200664
Michal Simek29b9b712018-05-17 14:06:06 +0200665 reset_reason();
666
Michal Simek705d44a2020-03-31 12:39:37 +0200667 return board_late_init_xilinx();
Michal Simek04b7e622015-01-15 10:01:51 +0100668}
Michal Simek342edfe2018-12-20 09:33:38 +0100669#endif
Siva Durga Prasad Paladugu650e0a32015-08-04 13:01:05 +0530670
671int checkboard(void)
672{
Michal Simek47ce9362016-01-25 11:04:21 +0100673 puts("Board: Xilinx ZynqMP\n");
Siva Durga Prasad Paladugu650e0a32015-08-04 13:01:05 +0530674 return 0;
675}
Michal Simek8d4a8d42020-07-30 13:37:49 +0200676
677enum env_location env_get_location(enum env_operation op, int prio)
678{
679 u32 bootmode = zynqmp_get_bootmode();
680
681 if (prio)
682 return ENVL_UNKNOWN;
683
684 switch (bootmode) {
685 case EMMC_MODE:
686 case SD_MODE:
687 case SD1_LSHFT_MODE:
688 case SD_MODE1:
689 if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
690 return ENVL_FAT;
691 if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
692 return ENVL_EXT4;
693 return ENVL_UNKNOWN;
694 case NAND_MODE:
695 if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
696 return ENVL_NAND;
697 if (IS_ENABLED(CONFIG_ENV_IS_IN_UBI))
698 return ENVL_UBI;
699 return ENVL_UNKNOWN;
700 case QSPI_MODE_24BIT:
701 case QSPI_MODE_32BIT:
702 if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
703 return ENVL_SPI_FLASH;
704 return ENVL_UNKNOWN;
705 case JTAG_MODE:
706 default:
707 return ENVL_NOWHERE;
708 }
709}