blob: dae1b3c5cf043b538d77bf4269e3fcca52bdc489 [file] [log] [blame]
wdenk5d3207d2002-08-21 22:08:56 +00001/*
Wolfgang Denk331dfe82008-03-26 15:38:47 +01002 * (C) Copyright 2001-2008
wdenk5d3207d2002-08-21 22:08:56 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * Keith Outwater, keith_outwater@mvis.com`
5 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
wdenk5d3207d2002-08-21 22:08:56 +00007 */
8
9/*
10 * Date & Time support (no alarms) for Dallas Semiconductor (now Maxim)
11 * DS1337 Real Time Clock (RTC).
12 */
13
14#include <common.h>
15#include <command.h>
16#include <rtc.h>
17#include <i2c.h>
18
Michal Simekc3e6c552008-07-14 19:45:37 +020019#if defined(CONFIG_CMD_DATE)
wdenk5d3207d2002-08-21 22:08:56 +000020
wdenk5d3207d2002-08-21 22:08:56 +000021/*
22 * RTC register addresses
23 */
Kenth Eriksson78196332012-07-12 19:59:44 +000024#if defined CONFIG_RTC_DS1337
wdenk5d3207d2002-08-21 22:08:56 +000025#define RTC_SEC_REG_ADDR 0x0
26#define RTC_MIN_REG_ADDR 0x1
27#define RTC_HR_REG_ADDR 0x2
28#define RTC_DAY_REG_ADDR 0x3
29#define RTC_DATE_REG_ADDR 0x4
30#define RTC_MON_REG_ADDR 0x5
31#define RTC_YR_REG_ADDR 0x6
32#define RTC_CTL_REG_ADDR 0x0e
33#define RTC_STAT_REG_ADDR 0x0f
Werner Pfister3563ca42009-09-21 14:49:55 +020034#define RTC_TC_REG_ADDR 0x10
Kenth Eriksson78196332012-07-12 19:59:44 +000035#elif defined CONFIG_RTC_DS1388
36#define RTC_SEC_REG_ADDR 0x1
37#define RTC_MIN_REG_ADDR 0x2
38#define RTC_HR_REG_ADDR 0x3
39#define RTC_DAY_REG_ADDR 0x4
40#define RTC_DATE_REG_ADDR 0x5
41#define RTC_MON_REG_ADDR 0x6
42#define RTC_YR_REG_ADDR 0x7
43#define RTC_CTL_REG_ADDR 0x0c
44#define RTC_STAT_REG_ADDR 0x0b
45#define RTC_TC_REG_ADDR 0x0a
46#endif
wdenk5d3207d2002-08-21 22:08:56 +000047
48/*
49 * RTC control register bits
50 */
Wolfgang Denk331dfe82008-03-26 15:38:47 +010051#define RTC_CTL_BIT_A1IE 0x1 /* Alarm 1 interrupt enable */
52#define RTC_CTL_BIT_A2IE 0x2 /* Alarm 2 interrupt enable */
53#define RTC_CTL_BIT_INTCN 0x4 /* Interrupt control */
54#define RTC_CTL_BIT_RS1 0x8 /* Rate select 1 */
55#define RTC_CTL_BIT_RS2 0x10 /* Rate select 2 */
56#define RTC_CTL_BIT_DOSC 0x80 /* Disable Oscillator */
wdenk5d3207d2002-08-21 22:08:56 +000057
58/*
59 * RTC status register bits
60 */
Wolfgang Denk331dfe82008-03-26 15:38:47 +010061#define RTC_STAT_BIT_A1F 0x1 /* Alarm 1 flag */
62#define RTC_STAT_BIT_A2F 0x2 /* Alarm 2 flag */
63#define RTC_STAT_BIT_OSF 0x80 /* Oscillator stop flag */
wdenk5d3207d2002-08-21 22:08:56 +000064
65
66static uchar rtc_read (uchar reg);
67static void rtc_write (uchar reg, uchar val);
wdenk5d3207d2002-08-21 22:08:56 +000068
69/*
70 * Get the current time from the RTC
71 */
Yuri Tikhonov9bacd942008-03-20 17:56:04 +030072int rtc_get (struct rtc_time *tmp)
wdenk5d3207d2002-08-21 22:08:56 +000073{
Yuri Tikhonov9bacd942008-03-20 17:56:04 +030074 int rel = 0;
wdenk5d3207d2002-08-21 22:08:56 +000075 uchar sec, min, hour, mday, wday, mon_cent, year, control, status;
76
77 control = rtc_read (RTC_CTL_REG_ADDR);
78 status = rtc_read (RTC_STAT_REG_ADDR);
79 sec = rtc_read (RTC_SEC_REG_ADDR);
80 min = rtc_read (RTC_MIN_REG_ADDR);
81 hour = rtc_read (RTC_HR_REG_ADDR);
82 wday = rtc_read (RTC_DAY_REG_ADDR);
83 mday = rtc_read (RTC_DATE_REG_ADDR);
84 mon_cent = rtc_read (RTC_MON_REG_ADDR);
85 year = rtc_read (RTC_YR_REG_ADDR);
86
Kenth Eriksson78196332012-07-12 19:59:44 +000087 /* No century bit, assume year 2000 */
88#ifdef CONFIG_RTC_DS1388
89 mon_cent |= 0x80;
90#endif
91
Wolfgang Denkc0b15f02011-10-29 09:39:11 +000092 debug("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x "
wdenk5d3207d2002-08-21 22:08:56 +000093 "hr: %02x min: %02x sec: %02x control: %02x status: %02x\n",
94 year, mon_cent, mday, wday, hour, min, sec, control, status);
95
96 if (status & RTC_STAT_BIT_OSF) {
97 printf ("### Warning: RTC oscillator has stopped\n");
98 /* clear the OSF flag */
99 rtc_write (RTC_STAT_REG_ADDR,
100 rtc_read (RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_OSF);
Yuri Tikhonov9bacd942008-03-20 17:56:04 +0300101 rel = -1;
wdenk5d3207d2002-08-21 22:08:56 +0000102 }
103
104 tmp->tm_sec = bcd2bin (sec & 0x7F);
105 tmp->tm_min = bcd2bin (min & 0x7F);
106 tmp->tm_hour = bcd2bin (hour & 0x3F);
107 tmp->tm_mday = bcd2bin (mday & 0x3F);
108 tmp->tm_mon = bcd2bin (mon_cent & 0x1F);
109 tmp->tm_year = bcd2bin (year) + ((mon_cent & 0x80) ? 2000 : 1900);
110 tmp->tm_wday = bcd2bin ((wday - 1) & 0x07);
111 tmp->tm_yday = 0;
112 tmp->tm_isdst= 0;
113
Wolfgang Denkc0b15f02011-10-29 09:39:11 +0000114 debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
wdenk5d3207d2002-08-21 22:08:56 +0000115 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
116 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
Yuri Tikhonov9bacd942008-03-20 17:56:04 +0300117
118 return rel;
wdenk5d3207d2002-08-21 22:08:56 +0000119}
120
121
122/*
123 * Set the RTC
124 */
Jean-Christophe PLAGNIOL-VILLARD97a2e102008-09-01 23:06:23 +0200125int rtc_set (struct rtc_time *tmp)
wdenk5d3207d2002-08-21 22:08:56 +0000126{
127 uchar century;
128
Wolfgang Denkc0b15f02011-10-29 09:39:11 +0000129 debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
wdenk5d3207d2002-08-21 22:08:56 +0000130 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
131 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
132
133 rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100));
134
135 century = (tmp->tm_year >= 2000) ? 0x80 : 0;
136 rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon) | century);
137
138 rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1));
139 rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday));
140 rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour));
141 rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
142 rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));
Jean-Christophe PLAGNIOL-VILLARD97a2e102008-09-01 23:06:23 +0200143
144 return 0;
wdenk5d3207d2002-08-21 22:08:56 +0000145}
146
147
148/*
149 * Reset the RTC. We also enable the oscillator output on the
150 * SQW/INTB* pin and program it for 32,768 Hz output. Note that
151 * according to the datasheet, turning on the square wave output
152 * increases the current drain on the backup battery from about
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200153 * 600 nA to 2uA. Define CONFIG_SYS_RTC_DS1337_NOOSC if you wish to turn
Joakim Tjernlund2ef27312008-03-26 13:02:13 +0100154 * off the OSC output.
wdenk5d3207d2002-08-21 22:08:56 +0000155 */
Kenth Eriksson78196332012-07-12 19:59:44 +0000156
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200157#ifdef CONFIG_SYS_RTC_DS1337_NOOSC
Joakim Tjernlund2ef27312008-03-26 13:02:13 +0100158 #define RTC_DS1337_RESET_VAL \
Wolfgang Denk331dfe82008-03-26 15:38:47 +0100159 (RTC_CTL_BIT_INTCN | RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2)
Joakim Tjernlund2ef27312008-03-26 13:02:13 +0100160#else
161 #define RTC_DS1337_RESET_VAL (RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2)
162#endif
wdenk5d3207d2002-08-21 22:08:56 +0000163void rtc_reset (void)
164{
Kenth Eriksson78196332012-07-12 19:59:44 +0000165#ifdef CONFIG_SYS_RTC_DS1337
Joakim Tjernlund2ef27312008-03-26 13:02:13 +0100166 rtc_write (RTC_CTL_REG_ADDR, RTC_DS1337_RESET_VAL);
Kenth Eriksson78196332012-07-12 19:59:44 +0000167#elif defined CONFIG_SYS_RTC_DS1388
168 rtc_write(RTC_CTL_REG_ADDR, 0x0); /* hw default */
169#endif
Werner Pfister3563ca42009-09-21 14:49:55 +0200170#ifdef CONFIG_SYS_DS1339_TCR_VAL
171 rtc_write (RTC_TC_REG_ADDR, CONFIG_SYS_DS1339_TCR_VAL);
172#endif
Kenth Eriksson78196332012-07-12 19:59:44 +0000173#ifdef CONFIG_SYS_DS1388_TCR_VAL
174 rtc_write(RTC_TC_REG_ADDR, CONFIG_SYS_DS1388_TCR_VAL);
175#endif
wdenk5d3207d2002-08-21 22:08:56 +0000176}
177
178
179/*
180 * Helper functions
181 */
182
183static
184uchar rtc_read (uchar reg)
185{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200186 return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
wdenk5d3207d2002-08-21 22:08:56 +0000187}
188
189
190static void rtc_write (uchar reg, uchar val)
191{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200192 i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
wdenk5d3207d2002-08-21 22:08:56 +0000193}
194
Jon Loeliger07efe2a2007-07-10 10:27:39 -0500195#endif