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wdenk5d3207d2002-08-21 22:08:56 +00001/*
Wolfgang Denk331dfe82008-03-26 15:38:47 +01002 * (C) Copyright 2001-2008
wdenk5d3207d2002-08-21 22:08:56 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * Keith Outwater, keith_outwater@mvis.com`
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25/*
26 * Date & Time support (no alarms) for Dallas Semiconductor (now Maxim)
27 * DS1337 Real Time Clock (RTC).
28 */
29
30#include <common.h>
31#include <command.h>
32#include <rtc.h>
33#include <i2c.h>
34
Michal Simekc3e6c552008-07-14 19:45:37 +020035#if defined(CONFIG_CMD_DATE)
wdenk5d3207d2002-08-21 22:08:56 +000036
wdenk5d3207d2002-08-21 22:08:56 +000037/*
38 * RTC register addresses
39 */
Kenth Eriksson78196332012-07-12 19:59:44 +000040#if defined CONFIG_RTC_DS1337
wdenk5d3207d2002-08-21 22:08:56 +000041#define RTC_SEC_REG_ADDR 0x0
42#define RTC_MIN_REG_ADDR 0x1
43#define RTC_HR_REG_ADDR 0x2
44#define RTC_DAY_REG_ADDR 0x3
45#define RTC_DATE_REG_ADDR 0x4
46#define RTC_MON_REG_ADDR 0x5
47#define RTC_YR_REG_ADDR 0x6
48#define RTC_CTL_REG_ADDR 0x0e
49#define RTC_STAT_REG_ADDR 0x0f
Werner Pfister3563ca42009-09-21 14:49:55 +020050#define RTC_TC_REG_ADDR 0x10
Kenth Eriksson78196332012-07-12 19:59:44 +000051#elif defined CONFIG_RTC_DS1388
52#define RTC_SEC_REG_ADDR 0x1
53#define RTC_MIN_REG_ADDR 0x2
54#define RTC_HR_REG_ADDR 0x3
55#define RTC_DAY_REG_ADDR 0x4
56#define RTC_DATE_REG_ADDR 0x5
57#define RTC_MON_REG_ADDR 0x6
58#define RTC_YR_REG_ADDR 0x7
59#define RTC_CTL_REG_ADDR 0x0c
60#define RTC_STAT_REG_ADDR 0x0b
61#define RTC_TC_REG_ADDR 0x0a
62#endif
wdenk5d3207d2002-08-21 22:08:56 +000063
64/*
65 * RTC control register bits
66 */
Wolfgang Denk331dfe82008-03-26 15:38:47 +010067#define RTC_CTL_BIT_A1IE 0x1 /* Alarm 1 interrupt enable */
68#define RTC_CTL_BIT_A2IE 0x2 /* Alarm 2 interrupt enable */
69#define RTC_CTL_BIT_INTCN 0x4 /* Interrupt control */
70#define RTC_CTL_BIT_RS1 0x8 /* Rate select 1 */
71#define RTC_CTL_BIT_RS2 0x10 /* Rate select 2 */
72#define RTC_CTL_BIT_DOSC 0x80 /* Disable Oscillator */
wdenk5d3207d2002-08-21 22:08:56 +000073
74/*
75 * RTC status register bits
76 */
Wolfgang Denk331dfe82008-03-26 15:38:47 +010077#define RTC_STAT_BIT_A1F 0x1 /* Alarm 1 flag */
78#define RTC_STAT_BIT_A2F 0x2 /* Alarm 2 flag */
79#define RTC_STAT_BIT_OSF 0x80 /* Oscillator stop flag */
wdenk5d3207d2002-08-21 22:08:56 +000080
81
82static uchar rtc_read (uchar reg);
83static void rtc_write (uchar reg, uchar val);
wdenk5d3207d2002-08-21 22:08:56 +000084
85/*
86 * Get the current time from the RTC
87 */
Yuri Tikhonov9bacd942008-03-20 17:56:04 +030088int rtc_get (struct rtc_time *tmp)
wdenk5d3207d2002-08-21 22:08:56 +000089{
Yuri Tikhonov9bacd942008-03-20 17:56:04 +030090 int rel = 0;
wdenk5d3207d2002-08-21 22:08:56 +000091 uchar sec, min, hour, mday, wday, mon_cent, year, control, status;
92
93 control = rtc_read (RTC_CTL_REG_ADDR);
94 status = rtc_read (RTC_STAT_REG_ADDR);
95 sec = rtc_read (RTC_SEC_REG_ADDR);
96 min = rtc_read (RTC_MIN_REG_ADDR);
97 hour = rtc_read (RTC_HR_REG_ADDR);
98 wday = rtc_read (RTC_DAY_REG_ADDR);
99 mday = rtc_read (RTC_DATE_REG_ADDR);
100 mon_cent = rtc_read (RTC_MON_REG_ADDR);
101 year = rtc_read (RTC_YR_REG_ADDR);
102
Kenth Eriksson78196332012-07-12 19:59:44 +0000103 /* No century bit, assume year 2000 */
104#ifdef CONFIG_RTC_DS1388
105 mon_cent |= 0x80;
106#endif
107
Wolfgang Denkc0b15f02011-10-29 09:39:11 +0000108 debug("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x "
wdenk5d3207d2002-08-21 22:08:56 +0000109 "hr: %02x min: %02x sec: %02x control: %02x status: %02x\n",
110 year, mon_cent, mday, wday, hour, min, sec, control, status);
111
112 if (status & RTC_STAT_BIT_OSF) {
113 printf ("### Warning: RTC oscillator has stopped\n");
114 /* clear the OSF flag */
115 rtc_write (RTC_STAT_REG_ADDR,
116 rtc_read (RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_OSF);
Yuri Tikhonov9bacd942008-03-20 17:56:04 +0300117 rel = -1;
wdenk5d3207d2002-08-21 22:08:56 +0000118 }
119
120 tmp->tm_sec = bcd2bin (sec & 0x7F);
121 tmp->tm_min = bcd2bin (min & 0x7F);
122 tmp->tm_hour = bcd2bin (hour & 0x3F);
123 tmp->tm_mday = bcd2bin (mday & 0x3F);
124 tmp->tm_mon = bcd2bin (mon_cent & 0x1F);
125 tmp->tm_year = bcd2bin (year) + ((mon_cent & 0x80) ? 2000 : 1900);
126 tmp->tm_wday = bcd2bin ((wday - 1) & 0x07);
127 tmp->tm_yday = 0;
128 tmp->tm_isdst= 0;
129
Wolfgang Denkc0b15f02011-10-29 09:39:11 +0000130 debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
wdenk5d3207d2002-08-21 22:08:56 +0000131 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
132 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
Yuri Tikhonov9bacd942008-03-20 17:56:04 +0300133
134 return rel;
wdenk5d3207d2002-08-21 22:08:56 +0000135}
136
137
138/*
139 * Set the RTC
140 */
Jean-Christophe PLAGNIOL-VILLARD97a2e102008-09-01 23:06:23 +0200141int rtc_set (struct rtc_time *tmp)
wdenk5d3207d2002-08-21 22:08:56 +0000142{
143 uchar century;
144
Wolfgang Denkc0b15f02011-10-29 09:39:11 +0000145 debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
wdenk5d3207d2002-08-21 22:08:56 +0000146 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
147 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
148
149 rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100));
150
151 century = (tmp->tm_year >= 2000) ? 0x80 : 0;
152 rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon) | century);
153
154 rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1));
155 rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday));
156 rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour));
157 rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
158 rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));
Jean-Christophe PLAGNIOL-VILLARD97a2e102008-09-01 23:06:23 +0200159
160 return 0;
wdenk5d3207d2002-08-21 22:08:56 +0000161}
162
163
164/*
165 * Reset the RTC. We also enable the oscillator output on the
166 * SQW/INTB* pin and program it for 32,768 Hz output. Note that
167 * according to the datasheet, turning on the square wave output
168 * increases the current drain on the backup battery from about
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200169 * 600 nA to 2uA. Define CONFIG_SYS_RTC_DS1337_NOOSC if you wish to turn
Joakim Tjernlund2ef27312008-03-26 13:02:13 +0100170 * off the OSC output.
wdenk5d3207d2002-08-21 22:08:56 +0000171 */
Kenth Eriksson78196332012-07-12 19:59:44 +0000172
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200173#ifdef CONFIG_SYS_RTC_DS1337_NOOSC
Joakim Tjernlund2ef27312008-03-26 13:02:13 +0100174 #define RTC_DS1337_RESET_VAL \
Wolfgang Denk331dfe82008-03-26 15:38:47 +0100175 (RTC_CTL_BIT_INTCN | RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2)
Joakim Tjernlund2ef27312008-03-26 13:02:13 +0100176#else
177 #define RTC_DS1337_RESET_VAL (RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2)
178#endif
wdenk5d3207d2002-08-21 22:08:56 +0000179void rtc_reset (void)
180{
Kenth Eriksson78196332012-07-12 19:59:44 +0000181#ifdef CONFIG_SYS_RTC_DS1337
Joakim Tjernlund2ef27312008-03-26 13:02:13 +0100182 rtc_write (RTC_CTL_REG_ADDR, RTC_DS1337_RESET_VAL);
Kenth Eriksson78196332012-07-12 19:59:44 +0000183#elif defined CONFIG_SYS_RTC_DS1388
184 rtc_write(RTC_CTL_REG_ADDR, 0x0); /* hw default */
185#endif
Werner Pfister3563ca42009-09-21 14:49:55 +0200186#ifdef CONFIG_SYS_DS1339_TCR_VAL
187 rtc_write (RTC_TC_REG_ADDR, CONFIG_SYS_DS1339_TCR_VAL);
188#endif
Kenth Eriksson78196332012-07-12 19:59:44 +0000189#ifdef CONFIG_SYS_DS1388_TCR_VAL
190 rtc_write(RTC_TC_REG_ADDR, CONFIG_SYS_DS1388_TCR_VAL);
191#endif
wdenk5d3207d2002-08-21 22:08:56 +0000192}
193
194
195/*
196 * Helper functions
197 */
198
199static
200uchar rtc_read (uchar reg)
201{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200202 return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
wdenk5d3207d2002-08-21 22:08:56 +0000203}
204
205
206static void rtc_write (uchar reg, uchar val)
207{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200208 i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
wdenk5d3207d2002-08-21 22:08:56 +0000209}
210
Jon Loeliger07efe2a2007-07-10 10:27:39 -0500211#endif