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git01.mediatek.com / filogic / uboot / fec4e17da84e22b9578a0fadd02acbfec8e9e78d / . / include / ppc440.h
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wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1/*----------------------------------------------------------------------------+
2|
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]3| This source code has been made available to you by IBM on an AS-IS
4| basis. Anyone receiving this source is licensed under IBM
5| copyrights to use it in any way he or she deems fit, including
6| copying it, modifying it, compiling it, and redistributing it either
7| with or without modifications. No license under IBM patents or
8| patent applications is to be implied by the copyright license.
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]9|
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]10| Any user of this software should understand that IBM cannot provide
11| technical support for this software and will not be responsible for
12| any consequences resulting from the use of this software.
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]13|
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]14| Any person who transfers this source code or any derivative work
15| must include the IBM copyright notice, this paragraph, and the
16| preceding two paragraphs in the transferred software.
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]17|
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]18| COPYRIGHT I B M CORPORATION 1999
19| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]20+----------------------------------------------------------------------------*/
21
Larry Johnson19b3d372007-12-22 15:15:13 -0500[diff] [blame]22/*
23 * (C) Copyright 2006
24 * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
25 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
26 * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
27 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
28 * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
29 *
30 * This program is free software; you can redistribute it and/or
31 * modify it under the terms of the GNU General Public License as
32 * published by the Free Software Foundation; either version 2 of
33 * the License, or (at your option) any later version.
34 *
35 * This program is distributed in the hope that it will be useful,
36 * but WITHOUT ANY WARRANTY; without even the implied warranty of
37 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
38 * GNU General Public License for more details.
39 *
40 * You should have received a copy of the GNU General Public License
41 * along with this program; if not, write to the Free Software
42 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
43 * MA 02111-1307 USA
44 */
45
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]46#ifndef __PPC440_H__
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]47#define __PPC440_H__
48
Stefan Roeseeff3a0a2007-10-31 17:55:58 +0100[diff] [blame]49#define CFG_DCACHE_SIZE (32 << 10) /* For AMCC 440 CPUs */
50
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]51/*--------------------------------------------------------------------- */
52/* Special Purpose Registers */
53/*--------------------------------------------------------------------- */
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]54#define xer_reg 0x001
55#define lr_reg 0x008
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]56#define dec 0x016 /* decrementer */
57#define srr0 0x01a /* save/restore register 0 */
58#define srr1 0x01b /* save/restore register 1 */
59#define pid 0x030 /* process id */
60#define decar 0x036 /* decrementer auto-reload */
61#define csrr0 0x03a /* critical save/restore register 0 */
62#define csrr1 0x03b /* critical save/restore register 1 */
63#define dear 0x03d /* data exception address register */
64#define esr 0x03e /* exception syndrome register */
65#define ivpr 0x03f /* interrupt prefix register */
66#define usprg0 0x100 /* user special purpose register general 0 */
67#define usprg1 0x110 /* user special purpose register general 1 */
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]68#define tblr 0x10c /* time base lower, read only */
69#define tbur 0x10d /* time base upper, read only */
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]70#define sprg1 0x111 /* special purpose register general 1 */
71#define sprg2 0x112 /* special purpose register general 2 */
72#define sprg3 0x113 /* special purpose register general 3 */
73#define sprg4 0x114 /* special purpose register general 4 */
74#define sprg5 0x115 /* special purpose register general 5 */
75#define sprg6 0x116 /* special purpose register general 6 */
76#define sprg7 0x117 /* special purpose register general 7 */
77#define tbl 0x11c /* time base lower (supervisor)*/
78#define tbu 0x11d /* time base upper (supervisor)*/
79#define pir 0x11e /* processor id register */
80/*#define pvr 0x11f processor version register */
81#define dbsr 0x130 /* debug status register */
82#define dbcr0 0x134 /* debug control register 0 */
83#define dbcr1 0x135 /* debug control register 1 */
84#define dbcr2 0x136 /* debug control register 2 */
85#define iac1 0x138 /* instruction address compare 1 */
86#define iac2 0x139 /* instruction address compare 2 */
87#define iac3 0x13a /* instruction address compare 3 */
88#define iac4 0x13b /* instruction address compare 4 */
89#define dac1 0x13c /* data address compare 1 */
90#define dac2 0x13d /* data address compare 2 */
91#define dvc1 0x13e /* data value compare 1 */
92#define dvc2 0x13f /* data value compare 2 */
93#define tsr 0x150 /* timer status register */
94#define tcr 0x154 /* timer control register */
95#define ivor0 0x190 /* interrupt vector offset register 0 */
96#define ivor1 0x191 /* interrupt vector offset register 1 */
97#define ivor2 0x192 /* interrupt vector offset register 2 */
98#define ivor3 0x193 /* interrupt vector offset register 3 */
99#define ivor4 0x194 /* interrupt vector offset register 4 */
100#define ivor5 0x195 /* interrupt vector offset register 5 */
101#define ivor6 0x196 /* interrupt vector offset register 6 */
102#define ivor7 0x197 /* interrupt vector offset register 7 */
103#define ivor8 0x198 /* interrupt vector offset register 8 */
104#define ivor9 0x199 /* interrupt vector offset register 9 */
105#define ivor10 0x19a /* interrupt vector offset register 10 */
106#define ivor11 0x19b /* interrupt vector offset register 11 */
107#define ivor12 0x19c /* interrupt vector offset register 12 */
108#define ivor13 0x19d /* interrupt vector offset register 13 */
109#define ivor14 0x19e /* interrupt vector offset register 14 */
110#define ivor15 0x19f /* interrupt vector offset register 15 */
Grzegorz Bernacki837bc5b2007-06-15 11:19:28 +0200[diff] [blame]111#if defined(CONFIG_440)
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]112#define mcsrr0 0x23a /* machine check save/restore register 0 */
113#define mcsrr1 0x23b /* mahcine check save/restore register 1 */
114#define mcsr 0x23c /* machine check status register */
115#endif
116#define inv0 0x370 /* instruction cache normal victim 0 */
117#define inv1 0x371 /* instruction cache normal victim 1 */
118#define inv2 0x372 /* instruction cache normal victim 2 */
119#define inv3 0x373 /* instruction cache normal victim 3 */
120#define itv0 0x374 /* instruction cache transient victim 0 */
121#define itv1 0x375 /* instruction cache transient victim 1 */
122#define itv2 0x376 /* instruction cache transient victim 2 */
123#define itv3 0x377 /* instruction cache transient victim 3 */
124#define dnv0 0x390 /* data cache normal victim 0 */
125#define dnv1 0x391 /* data cache normal victim 1 */
126#define dnv2 0x392 /* data cache normal victim 2 */
127#define dnv3 0x393 /* data cache normal victim 3 */
128#define dtv0 0x394 /* data cache transient victim 0 */
129#define dtv1 0x395 /* data cache transient victim 1 */
130#define dtv2 0x396 /* data cache transient victim 2 */
131#define dtv3 0x397 /* data cache transient victim 3 */
132#define dvlim 0x398 /* data cache victim limit */
133#define ivlim 0x399 /* instruction cache victim limit */
134#define rstcfg 0x39b /* reset configuration */
135#define dcdbtrl 0x39c /* data cache debug tag register low */
136#define dcdbtrh 0x39d /* data cache debug tag register high */
137#define icdbtrl 0x39e /* instruction cache debug tag register low */
138#define icdbtrh 0x39f /* instruction cache debug tag register high */
139#define mmucr 0x3b2 /* mmu control register */
140#define ccr0 0x3b3 /* core configuration register 0 */
Wolfgang Denk70df7bc2007-06-22 23:59:00 +0200[diff] [blame]141#define ccr1 0x378 /* core configuration for 440x5 only */
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]142#define icdbdr 0x3d3 /* instruction cache debug data register */
143#define dbdr 0x3f3 /* debug data register */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]144
145/******************************************************************************
146 * DCRs & Related
147 ******************************************************************************/
148
149/*-----------------------------------------------------------------------------
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]150 | Clocking Controller
151 +----------------------------------------------------------------------------*/
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]152/* values for clkcfga register - indirect addressing of these regs */
153#define clk_clkukpd 0x0020
154#define clk_pllc 0x0040
155#define clk_plld 0x0060
156#define clk_primad 0x0080
157#define clk_primbd 0x00a0
158#define clk_opbd 0x00c0
159#define clk_perd 0x00e0
160#define clk_mald 0x0100
Wolfgang Denk70df7bc2007-06-22 23:59:00 +0200[diff] [blame]161#define clk_spcid 0x0120
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]162#define clk_icfg 0x0140
163
164/* 440gx sdr register definations */
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]165#define sdr_sdstp0 0x0020 /* */
166#define sdr_sdstp1 0x0021 /* */
Stefan Roese3a75ac12007-04-18 12:05:59 +0200[diff] [blame]167#define SDR_PINSTP 0x0040
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]168#define sdr_sdcs 0x0060
169#define sdr_ecid0 0x0080
170#define sdr_ecid1 0x0081
171#define sdr_ecid2 0x0082
172#define sdr_jtag 0x00c0
Stefan Roese42fbddd2006-09-07 11:51:23 +0200[diff] [blame]173#if !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]174#define sdr_ddrdl 0x00e0
Stefan Roese42fbddd2006-09-07 11:51:23 +0200[diff] [blame]175#else
176#define sdr_cfg 0x00e0
177#define SDR_CFG_LT2_MASK 0x01000000 /* Leakage test 2*/
178#define SDR_CFG_64_32BITS_MASK 0x01000000 /* Switch DDR 64 bits or 32 bits */
179#define SDR_CFG_32BITS 0x00000000 /* 32 bits */
180#define SDR_CFG_64BITS 0x01000000 /* 64 bits */
181#define SDR_CFG_MC_V2518_MASK 0x02000000 /* Low VDD2518 (2.5 or 1.8V) */
182#define SDR_CFG_MC_V25 0x00000000 /* 2.5 V */
183#define SDR_CFG_MC_V18 0x02000000 /* 1.8 V */
184#endif /* !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) */
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]185#define sdr_ebc 0x0100
186#define sdr_uart0 0x0120 /* UART0 Config */
187#define sdr_uart1 0x0121 /* UART1 Config */
Stefan Roese326c9712005-08-01 16:41:48 +0200[diff] [blame]188#define sdr_uart2 0x0122 /* UART2 Config */
189#define sdr_uart3 0x0123 /* UART3 Config */
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]190#define sdr_cp440 0x0180
191#define sdr_xcr 0x01c0
192#define sdr_xpllc 0x01c1
193#define sdr_xplld 0x01c2
194#define sdr_srst 0x0200
195#define sdr_slpipe 0x0220
Stefan Roese326c9712005-08-01 16:41:48 +0200[diff] [blame]196#define sdr_amp0 0x0240 /* Override PLB4 prioritiy for up to 8 masters */
197#define sdr_amp1 0x0241 /* Override PLB3 prioritiy for up to 8 masters */
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]198#define sdr_mirq0 0x0260
199#define sdr_mirq1 0x0261
200#define sdr_maltbl 0x0280
201#define sdr_malrbl 0x02a0
202#define sdr_maltbs 0x02c0
203#define sdr_malrbs 0x02e0
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]204#define sdr_pci0 0x0300
205#define sdr_usb0 0x0320
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]206#define sdr_cust0 0x4000
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]207#define sdr_cust1 0x4002
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]208#define sdr_pfc0 0x4100 /* Pin Function 0 */
209#define sdr_pfc1 0x4101 /* Pin Function 1 */
210#define sdr_plbtr 0x4200
211#define sdr_mfr 0x4300 /* SDR0_MFR reg */
212
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]213/*-----------------------------------------------------------------------------
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]214 | SDRAM Controller
215 +----------------------------------------------------------------------------*/
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]216/* values for memcfga register - indirect addressing of these regs */
217#define mem_besr0_clr 0x0000 /* bus error status reg 0 (clr) */
218#define mem_besr0_set 0x0004 /* bus error status reg 0 (set) */
219#define mem_besr1_clr 0x0008 /* bus error status reg 1 (clr) */
220#define mem_besr1_set 0x000c /* bus error status reg 1 (set) */
221#define mem_bear 0x0010 /* bus error address reg */
222#define mem_mirq_clr 0x0011 /* bus master interrupt (clr) */
223#define mem_mirq_set 0x0012 /* bus master interrupt (set) */
224#define mem_slio 0x0018 /* ddr sdram slave interface options */
225#define mem_cfg0 0x0020 /* ddr sdram options 0 */
226#define mem_cfg1 0x0021 /* ddr sdram options 1 */
227#define mem_devopt 0x0022 /* ddr sdram device options */
228#define mem_mcsts 0x0024 /* memory controller status */
229#define mem_rtr 0x0030 /* refresh timer register */
230#define mem_pmit 0x0034 /* power management idle timer */
231#define mem_uabba 0x0038 /* plb UABus base address */
232#define mem_b0cr 0x0040 /* ddr sdram bank 0 configuration */
233#define mem_b1cr 0x0044 /* ddr sdram bank 1 configuration */
234#define mem_b2cr 0x0048 /* ddr sdram bank 2 configuration */
235#define mem_b3cr 0x004c /* ddr sdram bank 3 configuration */
236#define mem_tr0 0x0080 /* sdram timing register 0 */
237#define mem_tr1 0x0081 /* sdram timing register 1 */
238#define mem_clktr 0x0082 /* ddr clock timing register */
239#define mem_wddctr 0x0083 /* write data/dm/dqs clock timing reg */
240#define mem_dlycal 0x0084 /* delay line calibration register */
241#define mem_eccesr 0x0098 /* ECC error status */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]242
Marian Balakowicz6900eeb2006-06-30 18:35:04 +0200[diff] [blame]243#ifdef CONFIG_440GX
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]244#define sdr_amp 0x0240
245#define sdr_xpllc 0x01c1
246#define sdr_xplld 0x01c2
247#define sdr_xcr 0x01c0
248#define sdr_sdstp2 0x4001
249#define sdr_sdstp3 0x4003
Marian Balakowicz6900eeb2006-06-30 18:35:04 +0200[diff] [blame]250#endif /* CONFIG_440GX */
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]251
Igor Lisitsin95bcd382007-03-28 19:06:19 +0400[diff] [blame]252/*----------------------------------------------------------------------------+
253| Core Configuration/MMU configuration for 440 (CCR1 for 440x5 only).
254+----------------------------------------------------------------------------*/
255#define CCR0_PRE 0x40000000
256#define CCR0_CRPE 0x08000000
257#define CCR0_DSTG 0x00200000
258#define CCR0_DAPUIB 0x00100000
259#define CCR0_DTB 0x00008000
260#define CCR0_GICBT 0x00004000
261#define CCR0_GDCBT 0x00002000
262#define CCR0_FLSTA 0x00000100
263#define CCR0_ICSLC_MASK 0x0000000C
264#define CCR0_ICSLT_MASK 0x00000003
265#define CCR1_TCS_MASK 0x00000080
266#define CCR1_TCS_INTCLK 0x00000000
267#define CCR1_TCS_EXTCLK 0x00000080
268#define MMUCR_SWOA 0x01000000
269#define MMUCR_U1TE 0x00400000
270#define MMUCR_U2SWOAE 0x00200000
271#define MMUCR_DULXE 0x00800000
272#define MMUCR_IULXE 0x00400000
273#define MMUCR_STS 0x00100000
274#define MMUCR_STID_MASK 0x000000FF
Igor Lisitsin95bcd382007-03-28 19:06:19 +0400[diff] [blame]275
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]276#ifdef CONFIG_440SPE
277#undef sdr_sdstp2
278#define sdr_sdstp2 0x0022
279#undef sdr_sdstp3
280#define sdr_sdstp3 0x0023
281#define sdr_ddr0 0x00E1
282#define sdr_uart2 0x0122
283#define sdr_xcr0 0x01c0
284/* #define sdr_xcr1 0x01c3 only one PCIX - SG */
285/* #define sdr_xcr2 0x01c6 only one PCIX - SG */
286#define sdr_xpllc0 0x01c1
287#define sdr_xplld0 0x01c2
288#define sdr_xpllc1 0x01c4 /*notRCW - SG */
289#define sdr_xplld1 0x01c5 /*notRCW - SG */
290#define sdr_xpllc2 0x01c7 /*notRCW - SG */
291#define sdr_xplld2 0x01c8 /*notRCW - SG */
292#define sdr_amp0 0x0240
293#define sdr_amp1 0x0241
294#define sdr_cust2 0x4004
295#define sdr_cust3 0x4006
296#define sdr_sdstp4 0x4001
297#define sdr_sdstp5 0x4003
298#define sdr_sdstp6 0x4005
299#define sdr_sdstp7 0x4007
300
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]301/******************************************************************************
302 * PCI express defines
303 ******************************************************************************/
304#define SDR0_PE0UTLSET1 0x00000300 /* PE0 Upper transaction layer conf setting */
305#define SDR0_PE0UTLSET2 0x00000301 /* PE0 Upper transaction layer conf setting 2 */
306#define SDR0_PE0DLPSET 0x00000302 /* PE0 Data link & logical physical configuration */
307#define SDR0_PE0LOOP 0x00000303 /* PE0 Loopback interface status */
308#define SDR0_PE0RCSSET 0x00000304 /* PE0 Reset, clock & shutdown setting */
309#define SDR0_PE0RCSSTS 0x00000305 /* PE0 Reset, clock & shutdown status */
310#define SDR0_PE0HSSSET1L0 0x00000306 /* PE0 HSS Control Setting 1: Lane 0 */
311#define SDR0_PE0HSSSET2L0 0x00000307 /* PE0 HSS Control Setting 2: Lane 0 */
312#define SDR0_PE0HSSSTSL0 0x00000308 /* PE0 HSS Control Status : Lane 0 */
313#define SDR0_PE0HSSSET1L1 0x00000309 /* PE0 HSS Control Setting 1: Lane 1 */
314#define SDR0_PE0HSSSET2L1 0x0000030A /* PE0 HSS Control Setting 2: Lane 1 */
315#define SDR0_PE0HSSSTSL1 0x0000030B /* PE0 HSS Control Status : Lane 1 */
316#define SDR0_PE0HSSSET1L2 0x0000030C /* PE0 HSS Control Setting 1: Lane 2 */
317#define SDR0_PE0HSSSET2L2 0x0000030D /* PE0 HSS Control Setting 2: Lane 2 */
318#define SDR0_PE0HSSSTSL2 0x0000030E /* PE0 HSS Control Status : Lane 2 */
319#define SDR0_PE0HSSSET1L3 0x0000030F /* PE0 HSS Control Setting 1: Lane 3 */
320#define SDR0_PE0HSSSET2L3 0x00000310 /* PE0 HSS Control Setting 2: Lane 3 */
321#define SDR0_PE0HSSSTSL3 0x00000311 /* PE0 HSS Control Status : Lane 3 */
322#define SDR0_PE0HSSSET1L4 0x00000312 /* PE0 HSS Control Setting 1: Lane 4 */
323#define SDR0_PE0HSSSET2L4 0x00000313 /* PE0 HSS Control Setting 2: Lane 4 */
324#define SDR0_PE0HSSSTSL4 0x00000314 /* PE0 HSS Control Status : Lane 4 */
325#define SDR0_PE0HSSSET1L5 0x00000315 /* PE0 HSS Control Setting 1: Lane 5 */
326#define SDR0_PE0HSSSET2L5 0x00000316 /* PE0 HSS Control Setting 2: Lane 5 */
327#define SDR0_PE0HSSSTSL5 0x00000317 /* PE0 HSS Control Status : Lane 5 */
328#define SDR0_PE0HSSSET1L6 0x00000318 /* PE0 HSS Control Setting 1: Lane 6 */
329#define SDR0_PE0HSSSET2L6 0x00000319 /* PE0 HSS Control Setting 2: Lane 6 */
330#define SDR0_PE0HSSSTSL6 0x0000031A /* PE0 HSS Control Status : Lane 6 */
331#define SDR0_PE0HSSSET1L7 0x0000031B /* PE0 HSS Control Setting 1: Lane 7 */
332#define SDR0_PE0HSSSET2L7 0x0000031C /* PE0 HSS Control Setting 2: Lane 7 */
333#define SDR0_PE0HSSSTSL7 0x0000031D /* PE0 HSS Control Status : Lane 7 */
334#define SDR0_PE0HSSSEREN 0x0000031E /* PE0 Serdes Transmitter Enable */
335#define SDR0_PE0LANEABCD 0x0000031F /* PE0 Lanes ABCD affectation */
336#define SDR0_PE0LANEEFGH 0x00000320 /* PE0 Lanes EFGH affectation */
337
338#define SDR0_PE1UTLSET1 0x00000340 /* PE1 Upper transaction layer conf setting */
339#define SDR0_PE1UTLSET2 0x00000341 /* PE1 Upper transaction layer conf setting 2 */
340#define SDR0_PE1DLPSET 0x00000342 /* PE1 Data link & logical physical configuration */
341#define SDR0_PE1LOOP 0x00000343 /* PE1 Loopback interface status */
342#define SDR0_PE1RCSSET 0x00000344 /* PE1 Reset, clock & shutdown setting */
343#define SDR0_PE1RCSSTS 0x00000345 /* PE1 Reset, clock & shutdown status */
344#define SDR0_PE1HSSSET1L0 0x00000346 /* PE1 HSS Control Setting 1: Lane 0 */
345#define SDR0_PE1HSSSET2L0 0x00000347 /* PE1 HSS Control Setting 2: Lane 0 */
346#define SDR0_PE1HSSSTSL0 0x00000348 /* PE1 HSS Control Status : Lane 0 */
347#define SDR0_PE1HSSSET1L1 0x00000349 /* PE1 HSS Control Setting 1: Lane 1 */
348#define SDR0_PE1HSSSET2L1 0x0000034A /* PE1 HSS Control Setting 2: Lane 1 */
349#define SDR0_PE1HSSSTSL1 0x0000034B /* PE1 HSS Control Status : Lane 1 */
350#define SDR0_PE1HSSSET1L2 0x0000034C /* PE1 HSS Control Setting 1: Lane 2 */
351#define SDR0_PE1HSSSET2L2 0x0000034D /* PE1 HSS Control Setting 2: Lane 2 */
352#define SDR0_PE1HSSSTSL2 0x0000034E /* PE1 HSS Control Status : Lane 2 */
353#define SDR0_PE1HSSSET1L3 0x0000034F /* PE1 HSS Control Setting 1: Lane 3 */
354#define SDR0_PE1HSSSET2L3 0x00000350 /* PE1 HSS Control Setting 2: Lane 3 */
355#define SDR0_PE1HSSSTSL3 0x00000351 /* PE1 HSS Control Status : Lane 3 */
356#define SDR0_PE1HSSSEREN 0x00000352 /* PE1 Serdes Transmitter Enable */
357#define SDR0_PE1LANEABCD 0x00000353 /* PE1 Lanes ABCD affectation */
358#define SDR0_PE2UTLSET1 0x00000370 /* PE2 Upper transaction layer conf setting */
359#define SDR0_PE2UTLSET2 0x00000371 /* PE2 Upper transaction layer conf setting 2 */
360#define SDR0_PE2DLPSET 0x00000372 /* PE2 Data link & logical physical configuration */
361#define SDR0_PE2LOOP 0x00000373 /* PE2 Loopback interface status */
362#define SDR0_PE2RCSSET 0x00000374 /* PE2 Reset, clock & shutdown setting */
363#define SDR0_PE2RCSSTS 0x00000375 /* PE2 Reset, clock & shutdown status */
364#define SDR0_PE2HSSSET1L0 0x00000376 /* PE2 HSS Control Setting 1: Lane 0 */
365#define SDR0_PE2HSSSET2L0 0x00000377 /* PE2 HSS Control Setting 2: Lane 0 */
366#define SDR0_PE2HSSSTSL0 0x00000378 /* PE2 HSS Control Status : Lane 0 */
367#define SDR0_PE2HSSSET1L1 0x00000379 /* PE2 HSS Control Setting 1: Lane 1 */
368#define SDR0_PE2HSSSET2L1 0x0000037A /* PE2 HSS Control Setting 2: Lane 1 */
369#define SDR0_PE2HSSSTSL1 0x0000037B /* PE2 HSS Control Status : Lane 1 */
370#define SDR0_PE2HSSSET1L2 0x0000037C /* PE2 HSS Control Setting 1: Lane 2 */
371#define SDR0_PE2HSSSET2L2 0x0000037D /* PE2 HSS Control Setting 2: Lane 2 */
372#define SDR0_PE2HSSSTSL2 0x0000037E /* PE2 HSS Control Status : Lane 2 */
373#define SDR0_PE2HSSSET1L3 0x0000037F /* PE2 HSS Control Setting 1: Lane 3 */
374#define SDR0_PE2HSSSET2L3 0x00000380 /* PE2 HSS Control Setting 2: Lane 3 */
375#define SDR0_PE2HSSSTSL3 0x00000381 /* PE2 HSS Control Status : Lane 3 */
376#define SDR0_PE2HSSSEREN 0x00000382 /* PE2 Serdes Transmitter Enable */
377#define SDR0_PE2LANEABCD 0x00000383 /* PE2 Lanes ABCD affectation */
378#define SDR0_PEGPLLSET1 0x000003A0 /* PE Pll LC Tank Setting1 */
379#define SDR0_PEGPLLSET2 0x000003A1 /* PE Pll LC Tank Setting2 */
380#define SDR0_PEGPLLSTS 0x000003A2 /* PE Pll LC Tank Status */
Stefan Roeseb39ef632007-03-08 10:06:09 +0100[diff] [blame]381#endif /* CONFIG_440SPE */
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]382
Stefan Roeseb39ef632007-03-08 10:06:09 +0100[diff] [blame]383#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]384/*----------------------------------------------------------------------------+
385| SDRAM Controller
386+----------------------------------------------------------------------------*/
387/*-----------------------------------------------------------------------------+
388| SDRAM DLYCAL Options
389+-----------------------------------------------------------------------------*/
390#define SDRAM_DLYCAL_DLCV_MASK 0x000003FC
391#define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
392#define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
393
394/*----------------------------------------------------------------------------+
395| Memory queue defines
396+----------------------------------------------------------------------------*/
397/* A REVOIR versus RWC - SG*/
398#define SDRAMQ_DCR_BASE 0x040
399
400#define SDRAM_R0BAS (SDRAMQ_DCR_BASE+0x0) /* rank 0 base address & size */
401#define SDRAM_R1BAS (SDRAMQ_DCR_BASE+0x1) /* rank 1 base address & size */
402#define SDRAM_R2BAS (SDRAMQ_DCR_BASE+0x2) /* rank 2 base address & size */
403#define SDRAM_R3BAS (SDRAMQ_DCR_BASE+0x3) /* rank 3 base address & size */
404#define SDRAM_CONF1HB (SDRAMQ_DCR_BASE+0x5) /* configuration 1 HB */
405#define SDRAM_ERRSTATHB (SDRAMQ_DCR_BASE+0x7) /* error status HB */
406#define SDRAM_ERRADDUHB (SDRAMQ_DCR_BASE+0x8) /* error address upper 32 HB */
407#define SDRAM_ERRADDLHB (SDRAMQ_DCR_BASE+0x9) /* error address lower 32 HB */
408#define SDRAM_PLBADDULL (SDRAMQ_DCR_BASE+0xA) /* PLB base address upper 32 LL */
409#define SDRAM_CONF1LL (SDRAMQ_DCR_BASE+0xB) /* configuration 1 LL */
410#define SDRAM_ERRSTATLL (SDRAMQ_DCR_BASE+0xC) /* error status LL */
411#define SDRAM_ERRADDULL (SDRAMQ_DCR_BASE+0xD) /* error address upper 32 LL */
412#define SDRAM_ERRADDLLL (SDRAMQ_DCR_BASE+0xE) /* error address lower 32 LL */
413#define SDRAM_CONFPATHB (SDRAMQ_DCR_BASE+0xF) /* configuration between paths */
414#define SDRAM_PLBADDUHB (SDRAMQ_DCR_BASE+0x10) /* PLB base address upper 32 LL */
415
416/*-----------------------------------------------------------------------------+
417| Memory Bank 0-7 configuration
418+-----------------------------------------------------------------------------*/
Stefan Roeseb39ef632007-03-08 10:06:09 +0100[diff] [blame]419#if defined(CONFIG_440SPE)
420#define SDRAM_RXBAS_SDBA_MASK 0xFFE00000 /* Base address */
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]421#define SDRAM_RXBAS_SDBA_ENCODE(n) ((((unsigned long)(n))&0xFFE00000)>>2)
422#define SDRAM_RXBAS_SDBA_DECODE(n) ((((unsigned long)(n))&0xFFE00000)<<2)
Stefan Roeseb39ef632007-03-08 10:06:09 +0100[diff] [blame]423#endif /* CONFIG_440SPE */
424#if defined(CONFIG_440SP)
425#define SDRAM_RXBAS_SDBA_MASK 0xFF800000 /* Base address */
426#define SDRAM_RXBAS_SDBA_ENCODE(n) ((((unsigned long)(n))&0xFF800000))
427#define SDRAM_RXBAS_SDBA_DECODE(n) ((((unsigned long)(n))&0xFF800000))
428#endif /* CONFIG_440SP */
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]429#define SDRAM_RXBAS_SDSZ_MASK 0x0000FFC0 /* Size */
430#define SDRAM_RXBAS_SDSZ_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<6)
431#define SDRAM_RXBAS_SDSZ_DECODE(n) ((((unsigned long)(n))>>6)&0x3FF)
432#define SDRAM_RXBAS_SDSZ_0 0x00000000 /* 0M */
433#define SDRAM_RXBAS_SDSZ_8 0x0000FFC0 /* 8M */
434#define SDRAM_RXBAS_SDSZ_16 0x0000FF80 /* 16M */
435#define SDRAM_RXBAS_SDSZ_32 0x0000FF00 /* 32M */
436#define SDRAM_RXBAS_SDSZ_64 0x0000FE00 /* 64M */
437#define SDRAM_RXBAS_SDSZ_128 0x0000FC00 /* 128M */
438#define SDRAM_RXBAS_SDSZ_256 0x0000F800 /* 256M */
439#define SDRAM_RXBAS_SDSZ_512 0x0000F000 /* 512M */
440#define SDRAM_RXBAS_SDSZ_1024 0x0000E000 /* 1024M */
441#define SDRAM_RXBAS_SDSZ_2048 0x0000C000 /* 2048M */
442#define SDRAM_RXBAS_SDSZ_4096 0x00008000 /* 4096M */
443
444/*----------------------------------------------------------------------------+
445| Memory controller defines
446+----------------------------------------------------------------------------*/
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]447/* A REVOIR versus specs 4 bank - SG*/
448#define SDRAM_MCSTAT 0x14 /* memory controller status */
449#define SDRAM_MCOPT1 0x20 /* memory controller options 1 */
450#define SDRAM_MCOPT2 0x21 /* memory controller options 2 */
451#define SDRAM_MODT0 0x22 /* on die termination for bank 0 */
452#define SDRAM_MODT1 0x23 /* on die termination for bank 1 */
453#define SDRAM_MODT2 0x24 /* on die termination for bank 2 */
454#define SDRAM_MODT3 0x25 /* on die termination for bank 3 */
455#define SDRAM_CODT 0x26 /* on die termination for controller */
456#define SDRAM_VVPR 0x27 /* variable VRef programmming */
457#define SDRAM_OPARS 0x28 /* on chip driver control setup */
458#define SDRAM_OPART 0x29 /* on chip driver control trigger */
459#define SDRAM_RTR 0x30 /* refresh timer */
460#define SDRAM_PMIT 0x34 /* power management idle timer */
461#define SDRAM_MB0CF 0x40 /* memory bank 0 configuration */
462#define SDRAM_MB1CF 0x44 /* memory bank 1 configuration */
463#define SDRAM_MB2CF 0x48
464#define SDRAM_MB3CF 0x4C
465#define SDRAM_INITPLR0 0x50 /* manual initialization control */
466#define SDRAM_INITPLR1 0x51 /* manual initialization control */
467#define SDRAM_INITPLR2 0x52 /* manual initialization control */
468#define SDRAM_INITPLR3 0x53 /* manual initialization control */
469#define SDRAM_INITPLR4 0x54 /* manual initialization control */
470#define SDRAM_INITPLR5 0x55 /* manual initialization control */
471#define SDRAM_INITPLR6 0x56 /* manual initialization control */
472#define SDRAM_INITPLR7 0x57 /* manual initialization control */
473#define SDRAM_INITPLR8 0x58 /* manual initialization control */
474#define SDRAM_INITPLR9 0x59 /* manual initialization control */
475#define SDRAM_INITPLR10 0x5a /* manual initialization control */
476#define SDRAM_INITPLR11 0x5b /* manual initialization control */
477#define SDRAM_INITPLR12 0x5c /* manual initialization control */
478#define SDRAM_INITPLR13 0x5d /* manual initialization control */
479#define SDRAM_INITPLR14 0x5e /* manual initialization control */
480#define SDRAM_INITPLR15 0x5f /* manual initialization control */
481#define SDRAM_RQDC 0x70 /* read DQS delay control */
482#define SDRAM_RFDC 0x74 /* read feedback delay control */
483#define SDRAM_RDCC 0x78 /* read data capture control */
484#define SDRAM_DLCR 0x7A /* delay line calibration */
485#define SDRAM_CLKTR 0x80 /* DDR clock timing */
486#define SDRAM_WRDTR 0x81 /* write data, DQS, DM clock, timing */
487#define SDRAM_SDTR1 0x85 /* DDR SDRAM timing 1 */
488#define SDRAM_SDTR2 0x86 /* DDR SDRAM timing 2 */
489#define SDRAM_SDTR3 0x87 /* DDR SDRAM timing 3 */
490#define SDRAM_MMODE 0x88 /* memory mode */
491#define SDRAM_MEMODE 0x89 /* memory extended mode */
492#define SDRAM_ECCCR 0x98 /* ECC error status */
493#define SDRAM_CID 0xA4 /* core ID */
494#define SDRAM_RID 0xA8 /* revision ID */
Stefan Roesee3060b02008-01-05 09:12:41 +0100[diff] [blame]495#define SDRAM_RTSR 0xB1 /* run time status tracking */
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]496
497/*-----------------------------------------------------------------------------+
498| Memory Controller Status
499+-----------------------------------------------------------------------------*/
500#define SDRAM_MCSTAT_MIC_MASK 0x80000000 /* Memory init status mask */
501#define SDRAM_MCSTAT_MIC_NOTCOMP 0x00000000 /* Mem init not complete */
502#define SDRAM_MCSTAT_MIC_COMP 0x80000000 /* Mem init complete */
Stefan Roesea8856e32007-02-20 10:57:08 +0100[diff] [blame]503#define SDRAM_MCSTAT_SRMS_MASK 0x40000000 /* Mem self refresh stat mask */
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]504#define SDRAM_MCSTAT_SRMS_NOT_SF 0x00000000 /* Mem not in self refresh */
Stefan Roesea8856e32007-02-20 10:57:08 +0100[diff] [blame]505#define SDRAM_MCSTAT_SRMS_SF 0x40000000 /* Mem in self refresh */
506#define SDRAM_MCSTAT_IDLE_MASK 0x20000000 /* Mem self refresh stat mask */
507#define SDRAM_MCSTAT_IDLE_NOT 0x00000000 /* Mem contr not idle */
508#define SDRAM_MCSTAT_IDLE 0x20000000 /* Mem contr idle */
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]509
510/*-----------------------------------------------------------------------------+
511| Memory Controller Options 1
512+-----------------------------------------------------------------------------*/
513#define SDRAM_MCOPT1_MCHK_MASK 0x30000000 /* Memory data err check mask*/
514#define SDRAM_MCOPT1_MCHK_NON 0x00000000 /* No ECC generation */
515#define SDRAM_MCOPT1_MCHK_GEN 0x20000000 /* ECC generation */
516#define SDRAM_MCOPT1_MCHK_CHK 0x10000000 /* ECC generation and check */
517#define SDRAM_MCOPT1_MCHK_CHK_REP 0x30000000 /* ECC generation, chk, report*/
518#define SDRAM_MCOPT1_MCHK_CHK_DECODE(n) ((((unsigned long)(n))>>28)&0x3)
519#define SDRAM_MCOPT1_RDEN_MASK 0x08000000 /* Registered DIMM mask */
520#define SDRAM_MCOPT1_RDEN 0x08000000 /* Registered DIMM enable */
521#define SDRAM_MCOPT1_PMU_MASK 0x06000000 /* Page management unit mask */
522#define SDRAM_MCOPT1_PMU_CLOSE 0x00000000 /* PMU Close */
523#define SDRAM_MCOPT1_PMU_OPEN 0x04000000 /* PMU Open */
524#define SDRAM_MCOPT1_PMU_AUTOCLOSE 0x02000000 /* PMU AutoClose */
525#define SDRAM_MCOPT1_DMWD_MASK 0x01000000 /* DRAM width mask */
526#define SDRAM_MCOPT1_DMWD_32 0x00000000 /* 32 bits */
527#define SDRAM_MCOPT1_DMWD_64 0x01000000 /* 64 bits */
528#define SDRAM_MCOPT1_UIOS_MASK 0x00C00000 /* Unused IO State */
529#define SDRAM_MCOPT1_BCNT_MASK 0x00200000 /* Bank count */
530#define SDRAM_MCOPT1_4_BANKS 0x00000000 /* 4 Banks */
531#define SDRAM_MCOPT1_8_BANKS 0x00200000 /* 8 Banks */
532#define SDRAM_MCOPT1_DDR_TYPE_MASK 0x00100000 /* DDR Memory Type mask */
533#define SDRAM_MCOPT1_DDR1_TYPE 0x00000000 /* DDR1 Memory Type */
534#define SDRAM_MCOPT1_DDR2_TYPE 0x00100000 /* DDR2 Memory Type */
535#define SDRAM_MCOPT1_QDEP 0x00020000 /* 4 commands deep */
536#define SDRAM_MCOPT1_RWOO_MASK 0x00008000 /* Out of Order Read mask */
537#define SDRAM_MCOPT1_RWOO_DISABLED 0x00000000 /* disabled */
538#define SDRAM_MCOPT1_RWOO_ENABLED 0x00008000 /* enabled */
539#define SDRAM_MCOPT1_WOOO_MASK 0x00004000 /* Out of Order Write mask */
540#define SDRAM_MCOPT1_WOOO_DISABLED 0x00000000 /* disabled */
541#define SDRAM_MCOPT1_WOOO_ENABLED 0x00004000 /* enabled */
542#define SDRAM_MCOPT1_DCOO_MASK 0x00002000 /* All Out of Order mask */
543#define SDRAM_MCOPT1_DCOO_DISABLED 0x00002000 /* disabled */
544#define SDRAM_MCOPT1_DCOO_ENABLED 0x00000000 /* enabled */
545#define SDRAM_MCOPT1_DREF_MASK 0x00001000 /* Deferred refresh mask */
546#define SDRAM_MCOPT1_DREF_NORMAL 0x00000000 /* normal refresh */
547#define SDRAM_MCOPT1_DREF_DEFER_4 0x00001000 /* defer up to 4 refresh cmd */
548
549/*-----------------------------------------------------------------------------+
550| Memory Controller Options 2
551+-----------------------------------------------------------------------------*/
552#define SDRAM_MCOPT2_SREN_MASK 0x80000000 /* Self Test mask */
553#define SDRAM_MCOPT2_SREN_EXIT 0x00000000 /* Self Test exit */
554#define SDRAM_MCOPT2_SREN_ENTER 0x80000000 /* Self Test enter */
555#define SDRAM_MCOPT2_PMEN_MASK 0x40000000 /* Power Management mask */
556#define SDRAM_MCOPT2_PMEN_DISABLE 0x00000000 /* disable */
557#define SDRAM_MCOPT2_PMEN_ENABLE 0x40000000 /* enable */
558#define SDRAM_MCOPT2_IPTR_MASK 0x20000000 /* Init Trigger Reg mask */
559#define SDRAM_MCOPT2_IPTR_IDLE 0x00000000 /* idle */
560#define SDRAM_MCOPT2_IPTR_EXECUTE 0x20000000 /* execute preloaded init */
561#define SDRAM_MCOPT2_XSRP_MASK 0x10000000 /* Exit Self Refresh Prevent */
562#define SDRAM_MCOPT2_XSRP_ALLOW 0x00000000 /* allow self refresh exit */
563#define SDRAM_MCOPT2_XSRP_PREVENT 0x10000000 /* prevent self refresh exit */
564#define SDRAM_MCOPT2_DCEN_MASK 0x08000000 /* SDRAM Controller Enable */
565#define SDRAM_MCOPT2_DCEN_DISABLE 0x00000000 /* SDRAM Controller Enable */
566#define SDRAM_MCOPT2_DCEN_ENABLE 0x08000000 /* SDRAM Controller Enable */
567#define SDRAM_MCOPT2_ISIE_MASK 0x04000000 /* Init Seq Interruptable mas*/
568#define SDRAM_MCOPT2_ISIE_DISABLE 0x00000000 /* disable */
569#define SDRAM_MCOPT2_ISIE_ENABLE 0x04000000 /* enable */
570
571/*-----------------------------------------------------------------------------+
572| SDRAM Refresh Timer Register
573+-----------------------------------------------------------------------------*/
574#define SDRAM_RTR_RINT_MASK 0xFFF80000
575#define SDRAM_RTR_RINT_ENCODE(n) ((((unsigned long)(n))&0xFFF8)<<16)
576#define SDRAM_RTR_RINT_DECODE(n) ((((unsigned long)(n))>>16)&0xFFF8)
577
578/*-----------------------------------------------------------------------------+
579| SDRAM Read DQS Delay Control Register
580+-----------------------------------------------------------------------------*/
581#define SDRAM_RQDC_RQDE_MASK 0x80000000
582#define SDRAM_RQDC_RQDE_DISABLE 0x00000000
583#define SDRAM_RQDC_RQDE_ENABLE 0x80000000
584#define SDRAM_RQDC_RQFD_MASK 0x000001FF
585#define SDRAM_RQDC_RQFD_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0)
586
587#define SDRAM_RQDC_RQFD_MAX 0x1FF
588
589/*-----------------------------------------------------------------------------+
590| SDRAM Read Data Capture Control Register
591+-----------------------------------------------------------------------------*/
592#define SDRAM_RDCC_RDSS_MASK 0xC0000000
593#define SDRAM_RDCC_RDSS_T1 0x00000000
594#define SDRAM_RDCC_RDSS_T2 0x40000000
595#define SDRAM_RDCC_RDSS_T3 0x80000000
596#define SDRAM_RDCC_RDSS_T4 0xC0000000
597#define SDRAM_RDCC_RSAE_MASK 0x00000001
598#define SDRAM_RDCC_RSAE_DISABLE 0x00000001
599#define SDRAM_RDCC_RSAE_ENABLE 0x00000000
600
601/*-----------------------------------------------------------------------------+
602| SDRAM Read Feedback Delay Control Register
603+-----------------------------------------------------------------------------*/
604#define SDRAM_RFDC_ARSE_MASK 0x80000000
605#define SDRAM_RFDC_ARSE_DISABLE 0x80000000
606#define SDRAM_RFDC_ARSE_ENABLE 0x00000000
607#define SDRAM_RFDC_RFOS_MASK 0x007F0000
608#define SDRAM_RFDC_RFOS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
Stefan Roesee3060b02008-01-05 09:12:41 +0100[diff] [blame]609#define SDRAM_RFDC_RFFD_MASK 0x000007FF
610#define SDRAM_RFDC_RFFD_ENCODE(n) ((((unsigned long)(n))&0x7FF)<<0)
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]611
612#define SDRAM_RFDC_RFFD_MAX 0x7FF
613
614/*-----------------------------------------------------------------------------+
615| SDRAM Delay Line Calibration Register
616+-----------------------------------------------------------------------------*/
617#define SDRAM_DLCR_DCLM_MASK 0x80000000
618#define SDRAM_DLCR_DCLM_MANUEL 0x80000000
619#define SDRAM_DLCR_DCLM_AUTO 0x00000000
620#define SDRAM_DLCR_DLCR_MASK 0x08000000
621#define SDRAM_DLCR_DLCR_CALIBRATE 0x08000000
622#define SDRAM_DLCR_DLCR_IDLE 0x00000000
623#define SDRAM_DLCR_DLCS_MASK 0x07000000
624#define SDRAM_DLCR_DLCS_NOT_RUN 0x00000000
625#define SDRAM_DLCR_DLCS_IN_PROGRESS 0x01000000
626#define SDRAM_DLCR_DLCS_COMPLETE 0x02000000
627#define SDRAM_DLCR_DLCS_CONT_DONE 0x03000000
628#define SDRAM_DLCR_DLCS_ERROR 0x04000000
629#define SDRAM_DLCR_DLCV_MASK 0x000001FF
630#define SDRAM_DLCR_DLCV_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0)
631#define SDRAM_DLCR_DLCV_DECODE(n) ((((unsigned long)(n))>>0)&0x1FF)
632
633/*-----------------------------------------------------------------------------+
634| SDRAM Controller On Die Termination Register
635+-----------------------------------------------------------------------------*/
636#define SDRAM_CODT_ODT_ON 0x80000000
637#define SDRAM_CODT_ODT_OFF 0x00000000
638#define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK 0x00000020
639#define SDRAM_CODT_DQS_2_5_V_DDR1 0x00000000
640#define SDRAM_CODT_DQS_1_8_V_DDR2 0x00000020
641#define SDRAM_CODT_DQS_MASK 0x00000010
642#define SDRAM_CODT_DQS_DIFFERENTIAL 0x00000000
643#define SDRAM_CODT_DQS_SINGLE_END 0x00000010
644#define SDRAM_CODT_CKSE_DIFFERENTIAL 0x00000000
645#define SDRAM_CODT_CKSE_SINGLE_END 0x00000008
646#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END 0x00000004
647#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END 0x00000002
Wolfgang Denk70df7bc2007-06-22 23:59:00 +0200[diff] [blame]648#define SDRAM_CODT_IO_HIZ 0x00000000
649#define SDRAM_CODT_IO_NMODE 0x00000001
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]650
651/*-----------------------------------------------------------------------------+
652| SDRAM Mode Register
653+-----------------------------------------------------------------------------*/
654#define SDRAM_MMODE_WR_MASK 0x00000E00
655#define SDRAM_MMODE_WR_DDR1 0x00000000
656#define SDRAM_MMODE_WR_DDR2_3_CYC 0x00000400
657#define SDRAM_MMODE_WR_DDR2_4_CYC 0x00000600
658#define SDRAM_MMODE_WR_DDR2_5_CYC 0x00000800
659#define SDRAM_MMODE_WR_DDR2_6_CYC 0x00000A00
660#define SDRAM_MMODE_DCL_MASK 0x00000070
661#define SDRAM_MMODE_DCL_DDR1_2_0_CLK 0x00000020
662#define SDRAM_MMODE_DCL_DDR1_2_5_CLK 0x00000060
663#define SDRAM_MMODE_DCL_DDR1_3_0_CLK 0x00000030
664#define SDRAM_MMODE_DCL_DDR2_2_0_CLK 0x00000020
665#define SDRAM_MMODE_DCL_DDR2_3_0_CLK 0x00000030
666#define SDRAM_MMODE_DCL_DDR2_4_0_CLK 0x00000040
667#define SDRAM_MMODE_DCL_DDR2_5_0_CLK 0x00000050
668#define SDRAM_MMODE_DCL_DDR2_6_0_CLK 0x00000060
669#define SDRAM_MMODE_DCL_DDR2_7_0_CLK 0x00000070
670
671/*-----------------------------------------------------------------------------+
672| SDRAM Extended Mode Register
673+-----------------------------------------------------------------------------*/
674#define SDRAM_MEMODE_DIC_MASK 0x00000002
675#define SDRAM_MEMODE_DIC_NORMAL 0x00000000
676#define SDRAM_MEMODE_DIC_WEAK 0x00000002
677#define SDRAM_MEMODE_DLL_MASK 0x00000001
678#define SDRAM_MEMODE_DLL_DISABLE 0x00000001
679#define SDRAM_MEMODE_DLL_ENABLE 0x00000000
680#define SDRAM_MEMODE_RTT_MASK 0x00000044
681#define SDRAM_MEMODE_RTT_DISABLED 0x00000000
682#define SDRAM_MEMODE_RTT_75OHM 0x00000004
683#define SDRAM_MEMODE_RTT_150OHM 0x00000040
684#define SDRAM_MEMODE_DQS_MASK 0x00000400
685#define SDRAM_MEMODE_DQS_DISABLE 0x00000400
686#define SDRAM_MEMODE_DQS_ENABLE 0x00000000
687
688/*-----------------------------------------------------------------------------+
689| SDRAM Clock Timing Register
690+-----------------------------------------------------------------------------*/
691#define SDRAM_CLKTR_CLKP_MASK 0xC0000000
692#define SDRAM_CLKTR_CLKP_0_DEG 0x00000000
693#define SDRAM_CLKTR_CLKP_180_DEG_ADV 0x80000000
Stefan Roesee3060b02008-01-05 09:12:41 +0100[diff] [blame]694#define SDRAM_CLKTR_CLKP_90_DEG_ADV 0x40000000
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]695
696/*-----------------------------------------------------------------------------+
697| SDRAM Write Timing Register
698+-----------------------------------------------------------------------------*/
699#define SDRAM_WRDTR_LLWP_MASK 0x10000000
700#define SDRAM_WRDTR_LLWP_DIS 0x10000000
701#define SDRAM_WRDTR_LLWP_1_CYC 0x00000000
702#define SDRAM_WRDTR_WTR_MASK 0x0E000000
703#define SDRAM_WRDTR_WTR_0_DEG 0x06000000
Stefan Roesea8856e32007-02-20 10:57:08 +0100[diff] [blame]704#define SDRAM_WRDTR_WTR_90_DEG_ADV 0x04000000
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]705#define SDRAM_WRDTR_WTR_180_DEG_ADV 0x02000000
706#define SDRAM_WRDTR_WTR_270_DEG_ADV 0x00000000
707
708/*-----------------------------------------------------------------------------+
709| SDRAM SDTR1 Options
710+-----------------------------------------------------------------------------*/
711#define SDRAM_SDTR1_LDOF_MASK 0x80000000
712#define SDRAM_SDTR1_LDOF_1_CLK 0x00000000
713#define SDRAM_SDTR1_LDOF_2_CLK 0x80000000
714#define SDRAM_SDTR1_RTW_MASK 0x00F00000
715#define SDRAM_SDTR1_RTW_2_CLK 0x00200000
716#define SDRAM_SDTR1_RTW_3_CLK 0x00300000
717#define SDRAM_SDTR1_WTWO_MASK 0x000F0000
718#define SDRAM_SDTR1_WTWO_0_CLK 0x00000000
719#define SDRAM_SDTR1_WTWO_1_CLK 0x00010000
720#define SDRAM_SDTR1_RTRO_MASK 0x0000F000
721#define SDRAM_SDTR1_RTRO_1_CLK 0x00001000
722#define SDRAM_SDTR1_RTRO_2_CLK 0x00002000
723
724/*-----------------------------------------------------------------------------+
725| SDRAM SDTR2 Options
726+-----------------------------------------------------------------------------*/
727#define SDRAM_SDTR2_RCD_MASK 0xF0000000
728#define SDRAM_SDTR2_RCD_1_CLK 0x10000000
729#define SDRAM_SDTR2_RCD_2_CLK 0x20000000
730#define SDRAM_SDTR2_RCD_3_CLK 0x30000000
731#define SDRAM_SDTR2_RCD_4_CLK 0x40000000
732#define SDRAM_SDTR2_RCD_5_CLK 0x50000000
733#define SDRAM_SDTR2_WTR_MASK 0x0F000000
734#define SDRAM_SDTR2_WTR_1_CLK 0x01000000
735#define SDRAM_SDTR2_WTR_2_CLK 0x02000000
736#define SDRAM_SDTR2_WTR_3_CLK 0x03000000
737#define SDRAM_SDTR2_WTR_4_CLK 0x04000000
738#define SDRAM_SDTR3_WTR_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
739#define SDRAM_SDTR2_XSNR_MASK 0x00FF0000
740#define SDRAM_SDTR2_XSNR_8_CLK 0x00080000
741#define SDRAM_SDTR2_XSNR_16_CLK 0x00100000
742#define SDRAM_SDTR2_XSNR_32_CLK 0x00200000
743#define SDRAM_SDTR2_XSNR_64_CLK 0x00400000
744#define SDRAM_SDTR2_WPC_MASK 0x0000F000
745#define SDRAM_SDTR2_WPC_2_CLK 0x00002000
746#define SDRAM_SDTR2_WPC_3_CLK 0x00003000
747#define SDRAM_SDTR2_WPC_4_CLK 0x00004000
748#define SDRAM_SDTR2_WPC_5_CLK 0x00005000
749#define SDRAM_SDTR2_WPC_6_CLK 0x00006000
750#define SDRAM_SDTR3_WPC_ENCODE(n) ((((unsigned long)(n))&0xF)<<12)
751#define SDRAM_SDTR2_RPC_MASK 0x00000F00
752#define SDRAM_SDTR2_RPC_2_CLK 0x00000200
753#define SDRAM_SDTR2_RPC_3_CLK 0x00000300
754#define SDRAM_SDTR2_RPC_4_CLK 0x00000400
755#define SDRAM_SDTR2_RP_MASK 0x000000F0
756#define SDRAM_SDTR2_RP_3_CLK 0x00000030
757#define SDRAM_SDTR2_RP_4_CLK 0x00000040
758#define SDRAM_SDTR2_RP_5_CLK 0x00000050
759#define SDRAM_SDTR2_RP_6_CLK 0x00000060
760#define SDRAM_SDTR2_RP_7_CLK 0x00000070
761#define SDRAM_SDTR2_RRD_MASK 0x0000000F
762#define SDRAM_SDTR2_RRD_2_CLK 0x00000002
763#define SDRAM_SDTR2_RRD_3_CLK 0x00000003
764
765/*-----------------------------------------------------------------------------+
766| SDRAM SDTR3 Options
767+-----------------------------------------------------------------------------*/
768#define SDRAM_SDTR3_RAS_MASK 0x1F000000
769#define SDRAM_SDTR3_RAS_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
770#define SDRAM_SDTR3_RC_MASK 0x001F0000
771#define SDRAM_SDTR3_RC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16)
772#define SDRAM_SDTR3_XCS_MASK 0x00001F00
773#define SDRAM_SDTR3_XCS 0x00000D00
774#define SDRAM_SDTR3_RFC_MASK 0x0000003F
775#define SDRAM_SDTR3_RFC_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0)
776
777/*-----------------------------------------------------------------------------+
778| Memory Bank 0-1 configuration
779+-----------------------------------------------------------------------------*/
780#define SDRAM_BXCF_M_AM_MASK 0x00000F00 /* Addressing mode */
781#define SDRAM_BXCF_M_AM_0 0x00000000 /* Mode 0 */
782#define SDRAM_BXCF_M_AM_1 0x00000100 /* Mode 1 */
783#define SDRAM_BXCF_M_AM_2 0x00000200 /* Mode 2 */
784#define SDRAM_BXCF_M_AM_3 0x00000300 /* Mode 3 */
785#define SDRAM_BXCF_M_AM_4 0x00000400 /* Mode 4 */
786#define SDRAM_BXCF_M_AM_5 0x00000500 /* Mode 5 */
787#define SDRAM_BXCF_M_AM_6 0x00000600 /* Mode 6 */
788#define SDRAM_BXCF_M_AM_7 0x00000700 /* Mode 7 */
789#define SDRAM_BXCF_M_AM_8 0x00000800 /* Mode 8 */
790#define SDRAM_BXCF_M_AM_9 0x00000900 /* Mode 9 */
791#define SDRAM_BXCF_M_BE_MASK 0x00000001 /* Memory Bank Enable */
792#define SDRAM_BXCF_M_BE_DISABLE 0x00000000 /* Memory Bank Enable */
793#define SDRAM_BXCF_M_BE_ENABLE 0x00000001 /* Memory Bank Enable */
Stefan Roesef1990632007-12-06 05:58:43 +0100[diff] [blame]794
Stefan Roesee3060b02008-01-05 09:12:41 +0100[diff] [blame]795#define SDRAM_RTSR_TRK1SM_MASK 0xC0000000 /* Tracking State Mach 1*/
796#define SDRAM_RTSR_TRK1SM_ATBASE 0x00000000 /* atbase state */
797#define SDRAM_RTSR_TRK1SM_MISSED 0x40000000 /* missed state */
798#define SDRAM_RTSR_TRK1SM_ATPLS1 0x80000000 /* atpls1 state */
799#define SDRAM_RTSR_TRK1SM_RESET 0xC0000000 /* reset state */
800
Stefan Roesef1990632007-12-06 05:58:43 +0100[diff] [blame]801#define SDR0_MFR_FIXD 0x10000000 /* Workaround for PCI/DMA */
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]802#endif /* CONFIG_440SPE */
803
Larry Johnson19b3d372007-12-22 15:15:13 -0500[diff] [blame]804#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
805/*-----------------------------------------------------------------------------
806 | SDRAM Controller
807 +----------------------------------------------------------------------------*/
808#define DDR0_00 0x00
809#define DDR0_00_INT_ACK_MASK 0x7F000000 /* Write only */
810#define DDR0_00_INT_ACK_ALL 0x7F000000
811#define DDR0_00_INT_ACK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
812#define DDR0_00_INT_ACK_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
813/* Status */
814#define DDR0_00_INT_STATUS_MASK 0x00FF0000 /* Read only */
815/* Bit0. A single access outside the defined PHYSICAL memory space detected. */
816#define DDR0_00_INT_STATUS_BIT0 0x00010000
817/* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */
818#define DDR0_00_INT_STATUS_BIT1 0x00020000
819/* Bit2. Single correctable ECC event detected */
820#define DDR0_00_INT_STATUS_BIT2 0x00040000
821/* Bit3. Multiple correctable ECC events detected. */
822#define DDR0_00_INT_STATUS_BIT3 0x00080000
823/* Bit4. Single uncorrectable ECC event detected. */
824#define DDR0_00_INT_STATUS_BIT4 0x00100000
825/* Bit5. Multiple uncorrectable ECC events detected. */
826#define DDR0_00_INT_STATUS_BIT5 0x00200000
827/* Bit6. DRAM initialization complete. */
828#define DDR0_00_INT_STATUS_BIT6 0x00400000
829/* Bit7. Logical OR of all lower bits. */
830#define DDR0_00_INT_STATUS_BIT7 0x00800000
831
832#define DDR0_00_INT_STATUS_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
833#define DDR0_00_INT_STATUS_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
834#define DDR0_00_DLL_INCREMENT_MASK 0x00007F00
835#define DDR0_00_DLL_INCREMENT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
836#define DDR0_00_DLL_INCREMENT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
837#define DDR0_00_DLL_START_POINT_MASK 0x0000007F
838#define DDR0_00_DLL_START_POINT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
839#define DDR0_00_DLL_START_POINT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
840
841#define DDR0_01 0x01
842#define DDR0_01_PLB0_DB_CS_LOWER_MASK 0x1F000000
843#define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
844#define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
845#define DDR0_01_PLB0_DB_CS_UPPER_MASK 0x001F0000
846#define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16)
847#define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n) ((((unsigned long)(n))>>16)&0x1F)
848#define DDR0_01_OUT_OF_RANGE_TYPE_MASK 0x00000700 /* Read only */
849#define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
850#define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
851#define DDR0_01_INT_MASK_MASK 0x000000FF
852#define DDR0_01_INT_MASK_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
853#define DDR0_01_INT_MASK_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
854#define DDR0_01_INT_MASK_ALL_ON 0x000000FF
855#define DDR0_01_INT_MASK_ALL_OFF 0x00000000
856
857#define DDR0_02 0x02
858#define DDR0_02_MAX_CS_REG_MASK 0x02000000 /* Read only */
859#define DDR0_02_MAX_CS_REG_ENCODE(n) ((((unsigned long)(n))&0x2)<<24)
860#define DDR0_02_MAX_CS_REG_DECODE(n) ((((unsigned long)(n))>>24)&0x2)
861#define DDR0_02_MAX_COL_REG_MASK 0x000F0000 /* Read only */
862#define DDR0_02_MAX_COL_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<16)
863#define DDR0_02_MAX_COL_REG_DECODE(n) ((((unsigned long)(n))>>16)&0xF)
864#define DDR0_02_MAX_ROW_REG_MASK 0x00000F00 /* Read only */
865#define DDR0_02_MAX_ROW_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
866#define DDR0_02_MAX_ROW_REG_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
867#define DDR0_02_START_MASK 0x00000001
868#define DDR0_02_START_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
869#define DDR0_02_START_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
870#define DDR0_02_START_OFF 0x00000000
871#define DDR0_02_START_ON 0x00000001
872
873#define DDR0_03 0x03
874#define DDR0_03_BSTLEN_MASK 0x07000000
875#define DDR0_03_BSTLEN_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
876#define DDR0_03_BSTLEN_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
877#define DDR0_03_CASLAT_MASK 0x00070000
878#define DDR0_03_CASLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
879#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
880#define DDR0_03_CASLAT_LIN_MASK 0x00000F00
881#define DDR0_03_CASLAT_LIN_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
882#define DDR0_03_CASLAT_LIN_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
883#define DDR0_03_INITAREF_MASK 0x0000000F
884#define DDR0_03_INITAREF_ENCODE(n) ((((unsigned long)(n))&0xF)<<0)
885#define DDR0_03_INITAREF_DECODE(n) ((((unsigned long)(n))>>0)&0xF)
886
887#define DDR0_04 0x04
888#define DDR0_04_TRC_MASK 0x1F000000
889#define DDR0_04_TRC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
890#define DDR0_04_TRC_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
891#define DDR0_04_TRRD_MASK 0x00070000
892#define DDR0_04_TRRD_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
893#define DDR0_04_TRRD_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
894#define DDR0_04_TRTP_MASK 0x00000700
895#define DDR0_04_TRTP_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
896#define DDR0_04_TRTP_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
897
898#define DDR0_05 0x05
899#define DDR0_05_TMRD_MASK 0x1F000000
900#define DDR0_05_TMRD_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
901#define DDR0_05_TMRD_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
902#define DDR0_05_TEMRS_MASK 0x00070000
903#define DDR0_05_TEMRS_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
904#define DDR0_05_TEMRS_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
905#define DDR0_05_TRP_MASK 0x00000F00
906#define DDR0_05_TRP_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
907#define DDR0_05_TRP_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
908#define DDR0_05_TRAS_MIN_MASK 0x000000FF
909#define DDR0_05_TRAS_MIN_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
910#define DDR0_05_TRAS_MIN_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
911
912#define DDR0_06 0x06
913#define DDR0_06_WRITEINTERP_MASK 0x01000000
914#define DDR0_06_WRITEINTERP_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
915#define DDR0_06_WRITEINTERP_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
916#define DDR0_06_TWTR_MASK 0x00070000
917#define DDR0_06_TWTR_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
918#define DDR0_06_TWTR_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
919#define DDR0_06_TDLL_MASK 0x0000FF00
920#define DDR0_06_TDLL_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
921#define DDR0_06_TDLL_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
922#define DDR0_06_TRFC_MASK 0x0000007F
923#define DDR0_06_TRFC_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
924#define DDR0_06_TRFC_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
925
926#define DDR0_07 0x07
927#define DDR0_07_NO_CMD_INIT_MASK 0x01000000
928#define DDR0_07_NO_CMD_INIT_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
929#define DDR0_07_NO_CMD_INIT_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
930#define DDR0_07_TFAW_MASK 0x001F0000
931#define DDR0_07_TFAW_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16)
932#define DDR0_07_TFAW_DECODE(n) ((((unsigned long)(n))>>16)&0x1F)
933#define DDR0_07_AUTO_REFRESH_MODE_MASK 0x00000100
934#define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
935#define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
936#define DDR0_07_AREFRESH_MASK 0x00000001
937#define DDR0_07_AREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
938#define DDR0_07_AREFRESH_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
939
940#define DDR0_08 0x08
941#define DDR0_08_WRLAT_MASK 0x07000000
942#define DDR0_08_WRLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
943#define DDR0_08_WRLAT_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
944#define DDR0_08_TCPD_MASK 0x00FF0000
945#define DDR0_08_TCPD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
946#define DDR0_08_TCPD_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
947#define DDR0_08_DQS_N_EN_MASK 0x00000100
948#define DDR0_08_DQS_N_EN_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
949#define DDR0_08_DQS_N_EN_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
950#define DDR0_08_DDRII_SDRAM_MODE_MASK 0x00000001
951#define DDR0_08_DDRII_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
952#define DDR0_08_DDRII_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
953
954#define DDR0_09 0x09
955#define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK 0x1F000000
956#define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
957#define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
958#define DDR0_09_RTT_0_MASK 0x00030000
959#define DDR0_09_RTT_0_ENCODE(n) ((((unsigned long)(n))&0x3)<<16)
960#define DDR0_09_RTT_0_DECODE(n) ((((unsigned long)(n))>>16)&0x3)
961#define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK 0x00007F00
962#define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
963#define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
964#define DDR0_09_WR_DQS_SHIFT_MASK 0x0000007F
965#define DDR0_09_WR_DQS_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
966#define DDR0_09_WR_DQS_SHIFT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
967
968#define DDR0_10 0x0A
969#define DDR0_10_WRITE_MODEREG_MASK 0x00010000 /* Write only */
970#define DDR0_10_WRITE_MODEREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
971#define DDR0_10_WRITE_MODEREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
972#define DDR0_10_CS_MAP_MASK 0x00000300
973#define DDR0_10_CS_MAP_NO_MEM 0x00000000
974#define DDR0_10_CS_MAP_RANK0_INSTALLED 0x00000100
975#define DDR0_10_CS_MAP_RANK1_INSTALLED 0x00000200
976#define DDR0_10_CS_MAP_ENCODE(n) ((((unsigned long)(n))&0x3)<<8)
977#define DDR0_10_CS_MAP_DECODE(n) ((((unsigned long)(n))>>8)&0x3)
978#define DDR0_10_OCD_ADJUST_PUP_CS_0_MASK 0x0000001F
979#define DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<0)
980#define DDR0_10_OCD_ADJUST_PUP_CS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x1F)
981
982#define DDR0_11 0x0B
983#define DDR0_11_SREFRESH_MASK 0x01000000
984#define DDR0_11_SREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
985#define DDR0_11_SREFRESH_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
986#define DDR0_11_TXSNR_MASK 0x00FF0000
987#define DDR0_11_TXSNR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
988#define DDR0_11_TXSNR_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
989#define DDR0_11_TXSR_MASK 0x0000FF00
990#define DDR0_11_TXSR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
991#define DDR0_11_TXSR_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
992
993#define DDR0_12 0x0C
994#define DDR0_12_TCKE_MASK 0x0000007
995#define DDR0_12_TCKE_ENCODE(n) ((((unsigned long)(n))&0x7)<<0)
996#define DDR0_12_TCKE_DECODE(n) ((((unsigned long)(n))>>0)&0x7)
997
998#define DDR0_14 0x0E
999#define DDR0_14_DLL_BYPASS_MODE_MASK 0x01000000
1000#define DDR0_14_DLL_BYPASS_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
1001#define DDR0_14_DLL_BYPASS_MODE_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
1002#define DDR0_14_REDUC_MASK 0x00010000
1003#define DDR0_14_REDUC_64BITS 0x00000000
1004#define DDR0_14_REDUC_32BITS 0x00010000
1005#define DDR0_14_REDUC_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
1006#define DDR0_14_REDUC_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
1007#define DDR0_14_REG_DIMM_ENABLE_MASK 0x00000100
1008#define DDR0_14_REG_DIMM_ENABLE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
1009#define DDR0_14_REG_DIMM_ENABLE_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
1010
1011#define DDR0_17 0x11
1012#define DDR0_17_DLL_DQS_DELAY_0_MASK 0x7F000000
1013#define DDR0_17_DLL_DQS_DELAY_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
1014#define DDR0_17_DLL_DQS_DELAY_0_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
1015#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */
1016#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000
1017#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000
1018#define DDR0_17_DLLLOCKREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
1019#define DDR0_17_DLLLOCKREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
1020#define DDR0_17_DLL_LOCK_MASK 0x00007F00 /* Read only */
1021#define DDR0_17_DLL_LOCK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
1022#define DDR0_17_DLL_LOCK_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
1023
1024#define DDR0_18 0x12
1025#define DDR0_18_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F
1026#define DDR0_18_DLL_DQS_DELAY_4_MASK 0x7F000000
1027#define DDR0_18_DLL_DQS_DELAY_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
1028#define DDR0_18_DLL_DQS_DELAY_4_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
1029#define DDR0_18_DLL_DQS_DELAY_3_MASK 0x007F0000
1030#define DDR0_18_DLL_DQS_DELAY_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
1031#define DDR0_18_DLL_DQS_DELAY_3_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
1032#define DDR0_18_DLL_DQS_DELAY_2_MASK 0x00007F00
1033#define DDR0_18_DLL_DQS_DELAY_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
1034#define DDR0_18_DLL_DQS_DELAY_2_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
1035#define DDR0_18_DLL_DQS_DELAY_1_MASK 0x0000007F
1036#define DDR0_18_DLL_DQS_DELAY_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
1037#define DDR0_18_DLL_DQS_DELAY_1_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
1038
1039#define DDR0_19 0x13
1040#define DDR0_19_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F
1041#define DDR0_19_DLL_DQS_DELAY_8_MASK 0x7F000000
1042#define DDR0_19_DLL_DQS_DELAY_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
1043#define DDR0_19_DLL_DQS_DELAY_8_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
1044#define DDR0_19_DLL_DQS_DELAY_7_MASK 0x007F0000
1045#define DDR0_19_DLL_DQS_DELAY_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
1046#define DDR0_19_DLL_DQS_DELAY_7_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
1047#define DDR0_19_DLL_DQS_DELAY_6_MASK 0x00007F00
1048#define DDR0_19_DLL_DQS_DELAY_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
1049#define DDR0_19_DLL_DQS_DELAY_6_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
1050#define DDR0_19_DLL_DQS_DELAY_5_MASK 0x0000007F
1051#define DDR0_19_DLL_DQS_DELAY_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
1052#define DDR0_19_DLL_DQS_DELAY_5_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
1053
1054#define DDR0_20 0x14
1055#define DDR0_20_DLL_DQS_BYPASS_3_MASK 0x7F000000
1056#define DDR0_20_DLL_DQS_BYPASS_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
1057#define DDR0_20_DLL_DQS_BYPASS_3_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
1058#define DDR0_20_DLL_DQS_BYPASS_2_MASK 0x007F0000
1059#define DDR0_20_DLL_DQS_BYPASS_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
1060#define DDR0_20_DLL_DQS_BYPASS_2_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
1061#define DDR0_20_DLL_DQS_BYPASS_1_MASK 0x00007F00
1062#define DDR0_20_DLL_DQS_BYPASS_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
1063#define DDR0_20_DLL_DQS_BYPASS_1_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
1064#define DDR0_20_DLL_DQS_BYPASS_0_MASK 0x0000007F
1065#define DDR0_20_DLL_DQS_BYPASS_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
1066#define DDR0_20_DLL_DQS_BYPASS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
1067
1068#define DDR0_21 0x15
1069#define DDR0_21_DLL_DQS_BYPASS_7_MASK 0x7F000000
1070#define DDR0_21_DLL_DQS_BYPASS_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
1071#define DDR0_21_DLL_DQS_BYPASS_7_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
1072#define DDR0_21_DLL_DQS_BYPASS_6_MASK 0x007F0000
1073#define DDR0_21_DLL_DQS_BYPASS_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
1074#define DDR0_21_DLL_DQS_BYPASS_6_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
1075#define DDR0_21_DLL_DQS_BYPASS_5_MASK 0x00007F00
1076#define DDR0_21_DLL_DQS_BYPASS_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
1077#define DDR0_21_DLL_DQS_BYPASS_5_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
1078#define DDR0_21_DLL_DQS_BYPASS_4_MASK 0x0000007F
1079#define DDR0_21_DLL_DQS_BYPASS_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
1080#define DDR0_21_DLL_DQS_BYPASS_4_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
1081
1082#define DDR0_22 0x16
1083#define DDR0_22_CTRL_RAW_MASK 0x03000000
1084#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 /* ECC not being used */
1085#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 /* ECC checking is on, but no attempts to correct */
1086#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 /* No ECC RAM storage available */
1087#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC checking and correcting on */
1088#define DDR0_22_CTRL_RAW_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
1089#define DDR0_22_CTRL_RAW_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
1090#define DDR0_22_DQS_OUT_SHIFT_BYPASS_MASK 0x007F0000
1091#define DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
1092#define DDR0_22_DQS_OUT_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
1093#define DDR0_22_DQS_OUT_SHIFT_MASK 0x00007F00
1094#define DDR0_22_DQS_OUT_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
1095#define DDR0_22_DQS_OUT_SHIFT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
1096#define DDR0_22_DLL_DQS_BYPASS_8_MASK 0x0000007F
1097#define DDR0_22_DLL_DQS_BYPASS_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
1098#define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
1099
1100#define DDR0_23 0x17
1101#define DDR0_23_ODT_RD_MAP_CS0_MASK 0x03000000
1102#define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
1103#define DDR0_23_ODT_RD_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
1104#define DDR0_23_ECC_C_SYND_MASK 0x00FF0000 /* Read only */
1105#define DDR0_23_ECC_C_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
1106#define DDR0_23_ECC_C_SYND_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
1107#define DDR0_23_ECC_U_SYND_MASK 0x0000FF00 /* Read only */
1108#define DDR0_23_ECC_U_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
1109#define DDR0_23_ECC_U_SYND_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
1110#define DDR0_23_FWC_MASK 0x00000001 /* Write only */
1111#define DDR0_23_FWC_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
1112#define DDR0_23_FWC_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
1113
1114#define DDR0_24 0x18
1115#define DDR0_24_RTT_PAD_TERMINATION_MASK 0x03000000
1116#define DDR0_24_RTT_PAD_TERMINATION_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
1117#define DDR0_24_RTT_PAD_TERMINATION_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
1118#define DDR0_24_ODT_WR_MAP_CS1_MASK 0x00030000
1119#define DDR0_24_ODT_WR_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<16)
1120#define DDR0_24_ODT_WR_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>16)&0x3)
1121#define DDR0_24_ODT_RD_MAP_CS1_MASK 0x00000300
1122#define DDR0_24_ODT_RD_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<8)
1123#define DDR0_24_ODT_RD_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>8)&0x3)
1124#define DDR0_24_ODT_WR_MAP_CS0_MASK 0x00000003
1125#define DDR0_24_ODT_WR_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<0)
1126#define DDR0_24_ODT_WR_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>0)&0x3)
1127
1128#define DDR0_25 0x19
1129#define DDR0_25_VERSION_MASK 0xFFFF0000 /* Read only */
1130#define DDR0_25_VERSION_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
1131#define DDR0_25_VERSION_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
1132#define DDR0_25_OUT_OF_RANGE_LENGTH_MASK 0x000003FF /* Read only */
1133#define DDR0_25_OUT_OF_RANGE_LENGTH_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
1134#define DDR0_25_OUT_OF_RANGE_LENGTH_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
1135
1136#define DDR0_26 0x1A
1137#define DDR0_26_TRAS_MAX_MASK 0xFFFF0000
1138#define DDR0_26_TRAS_MAX_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
1139#define DDR0_26_TRAS_MAX_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
1140#define DDR0_26_TREF_MASK 0x00003FFF
1141#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0)
1142#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF)
1143
1144#define DDR0_27 0x1B
1145#define DDR0_27_EMRS_DATA_MASK 0x3FFF0000
1146#define DDR0_27_EMRS_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16)
1147#define DDR0_27_EMRS_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF)
1148#define DDR0_27_TINIT_MASK 0x0000FFFF
1149#define DDR0_27_TINIT_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0)
1150#define DDR0_27_TINIT_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF)
1151
1152#define DDR0_28 0x1C
1153#define DDR0_28_EMRS3_DATA_MASK 0x3FFF0000
1154#define DDR0_28_EMRS3_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16)
1155#define DDR0_28_EMRS3_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF)
1156#define DDR0_28_EMRS2_DATA_MASK 0x00003FFF
1157#define DDR0_28_EMRS2_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0)
1158#define DDR0_28_EMRS2_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF)
1159
1160#define DDR0_31 0x1F
1161#define DDR0_31_XOR_CHECK_BITS_MASK 0x0000FFFF
1162#define DDR0_31_XOR_CHECK_BITS_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0)
1163#define DDR0_31_XOR_CHECK_BITS_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF)
1164
1165#define DDR0_32 0x20
1166#define DDR0_32_OUT_OF_RANGE_ADDR_MASK 0xFFFFFFFF /* Read only */
1167#define DDR0_32_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
1168#define DDR0_32_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
1169
1170#define DDR0_33 0x21
1171#define DDR0_33_OUT_OF_RANGE_ADDR_MASK 0x00000001 /* Read only */
1172#define DDR0_33_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
1173#define DDR0_33_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
1174
1175#define DDR0_34 0x22
1176#define DDR0_34_ECC_U_ADDR_MASK 0xFFFFFFFF /* Read only */
1177#define DDR0_34_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
1178#define DDR0_34_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
1179
1180#define DDR0_35 0x23
1181#define DDR0_35_ECC_U_ADDR_MASK 0x00000001 /* Read only */
1182#define DDR0_35_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
1183#define DDR0_35_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
1184
1185#define DDR0_36 0x24
1186#define DDR0_36_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */
1187#define DDR0_36_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
1188#define DDR0_36_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
1189
1190#define DDR0_37 0x25
1191#define DDR0_37_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */
1192#define DDR0_37_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
1193#define DDR0_37_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
1194
1195#define DDR0_38 0x26
1196#define DDR0_38_ECC_C_ADDR_MASK 0xFFFFFFFF /* Read only */
1197#define DDR0_38_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
1198#define DDR0_38_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
1199
1200#define DDR0_39 0x27
1201#define DDR0_39_ECC_C_ADDR_MASK 0x00000001 /* Read only */
1202#define DDR0_39_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
1203#define DDR0_39_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
1204
1205#define DDR0_40 0x28
1206#define DDR0_40_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */
1207#define DDR0_40_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
1208#define DDR0_40_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
1209
1210#define DDR0_41 0x29
1211#define DDR0_41_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */
1212#define DDR0_41_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
1213#define DDR0_41_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
1214
1215#define DDR0_42 0x2A
1216#define DDR0_42_ADDR_PINS_MASK 0x07000000
1217#define DDR0_42_ADDR_PINS_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
1218#define DDR0_42_ADDR_PINS_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
1219#define DDR0_42_CASLAT_LIN_GATE_MASK 0x0000000F
1220#define DDR0_42_CASLAT_LIN_GATE_ENCODE(n) ((((unsigned long)(n))&0xF)<<0)
1221#define DDR0_42_CASLAT_LIN_GATE_DECODE(n) ((((unsigned long)(n))>>0)&0xF)
1222
1223#define DDR0_43 0x2B
1224#define DDR0_43_TWR_MASK 0x07000000
1225#define DDR0_43_TWR_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
1226#define DDR0_43_TWR_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
1227#define DDR0_43_APREBIT_MASK 0x000F0000
1228#define DDR0_43_APREBIT_ENCODE(n) ((((unsigned long)(n))&0xF)<<16)
1229#define DDR0_43_APREBIT_DECODE(n) ((((unsigned long)(n))>>16)&0xF)
1230#define DDR0_43_COLUMN_SIZE_MASK 0x00000700
1231#define DDR0_43_COLUMN_SIZE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
1232#define DDR0_43_COLUMN_SIZE_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
1233#define DDR0_43_EIGHT_BANK_MODE_MASK 0x00000001
1234#define DDR0_43_EIGHT_BANK_MODE_8_BANKS 0x00000001
1235#define DDR0_43_EIGHT_BANK_MODE_4_BANKS 0x00000000
1236#define DDR0_43_EIGHT_BANK_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
1237#define DDR0_43_EIGHT_BANK_MODE_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
1238
1239#define DDR0_44 0x2C
1240#define DDR0_44_TRCD_MASK 0x000000FF
1241#define DDR0_44_TRCD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
1242#define DDR0_44_TRCD_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
1243
1244#endif /* CONFIG_440EPX */
1245
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1246/*-----------------------------------------------------------------------------
Wolfgang Denkff4b91f2005-09-25 16:01:42 +0200[diff] [blame]1247 | External Bus Controller
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1248 +----------------------------------------------------------------------------*/
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]1249/* values for ebccfga register - indirect addressing of these regs */
1250#define pb0cr 0x00 /* periph bank 0 config reg */
1251#define pb1cr 0x01 /* periph bank 1 config reg */
1252#define pb2cr 0x02 /* periph bank 2 config reg */
1253#define pb3cr 0x03 /* periph bank 3 config reg */
1254#define pb4cr 0x04 /* periph bank 4 config reg */
1255#define pb5cr 0x05 /* periph bank 5 config reg */
1256#define pb6cr 0x06 /* periph bank 6 config reg */
1257#define pb7cr 0x07 /* periph bank 7 config reg */
1258#define pb0ap 0x10 /* periph bank 0 access parameters */
1259#define pb1ap 0x11 /* periph bank 1 access parameters */
1260#define pb2ap 0x12 /* periph bank 2 access parameters */
1261#define pb3ap 0x13 /* periph bank 3 access parameters */
1262#define pb4ap 0x14 /* periph bank 4 access parameters */
1263#define pb5ap 0x15 /* periph bank 5 access parameters */
1264#define pb6ap 0x16 /* periph bank 6 access parameters */
1265#define pb7ap 0x17 /* periph bank 7 access parameters */
1266#define pbear 0x20 /* periph bus error addr reg */
1267#define pbesr 0x21 /* periph bus error status reg */
1268#define xbcfg 0x23 /* external bus configuration reg */
Stefan Roesea8856e32007-02-20 10:57:08 +0100[diff] [blame]1269#define EBC0_CFG 0x23 /* external bus configuration reg */
Wolfgang Denkff4b91f2005-09-25 16:01:42 +0200[diff] [blame]1270#define xbcid 0x24 /* external bus core id reg */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1271
Stefan Roese42fbddd2006-09-07 11:51:23 +0200[diff] [blame]1272#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
1273 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
Stefan Roese326c9712005-08-01 16:41:48 +0200[diff] [blame]1274
1275/* PLB4 to PLB3 Bridge OUT */
1276#define P4P3_DCR_BASE 0x020
1277#define p4p3_esr0_read (P4P3_DCR_BASE+0x0)
1278#define p4p3_esr0_write (P4P3_DCR_BASE+0x1)
1279#define p4p3_eadr (P4P3_DCR_BASE+0x2)
1280#define p4p3_euadr (P4P3_DCR_BASE+0x3)
1281#define p4p3_esr1_read (P4P3_DCR_BASE+0x4)
1282#define p4p3_esr1_write (P4P3_DCR_BASE+0x5)
1283#define p4p3_confg (P4P3_DCR_BASE+0x6)
1284#define p4p3_pic (P4P3_DCR_BASE+0x7)
1285#define p4p3_peir (P4P3_DCR_BASE+0x8)
1286#define p4p3_rev (P4P3_DCR_BASE+0xA)
1287
1288/* PLB3 to PLB4 Bridge IN */
1289#define P3P4_DCR_BASE 0x030
1290#define p3p4_esr0_read (P3P4_DCR_BASE+0x0)
1291#define p3p4_esr0_write (P3P4_DCR_BASE+0x1)
1292#define p3p4_eadr (P3P4_DCR_BASE+0x2)
1293#define p3p4_euadr (P3P4_DCR_BASE+0x3)
1294#define p3p4_esr1_read (P3P4_DCR_BASE+0x4)
1295#define p3p4_esr1_write (P3P4_DCR_BASE+0x5)
1296#define p3p4_confg (P3P4_DCR_BASE+0x6)
1297#define p3p4_pic (P3P4_DCR_BASE+0x7)
1298#define p3p4_peir (P3P4_DCR_BASE+0x8)
1299#define p3p4_rev (P3P4_DCR_BASE+0xA)
1300
1301/* PLB3 Arbiter */
1302#define PLB3_DCR_BASE 0x070
1303#define plb3_revid (PLB3_DCR_BASE+0x2)
1304#define plb3_besr (PLB3_DCR_BASE+0x3)
1305#define plb3_bear (PLB3_DCR_BASE+0x6)
1306#define plb3_acr (PLB3_DCR_BASE+0x7)
1307
1308/* PLB4 Arbiter - PowerPC440EP Pass1 */
1309#define PLB4_DCR_BASE 0x080
Stefan Roesebc7057d2007-01-05 10:40:36 +0100[diff] [blame]1310#define plb4_acr (PLB4_DCR_BASE+0x1)
Stefan Roese326c9712005-08-01 16:41:48 +0200[diff] [blame]1311#define plb4_revid (PLB4_DCR_BASE+0x2)
Stefan Roese326c9712005-08-01 16:41:48 +0200[diff] [blame]1312#define plb4_besr (PLB4_DCR_BASE+0x4)
1313#define plb4_bearl (PLB4_DCR_BASE+0x6)
1314#define plb4_bearh (PLB4_DCR_BASE+0x7)
1315
Stefan Roesebc7057d2007-01-05 10:40:36 +0100[diff] [blame]1316#define PLB4_ACR_WRP (0x80000000 >> 7)
1317
Stefan Roese326c9712005-08-01 16:41:48 +0200[diff] [blame]1318/* Nebula PLB4 Arbiter - PowerPC440EP */
1319#define PLB_ARBITER_BASE 0x80
1320
1321#define plb0_revid (PLB_ARBITER_BASE+ 0x00)
1322#define plb0_acr (PLB_ARBITER_BASE+ 0x01)
1323#define plb0_acr_ppm_mask 0xF0000000
1324#define plb0_acr_ppm_fixed 0x00000000
1325#define plb0_acr_ppm_fair 0xD0000000
1326#define plb0_acr_hbu_mask 0x08000000
1327#define plb0_acr_hbu_disabled 0x00000000
1328#define plb0_acr_hbu_enabled 0x08000000
1329#define plb0_acr_rdp_mask 0x06000000
1330#define plb0_acr_rdp_disabled 0x00000000
1331#define plb0_acr_rdp_2deep 0x02000000
1332#define plb0_acr_rdp_3deep 0x04000000
1333#define plb0_acr_rdp_4deep 0x06000000
1334#define plb0_acr_wrp_mask 0x01000000
1335#define plb0_acr_wrp_disabled 0x00000000
1336#define plb0_acr_wrp_2deep 0x01000000
1337
1338#define plb0_besrl (PLB_ARBITER_BASE+ 0x02)
1339#define plb0_besrh (PLB_ARBITER_BASE+ 0x03)
1340#define plb0_bearl (PLB_ARBITER_BASE+ 0x04)
1341#define plb0_bearh (PLB_ARBITER_BASE+ 0x05)
1342#define plb0_ccr (PLB_ARBITER_BASE+ 0x08)
1343
1344#define plb1_acr (PLB_ARBITER_BASE+ 0x09)
1345#define plb1_acr_ppm_mask 0xF0000000
1346#define plb1_acr_ppm_fixed 0x00000000
1347#define plb1_acr_ppm_fair 0xD0000000
1348#define plb1_acr_hbu_mask 0x08000000
1349#define plb1_acr_hbu_disabled 0x00000000
1350#define plb1_acr_hbu_enabled 0x08000000
1351#define plb1_acr_rdp_mask 0x06000000
1352#define plb1_acr_rdp_disabled 0x00000000
1353#define plb1_acr_rdp_2deep 0x02000000
1354#define plb1_acr_rdp_3deep 0x04000000
1355#define plb1_acr_rdp_4deep 0x06000000
1356#define plb1_acr_wrp_mask 0x01000000
1357#define plb1_acr_wrp_disabled 0x00000000
1358#define plb1_acr_wrp_2deep 0x01000000
1359
1360#define plb1_besrl (PLB_ARBITER_BASE+ 0x0A)
1361#define plb1_besrh (PLB_ARBITER_BASE+ 0x0B)
1362#define plb1_bearl (PLB_ARBITER_BASE+ 0x0C)
1363#define plb1_bearh (PLB_ARBITER_BASE+ 0x0D)
1364
Stefan Roese363330b2005-08-04 17:09:16 +0200[diff] [blame]1365/* Pin Function Control Register 1 */
1366#define SDR0_PFC1 0x4101
1367#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
1368#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
1369#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
1370#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
1371#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
1372#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
1373#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
1374#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
1375#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
1376#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
1377#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
1378#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
1379#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */
1380#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
1381#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
1382#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */
1383#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
1384#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
1385#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
1386#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
1387#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
1388#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */
1389#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */
1390#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */
1391
1392#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */
1393#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */
1394#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
1395#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
1396
1397/* USB Control Register */
1398#define SDR0_USB0 0x0320
1399#define SDR0_USB0_USB_DEVSEL_MASK 0x00000002 /* USB Device Selection */
1400#define SDR0_USB0_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */
1401#define SDR0_USB0_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */
1402#define SDR0_USB0_LEEN_MASK 0x00000001 /* Little Endian selection */
1403#define SDR0_USB0_LEEN_DISABLE 0x00000000 /* Little Endian Disable */
1404#define SDR0_USB0_LEEN_ENABLE 0x00000001 /* Little Endian Enable */
1405
Stefan Roese42fbddd2006-09-07 11:51:23 +0200[diff] [blame]1406/* Miscealleneaous Function Reg. */
1407#define SDR0_MFR 0x4300
1408#define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */
1409#define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000
1410#define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */
1411#define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000
1412#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
1413#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
1414#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
1415#define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */
1416#define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */
1417#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
1418#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
1419#define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
1420#define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3)
1421
1422#define SDR0_MFR_ERRATA3_EN0 0x00800000
1423#define SDR0_MFR_ERRATA3_EN1 0x00400000
1424#define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */
1425#define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Enable on both EMAC3 0-1 */
1426#define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */
1427#define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */
1428#define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */
1429
Stefan Roese3b897fc2008-01-09 10:28:20 +0100[diff] [blame]1430#define GPT0_COMP6 0x00000098
Stefan Roese42fbddd2006-09-07 11:51:23 +0200[diff] [blame]1431
1432#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
Niklaus Giger77cad902007-06-27 18:11:38 +0200[diff] [blame]1433#define SDR0_USB2D0CR 0x0320
Stefan Roese42fbddd2006-09-07 11:51:23 +0200[diff] [blame]1434#define SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK 0x00000004 /* USB 2.0 Device/EBC Master Selection */
1435#define SDR0_USB2D0CR_USB2DEV_SELECTION 0x00000004 /* USB 2.0 Device Selection */
1436#define SDR0_USB2D0CR_EBC_SELECTION 0x00000000 /* EBC Selection */
1437
1438#define SDR0_USB2D0CR_USB_DEV_INT_SEL_MASK 0x00000002 /* USB Device Interface Selection */
1439#define SDR0_USB2D0CR_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */
1440#define SDR0_USB2D0CR_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */
1441
1442#define SDR0_USB2D0CR_LEEN_MASK 0x00000001 /* Little Endian selection */
1443#define SDR0_USB2D0CR_LEEN_DISABLE 0x00000000 /* Little Endian Disable */
1444#define SDR0_USB2D0CR_LEEN_ENABLE 0x00000001 /* Little Endian Enable */
1445
1446/* USB2 Host Control Register */
1447#define SDR0_USB2H0CR 0x0340
1448#define SDR0_USB2H0CR_WDINT_MASK 0x00000001 /* Host UTMI Word Interface */
1449#define SDR0_USB2H0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit/60MHz */
1450#define SDR0_USB2H0CR_WDINT_16BIT_30MHZ 0x00000001 /* 16-bit/30MHz */
1451#define SDR0_USB2H0CR_EFLADJ_MASK 0x0000007e /* EHCI Frame Length Adjustment */
1452
1453/* Pin Function Control Register 1 */
1454#define SDR0_PFC1 0x4101
1455#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
1456#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
1457#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
1458
1459#define SDR0_PFC1_SELECT_MASK 0x01C00000 /* Ethernet Pin Select EMAC 0 */
1460#define SDR0_PFC1_SELECT_CONFIG_1_1 0x00C00000 /* 1xMII using RGMII bridge */
1461#define SDR0_PFC1_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII bridge */
1462#define SDR0_PFC1_SELECT_CONFIG_2 0x00C00000 /* 1xGMII using RGMII bridge */
1463#define SDR0_PFC1_SELECT_CONFIG_3 0x01000000 /* 1xTBI using RGMII bridge */
1464#define SDR0_PFC1_SELECT_CONFIG_4 0x01400000 /* 2xRGMII using RGMII bridge */
1465#define SDR0_PFC1_SELECT_CONFIG_5 0x01800000 /* 2xRTBI using RGMII bridge */
1466#define SDR0_PFC1_SELECT_CONFIG_6 0x00800000 /* 2xSMII using ZMII bridge */
1467
1468#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
1469#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
1470#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
1471#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
1472#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
1473#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
1474#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
1475#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
1476#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
1477#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */
1478#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
1479#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
1480#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */
1481#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
1482#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
1483#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
1484#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
1485#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
1486#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */
1487#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */
1488#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */
1489
1490#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */
1491#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */
1492#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
1493#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
1494
1495/* Ethernet PLL Configuration Register */
1496#define SDR0_PFC2 0x4102
1497#define SDR0_PFC2_TUNE_MASK 0x01FF8000 /* Loop stability tuning bits */
1498#define SDR0_PFC2_MULTI_MASK 0x00007C00 /* Frequency multiplication selector */
1499#define SDR0_PFC2_RANGEB_MASK 0x00000380 /* PLLOUTB/C frequency selector */
1500#define SDR0_PFC2_RANGEA_MASK 0x00000071 /* PLLOUTA frequency selector */
1501
1502#define SDR0_PFC2_SELECT_MASK 0xE0000000 /* Ethernet Pin select EMAC1 */
1503#define SDR0_PFC2_SELECT_CONFIG_1_1 0x60000000 /* 1xMII using RGMII bridge */
1504#define SDR0_PFC2_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII bridge */
1505#define SDR0_PFC2_SELECT_CONFIG_2 0x60000000 /* 1xGMII using RGMII bridge */
1506#define SDR0_PFC2_SELECT_CONFIG_3 0x80000000 /* 1xTBI using RGMII bridge */
1507#define SDR0_PFC2_SELECT_CONFIG_4 0xA0000000 /* 2xRGMII using RGMII bridge */
1508#define SDR0_PFC2_SELECT_CONFIG_5 0xC0000000 /* 2xRTBI using RGMII bridge */
1509#define SDR0_PFC2_SELECT_CONFIG_6 0x40000000 /* 2xSMII using ZMII bridge */
1510
Stefan Roeseade5a512007-06-15 08:18:01 +0200[diff] [blame]1511#define SDR0_PFC4 0x4104
1512
Stefan Roese42fbddd2006-09-07 11:51:23 +0200[diff] [blame]1513/* USB2PHY0 Control Register */
1514#define SDR0_USB2PHY0CR 0x4103
1515#define SDR0_USB2PHY0CR_UTMICN_MASK 0x00100000 /* PHY UTMI interface connection */
1516#define SDR0_USB2PHY0CR_UTMICN_DEV 0x00000000 /* Device support */
1517#define SDR0_USB2PHY0CR_UTMICN_HOST 0x00100000 /* Host support */
1518
1519#define SDR0_USB2PHY0CR_DWNSTR_MASK 0x00400000 /* Select downstream port mode */
1520#define SDR0_USB2PHY0CR_DWNSTR_DEV 0x00000000 /* Device */
1521#define SDR0_USB2PHY0CR_DWNSTR_HOST 0x00400000 /* Host */
1522
1523#define SDR0_USB2PHY0CR_DVBUS_MASK 0x00800000 /* VBus detect (Device mode only) */
1524#define SDR0_USB2PHY0CR_DVBUS_PURDIS 0x00000000 /* Pull-up resistance on D+ is disabled */
1525#define SDR0_USB2PHY0CR_DVBUS_PUREN 0x00800000 /* Pull-up resistance on D+ is enabled */
1526
1527#define SDR0_USB2PHY0CR_WDINT_MASK 0x01000000 /* PHY UTMI data width and clock select */
1528#define SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit data/60MHz */
1529#define SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ 0x01000000 /* 16-bit data/30MHz */
1530
1531#define SDR0_USB2PHY0CR_LOOPEN_MASK 0x02000000 /* Loop back test enable */
1532#define SDR0_USB2PHY0CR_LOOP_ENABLE 0x00000000 /* Loop back disabled */
1533#define SDR0_USB2PHY0CR_LOOP_DISABLE 0x02000000 /* Loop back enabled (only test purposes) */
1534
1535#define SDR0_USB2PHY0CR_XOON_MASK 0x04000000 /* Force XO block on during a suspend */
1536#define SDR0_USB2PHY0CR_XO_ON 0x00000000 /* PHY XO block is powered-on */
1537#define SDR0_USB2PHY0CR_XO_OFF 0x04000000 /* PHY XO block is powered-off when all ports are suspended */
1538
1539#define SDR0_USB2PHY0CR_PWRSAV_MASK 0x08000000 /* Select PHY power-save mode */
1540#define SDR0_USB2PHY0CR_PWRSAV_OFF 0x00000000 /* Non-power-save mode */
1541#define SDR0_USB2PHY0CR_PWRSAV_ON 0x08000000 /* Power-save mode. Valid only for full-speed operation */
1542
1543#define SDR0_USB2PHY0CR_XOREF_MASK 0x10000000 /* Select reference clock source */
1544#define SDR0_USB2PHY0CR_XOREF_INTERNAL 0x00000000 /* PHY PLL uses chip internal 48M clock as a reference */
1545#define SDR0_USB2PHY0CR_XOREF_XO 0x10000000 /* PHY PLL uses internal XO block output as a reference */
1546
1547#define SDR0_USB2PHY0CR_XOCLK_MASK 0x20000000 /* Select clock for XO block */
1548#define SDR0_USB2PHY0CR_XOCLK_EXTERNAL 0x00000000 /* PHY macro used an external clock */
1549#define SDR0_USB2PHY0CR_XOCLK_CRYSTAL 0x20000000 /* PHY macro uses the clock from a crystal */
1550
1551#define SDR0_USB2PHY0CR_CLKSEL_MASK 0xc0000000 /* Select ref clk freq */
1552#define SDR0_USB2PHY0CR_CLKSEL_12MHZ 0x00000000 /* Select ref clk freq = 12 MHz*/
1553#define SDR0_USB2PHY0CR_CLKSEL_48MHZ 0x40000000 /* Select ref clk freq = 48 MHz*/
1554#define SDR0_USB2PHY0CR_CLKSEL_24MHZ 0x80000000 /* Select ref clk freq = 24 MHz*/
1555
1556/* Miscealleneaous Function Reg. */
1557#define SDR0_MFR 0x4300
1558#define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */
1559#define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000
1560#define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */
1561#define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000
1562#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
1563#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
1564#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
1565#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
1566#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
1567#define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
1568#define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3)
1569
1570#define SDR0_MFR_ERRATA3_EN0 0x00800000
1571#define SDR0_MFR_ERRATA3_EN1 0x00400000
1572#define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */
1573#define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Enable on both EMAC3 0-1 */
1574#define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */
1575#define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */
1576#define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */
1577
1578#endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */
1579
Stefan Roese363330b2005-08-04 17:09:16 +0200[diff] [blame]1580/* CUST0 Customer Configuration Register0 */
1581#define SDR0_CUST0 0x4000
1582#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */
1583#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */
1584#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */
1585#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */
1586
1587#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */
1588#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */
1589#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */
1590
1591#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */
1592#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */
1593#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */
1594
1595#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */
1596#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
1597#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
1598
1599#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */
1600#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22)
1601#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
1602
1603#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */
1604#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */
1605#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */
1606
1607#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */
1608#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */
1609#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */
1610
1611#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */
1612#define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4)
1613#define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF)
1614
1615#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */
1616#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */
1617#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Select Gating Enable */
1618#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */
1619#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */
1620#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */
1621#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */
1622
1623/* CUST1 Customer Configuration Register1 */
1624#define SDR0_CUST1 0x4002
1625#define SDR0_CUST1_NDRSC_MASK 0xFFFF0000 /* NDRSC Device Read Count */
1626#define SDR0_CUST1_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
1627#define SDR0_CUST1_NDRSC_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
1628
1629/* Pin Function Control Register 0 */
1630#define SDR0_PFC0 0x4100
1631#define SDR0_PFC0_CPU_TR_EN_MASK 0x00000100 /* CPU Trace Enable Mask */
1632#define SDR0_PFC0_CPU_TRACE_EN 0x00000100 /* CPU Trace Enable */
1633#define SDR0_PFC0_CPU_TRACE_DIS 0x00000100 /* CPU Trace Disable */
1634#define SDR0_PFC0_CTE_ENCODE(n) ((((unsigned long)(n))&0x01)<<8)
1635#define SDR0_PFC0_CTE_DECODE(n) ((((unsigned long)(n))>>8)&0x01)
1636
1637/* Pin Function Control Register 1 */
1638#define SDR0_PFC1 0x4101
1639#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
1640#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
1641#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
1642#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
1643#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
1644#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
1645#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
1646#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
1647#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
1648#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
1649#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
1650#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
1651#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */
1652#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
1653#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
1654#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */
1655#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
1656#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
1657#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
1658#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
1659#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
1660#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */
1661#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */
1662#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */
1663
1664#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */
1665#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */
1666#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
1667#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
1668
Stefan Roese42fbddd2006-09-07 11:51:23 +0200[diff] [blame]1669/*-----------------------------------------------------------------------------
1670 | Internal SRAM
1671 +----------------------------------------------------------------------------*/
1672#define ISRAM0_DCR_BASE 0x380
1673#define isram0_sb0cr (ISRAM0_DCR_BASE+0x00) /* SRAM bank config 0*/
1674#define isram0_bear (ISRAM0_DCR_BASE+0x04) /* SRAM bus error addr reg */
1675#define isram0_besr0 (ISRAM0_DCR_BASE+0x05) /* SRAM bus error status reg 0 */
1676#define isram0_besr1 (ISRAM0_DCR_BASE+0x06) /* SRAM bus error status reg 1 */
1677#define isram0_pmeg (ISRAM0_DCR_BASE+0x07) /* SRAM power management */
1678#define isram0_cid (ISRAM0_DCR_BASE+0x08) /* SRAM bus core id reg */
1679#define isram0_revid (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */
1680#define isram0_dpc (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */
Stefan Roese363330b2005-08-04 17:09:16 +0200[diff] [blame]1681
Stefan Roese326c9712005-08-01 16:41:48 +0200[diff] [blame]1682#else
1683
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1684/*-----------------------------------------------------------------------------
1685 | Internal SRAM
1686 +----------------------------------------------------------------------------*/
1687#define ISRAM0_DCR_BASE 0x020
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]1688#define isram0_sb0cr (ISRAM0_DCR_BASE+0x00) /* SRAM bank config 0*/
1689#define isram0_sb1cr (ISRAM0_DCR_BASE+0x01) /* SRAM bank config 1*/
1690#define isram0_sb2cr (ISRAM0_DCR_BASE+0x02) /* SRAM bank config 2*/
1691#define isram0_sb3cr (ISRAM0_DCR_BASE+0x03) /* SRAM bank config 3*/
1692#define isram0_bear (ISRAM0_DCR_BASE+0x04) /* SRAM bus error addr reg */
1693#define isram0_besr0 (ISRAM0_DCR_BASE+0x05) /* SRAM bus error status reg 0 */
1694#define isram0_besr1 (ISRAM0_DCR_BASE+0x06) /* SRAM bus error status reg 1 */
1695#define isram0_pmeg (ISRAM0_DCR_BASE+0x07) /* SRAM power management */
1696#define isram0_cid (ISRAM0_DCR_BASE+0x08) /* SRAM bus core id reg */
1697#define isram0_revid (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */
1698#define isram0_dpc (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1699
1700/*-----------------------------------------------------------------------------
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]1701 | L2 Cache
1702 +----------------------------------------------------------------------------*/
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]1703#if defined (CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]1704#define L2_CACHE_BASE 0x030
1705#define l2_cache_cfg (L2_CACHE_BASE+0x00) /* L2 Cache Config */
1706#define l2_cache_cmd (L2_CACHE_BASE+0x01) /* L2 Cache Command */
1707#define l2_cache_addr (L2_CACHE_BASE+0x02) /* L2 Cache Address */
1708#define l2_cache_data (L2_CACHE_BASE+0x03) /* L2 Cache Data */
1709#define l2_cache_stat (L2_CACHE_BASE+0x04) /* L2 Cache Status */
1710#define l2_cache_cver (L2_CACHE_BASE+0x05) /* L2 Cache Revision ID */
1711#define l2_cache_snp0 (L2_CACHE_BASE+0x06) /* L2 Cache Snoop reg 0 */
1712#define l2_cache_snp1 (L2_CACHE_BASE+0x07) /* L2 Cache Snoop reg 1 */
1713
Stefan Roeseb30f2a12005-08-08 12:42:22 +0200[diff] [blame]1714#endif /* CONFIG_440GX */
1715#endif /* !CONFIG_440EP !CONFIG_440GR*/
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]1716
1717/*-----------------------------------------------------------------------------
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1718 | On-Chip Buses
1719 +----------------------------------------------------------------------------*/
1720/* TODO: as needed */
1721
1722/*-----------------------------------------------------------------------------
1723 | Clocking, Power Management and Chip Control
1724 +----------------------------------------------------------------------------*/
1725#define CNTRL_DCR_BASE 0x0b0
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]1726#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
wdenk6148e742005-04-03 20:55:38 +0000[diff] [blame]1727#define cpc0_er (CNTRL_DCR_BASE+0x00) /* CPM enable register */
1728#define cpc0_fr (CNTRL_DCR_BASE+0x01) /* CPM force register */
1729#define cpc0_sr (CNTRL_DCR_BASE+0x02) /* CPM status register */
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]1730#else
wdenk6148e742005-04-03 20:55:38 +0000[diff] [blame]1731#define cpc0_sr (CNTRL_DCR_BASE+0x00) /* CPM status register */
1732#define cpc0_er (CNTRL_DCR_BASE+0x01) /* CPM enable register */
1733#define cpc0_fr (CNTRL_DCR_BASE+0x02) /* CPM force register */
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]1734#endif
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1735
wdenk6148e742005-04-03 20:55:38 +0000[diff] [blame]1736#define cpc0_sys0 (CNTRL_DCR_BASE+0x30) /* System configuration reg 0 */
1737#define cpc0_sys1 (CNTRL_DCR_BASE+0x31) /* System configuration reg 1 */
1738#define cpc0_cust0 (CNTRL_DCR_BASE+0x32) /* Customer configuration reg 0 */
1739#define cpc0_cust1 (CNTRL_DCR_BASE+0x33) /* Customer configuration reg 1 */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1740
1741#define cpc0_strp0 (CNTRL_DCR_BASE+0x34) /* Power-on config reg 0 (RO) */
1742#define cpc0_strp1 (CNTRL_DCR_BASE+0x35) /* Power-on config reg 1 (RO) */
1743#define cpc0_strp2 (CNTRL_DCR_BASE+0x36) /* Power-on config reg 2 (RO) */
1744#define cpc0_strp3 (CNTRL_DCR_BASE+0x37) /* Power-on config reg 3 (RO) */
1745
Stefan Roesec443fe92005-11-22 13:20:42 +0100[diff] [blame]1746#define cpc0_gpio (CNTRL_DCR_BASE+0x38) /* GPIO config reg (440GP) */
1747
wdenk6148e742005-04-03 20:55:38 +0000[diff] [blame]1748#define cntrl0 (CNTRL_DCR_BASE+0x3b) /* Control 0 register */
1749#define cntrl1 (CNTRL_DCR_BASE+0x3a) /* Control 1 register */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1750
1751/*-----------------------------------------------------------------------------
1752 | Universal interrupt controller
1753 +----------------------------------------------------------------------------*/
1754#define UIC0_DCR_BASE 0xc0
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]1755#define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */
1756#define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */
1757#define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */
1758#define uic0pr (UIC0_DCR_BASE+0x4) /* UIC0 polarity */
1759#define uic0tr (UIC0_DCR_BASE+0x5) /* UIC0 triggering */
1760#define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */
1761#define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */
1762#define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1763
1764#define UIC1_DCR_BASE 0xd0
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]1765#define uic1sr (UIC1_DCR_BASE+0x0) /* UIC1 status */
1766#define uic1er (UIC1_DCR_BASE+0x2) /* UIC1 enable */
1767#define uic1cr (UIC1_DCR_BASE+0x3) /* UIC1 critical */
1768#define uic1pr (UIC1_DCR_BASE+0x4) /* UIC1 polarity */
1769#define uic1tr (UIC1_DCR_BASE+0x5) /* UIC1 triggering */
1770#define uic1msr (UIC1_DCR_BASE+0x6) /* UIC1 masked status */
1771#define uic1vr (UIC1_DCR_BASE+0x7) /* UIC1 vector */
1772#define uic1vcr (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */
1773
Stefan Roese42fbddd2006-09-07 11:51:23 +0200[diff] [blame]1774#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]1775#define UIC2_DCR_BASE 0xe0
Stefan Roese44facef2006-11-29 12:03:57 +0100[diff] [blame]1776#define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status-Read Clear */
1777#define uic2srs (UIC2_DCR_BASE+0x1) /* UIC2 status-Read Set */
1778#define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */
1779#define uic2cr (UIC2_DCR_BASE+0x3) /* UIC2 critical */
1780#define uic2pr (UIC2_DCR_BASE+0x4) /* UIC2 polarity */
1781#define uic2tr (UIC2_DCR_BASE+0x5) /* UIC2 triggering */
1782#define uic2msr (UIC2_DCR_BASE+0x6) /* UIC2 masked status */
1783#define uic2vr (UIC2_DCR_BASE+0x7) /* UIC2 vector */
1784#define uic2vcr (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]1785
1786#define UIC3_DCR_BASE 0xf0
Stefan Roese44facef2006-11-29 12:03:57 +0100[diff] [blame]1787#define uic3sr (UIC3_DCR_BASE+0x0) /* UIC3 status-Read Clear */
1788#define uic3srs (UIC3_DCR_BASE+0x1) /* UIC3 status-Read Set */
1789#define uic3er (UIC3_DCR_BASE+0x2) /* UIC3 enable */
1790#define uic3cr (UIC3_DCR_BASE+0x3) /* UIC3 critical */
1791#define uic3pr (UIC3_DCR_BASE+0x4) /* UIC3 polarity */
1792#define uic3tr (UIC3_DCR_BASE+0x5) /* UIC3 triggering */
1793#define uic3msr (UIC3_DCR_BASE+0x6) /* UIC3 masked status */
1794#define uic3vr (UIC3_DCR_BASE+0x7) /* UIC3 vector */
1795#define uic3vcr (UIC3_DCR_BASE+0x8) /* UIC3 vector configuration */
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]1796#endif /* CONFIG_440SPE */
1797
Stefan Roeseb30f2a12005-08-08 12:42:22 +0200[diff] [blame]1798#if defined(CONFIG_440GX)
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]1799#define UIC2_DCR_BASE 0x210
1800#define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status */
1801#define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */
1802#define uic2cr (UIC2_DCR_BASE+0x3) /* UIC2 critical */
1803#define uic2pr (UIC2_DCR_BASE+0x4) /* UIC2 polarity */
1804#define uic2tr (UIC2_DCR_BASE+0x5) /* UIC2 triggering */
1805#define uic2msr (UIC2_DCR_BASE+0x6) /* UIC2 masked status */
1806#define uic2vr (UIC2_DCR_BASE+0x7) /* UIC2 vector */
1807#define uic2vcr (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */
1808
1809
1810#define UIC_DCR_BASE 0x200
1811#define uicb0sr (UIC_DCR_BASE+0x0) /* UIC Base Status Register */
1812#define uicb0er (UIC_DCR_BASE+0x2) /* UIC Base enable */
1813#define uicb0cr (UIC_DCR_BASE+0x3) /* UIC Base critical */
1814#define uicb0pr (UIC_DCR_BASE+0x4) /* UIC Base polarity */
1815#define uicb0tr (UIC_DCR_BASE+0x5) /* UIC Base triggering */
1816#define uicb0msr (UIC_DCR_BASE+0x6) /* UIC Base masked status */
1817#define uicb0vr (UIC_DCR_BASE+0x7) /* UIC Base vector */
1818#define uicb0vcr (UIC_DCR_BASE+0x8) /* UIC Base vector configuration */
Stefan Roeseb30f2a12005-08-08 12:42:22 +0200[diff] [blame]1819#endif /* CONFIG_440GX */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1820
1821/* The following is for compatibility with 405 code */
1822#define uicsr uic0sr
1823#define uicer uic0er
1824#define uiccr uic0cr
1825#define uicpr uic0pr
1826#define uictr uic0tr
1827#define uicmsr uic0msr
1828#define uicvr uic0vr
1829#define uicvcr uic0vcr
1830
Niklaus Giger77cad902007-06-27 18:11:38 +0200[diff] [blame]1831#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX)
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]1832/*----------------------------------------------------------------------------+
1833| Clock / Power-on-reset DCR's.
1834+----------------------------------------------------------------------------*/
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]1835#define CPR0_CLKUPD 0x20
1836#define CPR0_CLKUPD_BSY_MASK 0x80000000
1837#define CPR0_CLKUPD_BSY_COMPLETED 0x00000000
1838#define CPR0_CLKUPD_BSY_BUSY 0x80000000
1839#define CPR0_CLKUPD_CUI_MASK 0x80000000
1840#define CPR0_CLKUPD_CUI_DISABLE 0x00000000
1841#define CPR0_CLKUPD_CUI_ENABLE 0x80000000
1842#define CPR0_CLKUPD_CUD_MASK 0x40000000
1843#define CPR0_CLKUPD_CUD_DISABLE 0x00000000
1844#define CPR0_CLKUPD_CUD_ENABLE 0x40000000
1845
1846#define CPR0_PLLC 0x40
1847#define CPR0_PLLC_RST_MASK 0x80000000
1848#define CPR0_PLLC_RST_PLLLOCKED 0x00000000
1849#define CPR0_PLLC_RST_PLLRESET 0x80000000
1850#define CPR0_PLLC_ENG_MASK 0x40000000
1851#define CPR0_PLLC_ENG_DISABLE 0x00000000
1852#define CPR0_PLLC_ENG_ENABLE 0x40000000
1853#define CPR0_PLLC_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
1854#define CPR0_PLLC_ENG_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
1855#define CPR0_PLLC_SRC_MASK 0x20000000
1856#define CPR0_PLLC_SRC_PLLOUTA 0x00000000
1857#define CPR0_PLLC_SRC_PLLOUTB 0x20000000
1858#define CPR0_PLLC_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
1859#define CPR0_PLLC_SRC_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
1860#define CPR0_PLLC_SEL_MASK 0x07000000
1861#define CPR0_PLLC_SEL_PLLOUT 0x00000000
1862#define CPR0_PLLC_SEL_CPU 0x01000000
1863#define CPR0_PLLC_SEL_EBC 0x05000000
1864#define CPR0_PLLC_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
1865#define CPR0_PLLC_SEL_DECODE(n) ((((unsigned long)(n))>>24)&0x07)
1866#define CPR0_PLLC_TUNE_MASK 0x000003FF
1867#define CPR0_PLLC_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
1868#define CPR0_PLLC_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
1869
1870#define CPR0_PLLD 0x60
1871#define CPR0_PLLD_FBDV_MASK 0x1F000000
1872#define CPR0_PLLD_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
1873#define CPR0_PLLD_FBDV_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x1F)+1)
1874#define CPR0_PLLD_FWDVA_MASK 0x000F0000
1875#define CPR0_PLLD_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<16)
1876#define CPR0_PLLD_FWDVA_DECODE(n) ((((((unsigned long)(n))>>16)-1)&0x0F)+1)
1877#define CPR0_PLLD_FWDVB_MASK 0x00000700
1878#define CPR0_PLLD_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<8)
1879#define CPR0_PLLD_FWDVB_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x07)+1)
1880#define CPR0_PLLD_LFBDV_MASK 0x0000003F
1881#define CPR0_PLLD_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0)
1882#define CPR0_PLLD_LFBDV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x3F)+1)
1883
1884#define CPR0_PRIMAD 0x80
1885#define CPR0_PRIMAD_PRADV0_MASK 0x07000000
1886#define CPR0_PRIMAD_PRADV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
1887#define CPR0_PRIMAD_PRADV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1)
1888
1889#define CPR0_PRIMBD 0xA0
1890#define CPR0_PRIMBD_PRBDV0_MASK 0x07000000
1891#define CPR0_PRIMBD_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
1892#define CPR0_PRIMBD_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1)
1893
1894#define CPR0_OPBD 0xC0
1895#define CPR0_OPBD_OPBDV0_MASK 0x03000000
1896#define CPR0_OPBD_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
1897#define CPR0_OPBD_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
1898
1899#define CPR0_PERD 0xE0
Niklaus Giger77cad902007-06-27 18:11:38 +0200[diff] [blame]1900#if !defined(CONFIG_440EPX)
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]1901#define CPR0_PERD_PERDV0_MASK 0x03000000
1902#define CPR0_PERD_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
1903#define CPR0_PERD_PERDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
Niklaus Giger77cad902007-06-27 18:11:38 +0200[diff] [blame]1904#endif
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]1905
1906#define CPR0_MALD 0x100
1907#define CPR0_MALD_MALDV0_MASK 0x03000000
1908#define CPR0_MALD_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
1909#define CPR0_MALD_MALDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
1910
1911#define CPR0_ICFG 0x140
1912#define CPR0_ICFG_RLI_MASK 0x80000000
1913#define CPR0_ICFG_RLI_RESETCPR 0x00000000
1914#define CPR0_ICFG_RLI_PRESERVECPR 0x80000000
1915#define CPR0_ICFG_ICS_MASK 0x00000007
1916#define CPR0_ICFG_ICS_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0)
1917#define CPR0_ICFG_ICS_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x3F)+1)
1918
1919/************************/
1920/* IIC defines */
1921/************************/
1922#define IIC0_MMIO_BASE 0xA0000400
1923#define IIC1_MMIO_BASE 0xA0000500
1924
1925#endif /* CONFIG_440SP */
1926
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1927/*-----------------------------------------------------------------------------
1928 | DMA
1929 +----------------------------------------------------------------------------*/
1930#define DMA_DCR_BASE 0x100
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]1931#define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */
1932#define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */
1933#define dmasah0 (DMA_DCR_BASE+0x02) /* DMA source address high 0 */
1934#define dmasal0 (DMA_DCR_BASE+0x03) /* DMA source address low 0 */
1935#define dmadah0 (DMA_DCR_BASE+0x04) /* DMA destination address high 0 */
1936#define dmadal0 (DMA_DCR_BASE+0x05) /* DMA destination address low 0 */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1937#define dmasgh0 (DMA_DCR_BASE+0x06) /* DMA scatter/gather desc addr high 0 */
1938#define dmasgl0 (DMA_DCR_BASE+0x07) /* DMA scatter/gather desc addr low 0 */
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]1939#define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */
1940#define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */
1941#define dmasah1 (DMA_DCR_BASE+0x0a) /* DMA source address high 1 */
1942#define dmasal1 (DMA_DCR_BASE+0x0b) /* DMA source address low 1 */
1943#define dmadah1 (DMA_DCR_BASE+0x0c) /* DMA destination address high 1 */
1944#define dmadal1 (DMA_DCR_BASE+0x0d) /* DMA destination address low 1 */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1945#define dmasgh1 (DMA_DCR_BASE+0x0e) /* DMA scatter/gather desc addr high 1 */
1946#define dmasgl1 (DMA_DCR_BASE+0x0f) /* DMA scatter/gather desc addr low 1 */
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]1947#define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */
1948#define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */
1949#define dmasah2 (DMA_DCR_BASE+0x12) /* DMA source address high 2 */
1950#define dmasal2 (DMA_DCR_BASE+0x13) /* DMA source address low 2 */
1951#define dmadah2 (DMA_DCR_BASE+0x14) /* DMA destination address high 2 */
1952#define dmadal2 (DMA_DCR_BASE+0x15) /* DMA destination address low 2 */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1953#define dmasgh2 (DMA_DCR_BASE+0x16) /* DMA scatter/gather desc addr high 2 */
1954#define dmasgl2 (DMA_DCR_BASE+0x17) /* DMA scatter/gather desc addr low 2 */
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]1955#define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 2 */
1956#define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 2 */
1957#define dmasah3 (DMA_DCR_BASE+0x1a) /* DMA source address high 2 */
1958#define dmasal3 (DMA_DCR_BASE+0x1b) /* DMA source address low 2 */
1959#define dmadah3 (DMA_DCR_BASE+0x1c) /* DMA destination address high 2 */
1960#define dmadal3 (DMA_DCR_BASE+0x1d) /* DMA destination address low 2 */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1961#define dmasgh3 (DMA_DCR_BASE+0x1e) /* DMA scatter/gather desc addr high 2 */
1962#define dmasgl3 (DMA_DCR_BASE+0x1f) /* DMA scatter/gather desc addr low 2 */
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]1963#define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */
1964#define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */
1965#define dmaslp (DMA_DCR_BASE+0x25) /* DMA sleep mode register */
1966#define dmapol (DMA_DCR_BASE+0x26) /* DMA polarity configuration register */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1967
1968/*-----------------------------------------------------------------------------
1969 | Memory Access Layer
1970 +----------------------------------------------------------------------------*/
1971#define MAL_DCR_BASE 0x180
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]1972#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */
1973#define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */
1974#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */
1975#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */
1976#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1977#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */
1978#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]1979#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */
1980#define maltxtattrr (MAL_DCR_BASE+0x08) /* TX PLB attribute reg */
1981#define maltxbattr (MAL_DCR_BASE+0x09) /* TX descriptor base addr reg */
1982#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1983#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */
1984#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]1985#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */
1986#define malrxtattrr (MAL_DCR_BASE+0x14) /* RX PLB attribute reg */
1987#define malrxbattr (MAL_DCR_BASE+0x15) /* RX descriptor base addr reg */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1988#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */
1989#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]1990#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */
1991#define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table pointer reg */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1992#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */
1993#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */
Stefan Roeseb30f2a12005-08-08 12:42:22 +0200[diff] [blame]1994#if defined(CONFIG_440GX)
Wolfgang Denk2e58f9f2006-09-20 23:47:49 +0200[diff] [blame]1995#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table pointer reg */
1996#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table pointer reg */
Stefan Roeseb30f2a12005-08-08 12:42:22 +0200[diff] [blame]1997#endif /* CONFIG_440GX */
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]1998#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
1999#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */
Stefan Roeseb30f2a12005-08-08 12:42:22 +0200[diff] [blame]2000#if defined(CONFIG_440GX)
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]2001#define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */
2002#define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */
Stefan Roeseb30f2a12005-08-08 12:42:22 +0200[diff] [blame]2003#endif /* CONFIG_440GX */
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]2004
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]2005
2006/*---------------------------------------------------------------------------+
2007| Universal interrupt controller 0 interrupts (UIC0)
2008+---------------------------------------------------------------------------*/
Stefan Roese99644742005-11-29 18:18:21 +0100[diff] [blame]2009#if defined(CONFIG_440SP)
2010#define UIC_U0 0x80000000 /* UART 0 */
2011#define UIC_U1 0x40000000 /* UART 1 */
2012#define UIC_IIC0 0x20000000 /* IIC */
2013#define UIC_IIC1 0x10000000 /* IIC */
2014#define UIC_PIM 0x08000000 /* PCI0 inbound message */
2015#define UIC_PCRW 0x04000000 /* PCI0 command write register */
2016#define UIC_PPM 0x02000000 /* PCI0 power management */
2017#define UIC_PVPD 0x01000000 /* PCI0 VPD Access */
2018#define UIC_MSI0 0x00800000 /* PCI0 MSI level 0 */
2019#define UIC_P1IM 0x00400000 /* PCI1 Inbound Message */
2020#define UIC_P1CRW 0x00200000 /* PCI1 command write register */
2021#define UIC_P1PM 0x00100000 /* PCI1 power management */
2022#define UIC_P1VPD 0x00080000 /* PCI1 VPD Access */
2023#define UIC_P1MSI0 0x00040000 /* PCI1 MSI level 0 */
2024#define UIC_P2IM 0x00020000 /* PCI2 inbound message */
2025#define UIC_P2CRW 0x00010000 /* PCI2 command register write */
2026#define UIC_P2PM 0x00008000 /* PCI2 power management */
2027#define UIC_P2VPD 0x00004000 /* PCI2 VPD access */
2028#define UIC_P2MSI0 0x00002000 /* PCI2 MSI level 0 */
2029#define UIC_D0CPF 0x00001000 /* DMA0 command pointer */
2030#define UIC_D0CSF 0x00000800 /* DMA0 command status */
2031#define UIC_D1CPF 0x00000400 /* DMA1 command pointer */
2032#define UIC_D1CSF 0x00000200 /* DMA1 command status */
2033#define UIC_I2OID 0x00000100 /* I2O inbound doorbell */
2034#define UIC_I2OPLF 0x00000080 /* I2O inbound post list */
2035#define UIC_I2O0LL 0x00000040 /* I2O0 low latency PLB write */
2036#define UIC_I2O1LL 0x00000020 /* I2O1 low latency PLB write */
2037#define UIC_I2O0HB 0x00000010 /* I2O0 high bandwidth PLB write */
2038#define UIC_I2O1HB 0x00000008 /* I2O1 high bandwidth PLB write */
2039#define UIC_GPTCT 0x00000004 /* GPT count timer */
2040#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
2041#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]2042#elif defined(CONFIG_440GX) || defined(CONFIG_440EP)
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]2043#define UIC_U0 0x80000000 /* UART 0 */
2044#define UIC_U1 0x40000000 /* UART 1 */
2045#define UIC_IIC0 0x20000000 /* IIC */
2046#define UIC_IIC1 0x10000000 /* IIC */
2047#define UIC_PIM 0x08000000 /* PCI inbound message */
2048#define UIC_PCRW 0x04000000 /* PCI command register write */
2049#define UIC_PPM 0x02000000 /* PCI power management */
2050#define UIC_MSI0 0x01000000 /* PCI MSI level 0 */
2051#define UIC_MSI1 0x00800000 /* PCI MSI level 1 */
2052#define UIC_MSI2 0x00400000 /* PCI MSI level 2 */
2053#define UIC_MTE 0x00200000 /* MAL TXEOB */
2054#define UIC_MRE 0x00100000 /* MAL RXEOB */
2055#define UIC_D0 0x00080000 /* DMA channel 0 */
2056#define UIC_D1 0x00040000 /* DMA channel 1 */
2057#define UIC_D2 0x00020000 /* DMA channel 2 */
2058#define UIC_D3 0x00010000 /* DMA channel 3 */
2059#define UIC_RSVD0 0x00008000 /* Reserved */
2060#define UIC_RSVD1 0x00004000 /* Reserved */
2061#define UIC_CT0 0x00002000 /* GPT compare timer 0 */
2062#define UIC_CT1 0x00001000 /* GPT compare timer 1 */
2063#define UIC_CT2 0x00000800 /* GPT compare timer 2 */
2064#define UIC_CT3 0x00000400 /* GPT compare timer 3 */
2065#define UIC_CT4 0x00000200 /* GPT compare timer 4 */
2066#define UIC_EIR0 0x00000100 /* External interrupt 0 */
2067#define UIC_EIR1 0x00000080 /* External interrupt 1 */
2068#define UIC_EIR2 0x00000040 /* External interrupt 2 */
2069#define UIC_EIR3 0x00000020 /* External interrupt 3 */
2070#define UIC_EIR4 0x00000010 /* External interrupt 4 */
2071#define UIC_EIR5 0x00000008 /* External interrupt 5 */
2072#define UIC_EIR6 0x00000004 /* External interrupt 6 */
2073#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
2074#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
Stefan Roese42fbddd2006-09-07 11:51:23 +0200[diff] [blame]2075
2076#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
2077
2078#define UIC_U0 0x80000000 /* UART 0 */
2079#define UIC_U1 0x40000000 /* UART 1 */
2080#define UIC_IIC0 0x20000000 /* IIC */
2081#define UIC_KRD 0x10000000 /* Kasumi Ready for data */
2082#define UIC_KDA 0x08000000 /* Kasumi Data Available */
2083#define UIC_PCRW 0x04000000 /* PCI command register write */
2084#define UIC_PPM 0x02000000 /* PCI power management */
2085#define UIC_IIC1 0x01000000 /* IIC */
2086#define UIC_SPI 0x00800000 /* SPI */
2087#define UIC_EPCISER 0x00400000 /* External PCI SERR */
2088#define UIC_MTE 0x00200000 /* MAL TXEOB */
2089#define UIC_MRE 0x00100000 /* MAL RXEOB */
2090#define UIC_D0 0x00080000 /* DMA channel 0 */
2091#define UIC_D1 0x00040000 /* DMA channel 1 */
2092#define UIC_D2 0x00020000 /* DMA channel 2 */
2093#define UIC_D3 0x00010000 /* DMA channel 3 */
2094#define UIC_UD0 0x00008000 /* UDMA irq 0 */
2095#define UIC_UD1 0x00004000 /* UDMA irq 1 */
2096#define UIC_UD2 0x00002000 /* UDMA irq 2 */
2097#define UIC_UD3 0x00001000 /* UDMA irq 3 */
2098#define UIC_HSB2D 0x00000800 /* USB2.0 Device */
2099#define UIC_OHCI1 0x00000400 /* USB2.0 Host OHCI irq 1 */
2100#define UIC_OHCI2 0x00000200 /* USB2.0 Host OHCI irq 2 */
2101#define UIC_EIP94 0x00000100 /* Security EIP94 */
2102#define UIC_ETH0 0x00000080 /* Emac 0 */
2103#define UIC_ETH1 0x00000040 /* Emac 1 */
2104#define UIC_EHCI 0x00000020 /* USB2.0 Host EHCI */
2105#define UIC_EIR4 0x00000010 /* External interrupt 4 */
2106#define UIC_UIC2NC 0x00000008 /* UIC2 non-critical interrupt */
2107#define UIC_UIC2C 0x00000004 /* UIC2 critical interrupt */
2108#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
2109#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
2110
2111/* For compatibility with 405 code */
2112#define UIC_MAL_TXEOB UIC_MTE
2113#define UIC_MAL_RXEOB UIC_MRE
2114
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]2115#elif !defined(CONFIG_440SPE)
2116#define UIC_U0 0x80000000 /* UART 0 */
2117#define UIC_U1 0x40000000 /* UART 1 */
2118#define UIC_IIC0 0x20000000 /* IIC */
2119#define UIC_IIC1 0x10000000 /* IIC */
2120#define UIC_PIM 0x08000000 /* PCI inbound message */
2121#define UIC_PCRW 0x04000000 /* PCI command register write */
2122#define UIC_PPM 0x02000000 /* PCI power management */
2123#define UIC_MSI0 0x01000000 /* PCI MSI level 0 */
2124#define UIC_MSI1 0x00800000 /* PCI MSI level 1 */
2125#define UIC_MSI2 0x00400000 /* PCI MSI level 2 */
2126#define UIC_MTE 0x00200000 /* MAL TXEOB */
2127#define UIC_MRE 0x00100000 /* MAL RXEOB */
2128#define UIC_D0 0x00080000 /* DMA channel 0 */
2129#define UIC_D1 0x00040000 /* DMA channel 1 */
2130#define UIC_D2 0x00020000 /* DMA channel 2 */
2131#define UIC_D3 0x00010000 /* DMA channel 3 */
2132#define UIC_RSVD0 0x00008000 /* Reserved */
2133#define UIC_RSVD1 0x00004000 /* Reserved */
2134#define UIC_CT0 0x00002000 /* GPT compare timer 0 */
2135#define UIC_CT1 0x00001000 /* GPT compare timer 1 */
2136#define UIC_CT2 0x00000800 /* GPT compare timer 2 */
2137#define UIC_CT3 0x00000400 /* GPT compare timer 3 */
2138#define UIC_CT4 0x00000200 /* GPT compare timer 4 */
2139#define UIC_EIR0 0x00000100 /* External interrupt 0 */
2140#define UIC_EIR1 0x00000080 /* External interrupt 1 */
2141#define UIC_EIR2 0x00000040 /* External interrupt 2 */
2142#define UIC_EIR3 0x00000020 /* External interrupt 3 */
2143#define UIC_EIR4 0x00000010 /* External interrupt 4 */
2144#define UIC_EIR5 0x00000008 /* External interrupt 5 */
2145#define UIC_EIR6 0x00000004 /* External interrupt 6 */
2146#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
2147#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
2148#endif /* CONFIG_440GX */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]2149
2150/* For compatibility with 405 code */
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]2151#define UIC_MAL_TXEOB UIC_MTE
2152#define UIC_MAL_RXEOB UIC_MRE
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]2153
2154/*---------------------------------------------------------------------------+
2155| Universal interrupt controller 1 interrupts (UIC1)
2156+---------------------------------------------------------------------------*/
Stefan Roese99644742005-11-29 18:18:21 +0100[diff] [blame]2157#if defined(CONFIG_440SP)
2158#define UIC_EIR0 0x80000000 /* External interrupt 0 */
2159#define UIC_MS 0x40000000 /* MAL SERR */
2160#define UIC_MTDE 0x20000000 /* MAL TXDE */
2161#define UIC_MRDE 0x10000000 /* MAL RXDE */
2162#define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */
2163#define UIC_EBCO 0x04000000 /* EBCO interrupt status */
2164#define UIC_MTE 0x02000000 /* MAL TXEOB */
2165#define UIC_MRE 0x01000000 /* MAL RXEOB */
2166#define UIC_P0MSI1 0x00800000 /* PCI0 MSI level 1 */
2167#define UIC_P1MSI1 0x00400000 /* PCI1 MSI level 1 */
2168#define UIC_P2MSI1 0x00200000 /* PCI2 MSI level 1 */
2169#define UIC_L2C 0x00100000 /* L2 cache */
2170#define UIC_CT0 0x00080000 /* GPT compare timer 0 */
2171#define UIC_CT1 0x00040000 /* GPT compare timer 1 */
2172#define UIC_CT2 0x00020000 /* GPT compare timer 2 */
2173#define UIC_CT3 0x00010000 /* GPT compare timer 3 */
2174#define UIC_CT4 0x00008000 /* GPT compare timer 4 */
2175#define UIC_EIR1 0x00004000 /* External interrupt 1 */
2176#define UIC_EIR2 0x00002000 /* External interrupt 2 */
2177#define UIC_EIR3 0x00001000 /* External interrupt 3 */
2178#define UIC_EIR4 0x00000800 /* External interrupt 4 */
2179#define UIC_EIR5 0x00000400 /* External interrupt 5 */
2180#define UIC_DMAE 0x00000200 /* DMA error */
2181#define UIC_I2OE 0x00000100 /* I2O error */
2182#define UIC_SRE 0x00000080 /* Serial ROM error */
2183#define UIC_P0AE 0x00000040 /* PCI0 asynchronous error */
2184#define UIC_P1AE 0x00000020 /* PCI1 asynchronous error */
2185#define UIC_P2AE 0x00000010 /* PCI2 asynchronous error */
2186#define UIC_ETH0 0x00000008 /* Ethernet 0 */
2187#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
2188#define UIC_ETH1 0x00000002 /* Reserved */
2189#define UIC_XOR 0x00000001 /* XOR */
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]2190#elif defined(CONFIG_440GX) || defined(CONFIG_440EP)
2191#define UIC_MS 0x80000000 /* MAL SERR */
2192#define UIC_MTDE 0x40000000 /* MAL TXDE */
2193#define UIC_MRDE 0x20000000 /* MAL RXDE */
2194#define UIC_DEUE 0x10000000 /* DDR SDRAM ECC uncorrectible error*/
2195#define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */
2196#define UIC_EBCO 0x04000000 /* EBCO interrupt status */
2197#define UIC_EBMI 0x02000000 /* EBMI interrupt status */
2198#define UIC_OPB 0x01000000 /* OPB to PLB bridge interrupt stat */
2199#define UIC_MSI3 0x00800000 /* PCI MSI level 3 */
2200#define UIC_MSI4 0x00400000 /* PCI MSI level 4 */
2201#define UIC_MSI5 0x00200000 /* PCI MSI level 5 */
2202#define UIC_MSI6 0x00100000 /* PCI MSI level 6 */
2203#define UIC_MSI7 0x00080000 /* PCI MSI level 7 */
2204#define UIC_MSI8 0x00040000 /* PCI MSI level 8 */
2205#define UIC_MSI9 0x00020000 /* PCI MSI level 9 */
2206#define UIC_MSI10 0x00010000 /* PCI MSI level 10 */
2207#define UIC_MSI11 0x00008000 /* PCI MSI level 11 */
2208#define UIC_PPMI 0x00004000 /* PPM interrupt status */
2209#define UIC_EIR7 0x00002000 /* External interrupt 7 */
2210#define UIC_EIR8 0x00001000 /* External interrupt 8 */
2211#define UIC_EIR9 0x00000800 /* External interrupt 9 */
2212#define UIC_EIR10 0x00000400 /* External interrupt 10 */
2213#define UIC_EIR11 0x00000200 /* External interrupt 11 */
2214#define UIC_EIR12 0x00000100 /* External interrupt 12 */
2215#define UIC_SRE 0x00000080 /* Serial ROM error */
2216#define UIC_RSVD2 0x00000040 /* Reserved */
2217#define UIC_RSVD3 0x00000020 /* Reserved */
2218#define UIC_PAE 0x00000010 /* PCI asynchronous error */
2219#define UIC_ETH0 0x00000008 /* Ethernet 0 */
2220#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
2221#define UIC_ETH1 0x00000002 /* Ethernet 1 */
2222#define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */
Stefan Roese42fbddd2006-09-07 11:51:23 +0200[diff] [blame]2223
2224#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
2225
2226#define UIC_MS 0x80000000 /* MAL SERR */
2227#define UIC_MTDE 0x40000000 /* MAL TXDE */
2228#define UIC_MRDE 0x20000000 /* MAL RXDE */
2229#define UIC_U2 0x10000000 /* UART 2 */
2230#define UIC_U3 0x08000000 /* UART 3 */
2231#define UIC_EBCO 0x04000000 /* EBCO interrupt status */
2232#define UIC_NDFC 0x02000000 /* NDFC */
2233#define UIC_KSLE 0x01000000 /* KASUMI slave error */
2234#define UIC_CT5 0x00800000 /* GPT compare timer 5 */
2235#define UIC_CT6 0x00400000 /* GPT compare timer 6 */
2236#define UIC_PLB34I0 0x00200000 /* PLB3X4X MIRQ0 */
2237#define UIC_PLB34I1 0x00100000 /* PLB3X4X MIRQ1 */
2238#define UIC_PLB34I2 0x00080000 /* PLB3X4X MIRQ2 */
2239#define UIC_PLB34I3 0x00040000 /* PLB3X4X MIRQ3 */
2240#define UIC_PLB34I4 0x00020000 /* PLB3X4X MIRQ4 */
2241#define UIC_PLB34I5 0x00010000 /* PLB3X4X MIRQ5 */
2242#define UIC_CT0 0x00008000 /* GPT compare timer 0 */
2243#define UIC_CT1 0x00004000 /* GPT compare timer 1 */
2244#define UIC_EIR7 0x00002000 /* External interrupt 7 */
2245#define UIC_EIR8 0x00001000 /* External interrupt 8 */
2246#define UIC_EIR9 0x00000800 /* External interrupt 9 */
2247#define UIC_CT2 0x00000400 /* GPT compare timer 2 */
2248#define UIC_CT3 0x00000200 /* GPT compare timer 3 */
2249#define UIC_CT4 0x00000100 /* GPT compare timer 4 */
2250#define UIC_SRE 0x00000080 /* Serial ROM error */
2251#define UIC_GPTDC 0x00000040 /* GPT decrementer pulse */
2252#define UIC_RSVD0 0x00000020 /* Reserved */
2253#define UIC_EPCIPER 0x00000010 /* External PCI PERR */
2254#define UIC_EIR0 0x00000008 /* External interrupt 0 */
2255#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
2256#define UIC_EIR1 0x00000002 /* External interrupt 1 */
2257#define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */
2258
2259/* For compatibility with 405 code */
2260#define UIC_MAL_SERR UIC_MS
2261#define UIC_MAL_TXDE UIC_MTDE
2262#define UIC_MAL_RXDE UIC_MRDE
2263#define UIC_ENET UIC_ETH0
2264
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]2265#elif !defined(CONFIG_440SPE)
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]2266#define UIC_MS 0x80000000 /* MAL SERR */
2267#define UIC_MTDE 0x40000000 /* MAL TXDE */
2268#define UIC_MRDE 0x20000000 /* MAL RXDE */
2269#define UIC_DEUE 0x10000000 /* DDR SDRAM ECC uncorrectible error*/
2270#define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */
2271#define UIC_EBCO 0x04000000 /* EBCO interrupt status */
2272#define UIC_EBMI 0x02000000 /* EBMI interrupt status */
2273#define UIC_OPB 0x01000000 /* OPB to PLB bridge interrupt stat */
2274#define UIC_MSI3 0x00800000 /* PCI MSI level 3 */
2275#define UIC_MSI4 0x00400000 /* PCI MSI level 4 */
2276#define UIC_MSI5 0x00200000 /* PCI MSI level 5 */
2277#define UIC_MSI6 0x00100000 /* PCI MSI level 6 */
2278#define UIC_MSI7 0x00080000 /* PCI MSI level 7 */
2279#define UIC_MSI8 0x00040000 /* PCI MSI level 8 */
2280#define UIC_MSI9 0x00020000 /* PCI MSI level 9 */
2281#define UIC_MSI10 0x00010000 /* PCI MSI level 10 */
2282#define UIC_MSI11 0x00008000 /* PCI MSI level 11 */
2283#define UIC_PPMI 0x00004000 /* PPM interrupt status */
2284#define UIC_EIR7 0x00002000 /* External interrupt 7 */
2285#define UIC_EIR8 0x00001000 /* External interrupt 8 */
2286#define UIC_EIR9 0x00000800 /* External interrupt 9 */
2287#define UIC_EIR10 0x00000400 /* External interrupt 10 */
2288#define UIC_EIR11 0x00000200 /* External interrupt 11 */
2289#define UIC_EIR12 0x00000100 /* External interrupt 12 */
2290#define UIC_SRE 0x00000080 /* Serial ROM error */
2291#define UIC_RSVD2 0x00000040 /* Reserved */
2292#define UIC_RSVD3 0x00000020 /* Reserved */
2293#define UIC_PAE 0x00000010 /* PCI asynchronous error */
2294#define UIC_ETH0 0x00000008 /* Ethernet 0 */
2295#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
2296#define UIC_ETH1 0x00000002 /* Ethernet 1 */
2297#define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */
Stefan Roese99644742005-11-29 18:18:21 +0100[diff] [blame]2298#endif /* CONFIG_440SP */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]2299
2300/* For compatibility with 405 code */
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]2301#define UIC_MAL_SERR UIC_MS
2302#define UIC_MAL_TXDE UIC_MTDE
2303#define UIC_MAL_RXDE UIC_MRDE
2304#define UIC_ENET UIC_ETH0
2305
2306/*---------------------------------------------------------------------------+
2307| Universal interrupt controller 2 interrupts (UIC2)
2308+---------------------------------------------------------------------------*/
Stefan Roeseb30f2a12005-08-08 12:42:22 +0200[diff] [blame]2309#if defined(CONFIG_440GX)
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]2310#define UIC_ETH2 0x80000000 /* Ethernet 2 */
2311#define UIC_EWU2 0x40000000 /* Ethernet 2 wakeup */
2312#define UIC_ETH3 0x20000000 /* Ethernet 3 */
2313#define UIC_EWU3 0x10000000 /* Ethernet 3 wakeup */
2314#define UIC_TAH0 0x08000000 /* TAH 0 */
2315#define UIC_TAH1 0x04000000 /* TAH 1 */
2316#define UIC_IMUOBFQ 0x02000000 /* IMU outbound free queue */
2317#define UIC_IMUIBPQ 0x01000000 /* IMU inbound post queue */
2318#define UIC_IMUIRQDB 0x00800000 /* IMU irq doorbell */
2319#define UIC_IMUIBDB 0x00400000 /* IMU inbound doorbell */
2320#define UIC_IMUMSG0 0x00200000 /* IMU inbound message 0 */
2321#define UIC_IMUMSG1 0x00100000 /* IMU inbound message 1 */
2322#define UIC_IMUTO 0x00080000 /* IMU timeout */
2323#define UIC_MSI12 0x00040000 /* PCI MSI level 12 */
2324#define UIC_MSI13 0x00020000 /* PCI MSI level 13 */
2325#define UIC_MSI14 0x00010000 /* PCI MSI level 14 */
2326#define UIC_MSI15 0x00008000 /* PCI MSI level 15 */
2327#define UIC_EIR13 0x00004000 /* External interrupt 13 */
2328#define UIC_EIR14 0x00002000 /* External interrupt 14 */
2329#define UIC_EIR15 0x00001000 /* External interrupt 15 */
2330#define UIC_EIR16 0x00000800 /* External interrupt 16 */
2331#define UIC_EIR17 0x00000400 /* External interrupt 17 */
2332#define UIC_PCIVPD 0x00000200 /* PCI VPD */
2333#define UIC_L2C 0x00000100 /* L2 Cache */
2334#define UIC_ETH2PCS 0x00000080 /* Ethernet 2 PCS */
2335#define UIC_ETH3PCS 0x00000040 /* Ethernet 3 PCS */
2336#define UIC_RSVD26 0x00000020 /* Reserved */
2337#define UIC_RSVD27 0x00000010 /* Reserved */
2338#define UIC_RSVD28 0x00000008 /* Reserved */
2339#define UIC_RSVD29 0x00000004 /* Reserved */
2340#define UIC_RSVD30 0x00000002 /* Reserved */
2341#define UIC_RSVD31 0x00000001 /* Reserved */
Stefan Roese42fbddd2006-09-07 11:51:23 +0200[diff] [blame]2342
2343#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* UIC2 */
2344
2345#define UIC_EIR5 0x80000000 /* External interrupt 5 */
2346#define UIC_EIR6 0x40000000 /* External interrupt 6 */
2347#define UIC_OPB 0x20000000 /* OPB to PLB bridge interrupt stat */
2348#define UIC_EIR2 0x10000000 /* External interrupt 2 */
2349#define UIC_EIR3 0x08000000 /* External interrupt 3 */
2350#define UIC_DDR2 0x04000000 /* DDR2 sdram */
2351#define UIC_MCTX0 0x02000000 /* MAl intp coalescence TX0 */
2352#define UIC_MCTX1 0x01000000 /* MAl intp coalescence TX1 */
2353#define UIC_MCTR0 0x00800000 /* MAl intp coalescence TR0 */
2354#define UIC_MCTR1 0x00400000 /* MAl intp coalescence TR1 */
2355
Stefan Roeseb30f2a12005-08-08 12:42:22 +0200[diff] [blame]2356#endif /* CONFIG_440GX */
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]2357
2358/*---------------------------------------------------------------------------+
2359| Universal interrupt controller Base 0 interrupts (UICB0)
2360+---------------------------------------------------------------------------*/
Stefan Roeseb30f2a12005-08-08 12:42:22 +0200[diff] [blame]2361#if defined(CONFIG_440GX)
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]2362#define UICB0_UIC0CI 0x80000000 /* UIC0 Critical Interrupt */
2363#define UICB0_UIC0NCI 0x40000000 /* UIC0 Noncritical Interrupt */
2364#define UICB0_UIC1CI 0x20000000 /* UIC1 Critical Interrupt */
2365#define UICB0_UIC1NCI 0x10000000 /* UIC1 Noncritical Interrupt */
2366#define UICB0_UIC2CI 0x08000000 /* UIC2 Critical Interrupt */
2367#define UICB0_UIC2NCI 0x04000000 /* UIC2 Noncritical Interrupt */
2368
2369#define UICB0_ALL (UICB0_UIC0CI | UICB0_UIC0NCI | UICB0_UIC1CI | \
2370 UICB0_UIC1NCI | UICB0_UIC2CI | UICB0_UIC2NCI)
Stefan Roese42fbddd2006-09-07 11:51:23 +0200[diff] [blame]2371
2372#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
2373
2374#define UICB0_UIC1CI 0x00000000 /* UIC1 Critical Interrupt */
2375#define UICB0_UIC1NCI 0x00000000 /* UIC1 Noncritical Interrupt */
2376#define UICB0_UIC2CI 0x00000000 /* UIC2 Critical Interrupt */
2377#define UICB0_UIC2NCI 0x00000000 /* UIC2 Noncritical Interrupt */
2378
2379#define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | \
2380 UICB0_UIC1CI | UICB0_UIC2NCI)
2381
Marian Balakowicz6900eeb2006-06-30 18:35:04 +0200[diff] [blame]2382#endif /* CONFIG_440GX */
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]2383/*---------------------------------------------------------------------------+
2384| Universal interrupt controller interrupts
2385+---------------------------------------------------------------------------*/
2386#if defined(CONFIG_440SPE)
2387/*#define UICB0_UIC0CI 0x80000000*/ /* UIC0 Critical Interrupt */
2388/*#define UICB0_UIC0NCI 0x40000000*/ /* UIC0 Noncritical Interrupt */
2389#define UICB0_UIC1CI 0x00000002 /* UIC1 Critical Interrupt */
2390#define UICB0_UIC1NCI 0x00000001 /* UIC1 Noncritical Interrupt */
2391#define UICB0_UIC2CI 0x00200000 /* UIC2 Critical Interrupt */
2392#define UICB0_UIC2NCI 0x00100000 /* UIC2 Noncritical Interrupt */
2393#define UICB0_UIC3CI 0x00008000 /* UIC3 Critical Interrupt */
2394#define UICB0_UIC3NCI 0x00004000 /* UIC3 Noncritical Interrupt */
2395
2396#define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | UICB0_UIC2CI | \
2397 UICB0_UIC2NCI | UICB0_UIC3CI | UICB0_UIC3NCI)
2398/*---------------------------------------------------------------------------+
2399| Universal interrupt controller 0 interrupts (UIC0)
2400+---------------------------------------------------------------------------*/
2401#define UIC_U0 0x80000000 /* UART 0 */
2402#define UIC_U1 0x40000000 /* UART 1 */
2403#define UIC_IIC0 0x20000000 /* IIC */
2404#define UIC_IIC1 0x10000000 /* IIC */
2405#define UIC_PIM 0x08000000 /* PCI inbound message */
2406#define UIC_PCRW 0x04000000 /* PCI command register write */
2407#define UIC_PPM 0x02000000 /* PCI power management */
2408#define UIC_PVPDA 0x01000000 /* PCIx 0 vpd access */
2409#define UIC_MSI0 0x00800000 /* PCIx MSI level 0 */
2410#define UIC_EIR15 0x00400000 /* External intp 15 */
2411#define UIC_PEMSI0 0x00080000 /* PCIe MSI level 0 */
2412#define UIC_PEMSI1 0x00040000 /* PCIe MSI level 1 */
2413#define UIC_PEMSI2 0x00020000 /* PCIe MSI level 2 */
2414#define UIC_PEMSI3 0x00010000 /* PCIe MSI level 3 */
2415#define UIC_EIR14 0x00002000 /* External interrupt 14 */
2416#define UIC_D0CPFF 0x00001000 /* DMA0 cp fifo full */
2417#define UIC_D0CSNS 0x00000800 /* DMA0 cs fifo needs service */
2418#define UIC_D1CPFF 0x00000400 /* DMA1 cp fifo full */
2419#define UIC_D1CSNS 0x00000200 /* DMA1 cs fifo needs service */
2420#define UIC_I2OID 0x00000100 /* I2O inbound door bell */
2421#define UIC_I2OLNE 0x00000080 /* I2O Inbound Post List FIFO Not Empty */
2422#define UIC_I20R0LL 0x00000040 /* I2O Region 0 Low Latency PLB Write */
2423#define UIC_I2OR1LL 0x00000020 /* I2O Region 1 Low Latency PLB Write */
2424#define UIC_I20R0HB 0x00000010 /* I2O Region 0 High Bandwidth PLB Write */
2425#define UIC_I2OR1HB 0x00000008 /* I2O Region 1 High Bandwidth PLB Write */
2426#define UIC_CPTCNT 0x00000004 /* GPT Count Timer */
2427/*---------------------------------------------------------------------------+
2428| Universal interrupt controller 1 interrupts (UIC1)
2429+---------------------------------------------------------------------------*/
2430#define UIC_EIR13 0x80000000 /* externei intp 13 */
2431#define UIC_MS 0x40000000 /* MAL SERR */
2432#define UIC_MTDE 0x20000000 /* MAL TXDE */
2433#define UIC_MRDE 0x10000000 /* MAL RXDE */
2434#define UIC_DEUE 0x08000000 /* DDR SDRAM ECC correct/uncorrectable error */
2435#define UIC_EBCO 0x04000000 /* EBCO interrupt status */
2436#define UIC_MTE 0x02000000 /* MAL TXEOB */
2437#define UIC_MRE 0x01000000 /* MAL RXEOB */
2438#define UIC_MSI1 0x00800000 /* PCI MSI level 1 */
2439#define UIC_MSI2 0x00400000 /* PCI MSI level 2 */
2440#define UIC_MSI3 0x00200000 /* PCI MSI level 3 */
2441#define UIC_L2C 0x00100000 /* L2 cache */
2442#define UIC_CT0 0x00080000 /* GPT compare timer 0 */
2443#define UIC_CT1 0x00040000 /* GPT compare timer 1 */
2444#define UIC_CT2 0x00020000 /* GPT compare timer 2 */
2445#define UIC_CT3 0x00010000 /* GPT compare timer 3 */
2446#define UIC_CT4 0x00008000 /* GPT compare timer 4 */
2447#define UIC_EIR12 0x00004000 /* External interrupt 12 */
2448#define UIC_EIR11 0x00002000 /* External interrupt 11 */
2449#define UIC_EIR10 0x00001000 /* External interrupt 10 */
2450#define UIC_EIR9 0x00000800 /* External interrupt 9 */
2451#define UIC_EIR8 0x00000400 /* External interrupt 8 */
2452#define UIC_DMAE 0x00000200 /* dma error */
2453#define UIC_I2OE 0x00000100 /* i2o error */
2454#define UIC_SRE 0x00000080 /* Serial ROM error */
2455#define UIC_PCIXAE 0x00000040 /* Pcix0 async error */
2456#define UIC_EIR7 0x00000020 /* External interrupt 7 */
2457#define UIC_EIR6 0x00000010 /* External interrupt 6 */
2458#define UIC_ETH0 0x00000008 /* Ethernet 0 */
2459#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
2460#define UIC_ETH1 0x00000002 /* reserved */
2461#define UIC_XOR 0x00000001 /* xor */
2462
2463/*---------------------------------------------------------------------------+
2464| Universal interrupt controller 2 interrupts (UIC2)
2465+---------------------------------------------------------------------------*/
2466#define UIC_PEOAL 0x80000000 /* PE0 AL */
2467#define UIC_PEOVA 0x40000000 /* PE0 VPD access */
2468#define UIC_PEOHRR 0x20000000 /* PE0 Host reset request rising */
2469#define UIC_PE0HRF 0x10000000 /* PE0 Host reset request falling */
2470#define UIC_PE0TCR 0x08000000 /* PE0 TCR */
2471#define UIC_PE0BVCO 0x04000000 /* PE0 Busmaster VCO */
2472#define UIC_PE0DCRE 0x02000000 /* PE0 DCR error */
2473#define UIC_PE1AL 0x00800000 /* PE1 AL */
2474#define UIC_PE1VA 0x00400000 /* PE1 VPD access */
2475#define UIC_PE1HRR 0x00200000 /* PE1 Host reset request rising */
2476#define UIC_PE1HRF 0x00100000 /* PE1 Host reset request falling */
2477#define UIC_PE1TCR 0x00080000 /* PE1 TCR */
2478#define UIC_PE1BVCO 0x00040000 /* PE1 Busmaster VCO */
2479#define UIC_PE1DCRE 0x00020000 /* PE1 DCR error */
2480#define UIC_PE2AL 0x00008000 /* PE2 AL */
2481#define UIC_PE2VA 0x00004000 /* PE2 VPD access */
2482#define UIC_PE2HRR 0x00002000 /* PE2 Host reset request rising */
2483#define UIC_PE2HRF 0x00001000 /* PE2 Host reset request falling */
2484#define UIC_PE2TCR 0x00000800 /* PE2 TCR */
2485#define UIC_PE2BVCO 0x00000400 /* PE2 Busmaster VCO */
2486#define UIC_PE2DCRE 0x00000200 /* PE2 DCR error */
2487#define UIC_EIR5 0x00000080 /* External interrupt 5 */
2488#define UIC_EIR4 0x00000040 /* External interrupt 4 */
2489#define UIC_EIR3 0x00000020 /* External interrupt 3 */
2490#define UIC_EIR2 0x00000010 /* External interrupt 2 */
2491#define UIC_EIR1 0x00000008 /* External interrupt 1 */
2492#define UIC_EIR0 0x00000004 /* External interrupt 0 */
2493#endif /* CONFIG_440SPE */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]2494
2495/*-----------------------------------------------------------------------------+
wdenk00fe1612004-03-14 00:07:33 +0000[diff] [blame]2496| External Bus Controller Bit Settings
2497+-----------------------------------------------------------------------------*/
wdenk6148e742005-04-03 20:55:38 +0000[diff] [blame]2498#define EBC_CFGADDR_MASK 0x0000003F
wdenk00fe1612004-03-14 00:07:33 +0000[diff] [blame]2499
wdenk6148e742005-04-03 20:55:38 +0000[diff] [blame]2500#define EBC_BXCR_BAS_ENCODE(n) ((((unsigned long)(n))&0xFFF00000)<<0)
2501#define EBC_BXCR_BS_MASK 0x000E0000
2502#define EBC_BXCR_BS_1MB 0x00000000
2503#define EBC_BXCR_BS_2MB 0x00020000
2504#define EBC_BXCR_BS_4MB 0x00040000
2505#define EBC_BXCR_BS_8MB 0x00060000
2506#define EBC_BXCR_BS_16MB 0x00080000
2507#define EBC_BXCR_BS_32MB 0x000A0000
2508#define EBC_BXCR_BS_64MB 0x000C0000
2509#define EBC_BXCR_BS_128MB 0x000E0000
2510#define EBC_BXCR_BU_MASK 0x00018000
2511#define EBC_BXCR_BU_R 0x00008000
2512#define EBC_BXCR_BU_W 0x00010000
2513#define EBC_BXCR_BU_RW 0x00018000
2514#define EBC_BXCR_BW_MASK 0x00006000
2515#define EBC_BXCR_BW_8BIT 0x00000000
2516#define EBC_BXCR_BW_16BIT 0x00002000
Stefan Roese5ff4c3f2005-08-15 12:31:23 +0200[diff] [blame]2517#define EBC_BXCR_BW_32BIT 0x00006000
wdenk6148e742005-04-03 20:55:38 +0000[diff] [blame]2518#define EBC_BXAP_BME_ENABLED 0x80000000
2519#define EBC_BXAP_BME_DISABLED 0x00000000
2520#define EBC_BXAP_TWT_ENCODE(n) ((((unsigned long)(n))&0xFF)<<23)
2521#define EBC_BXAP_BCE_DISABLE 0x00000000
2522#define EBC_BXAP_BCE_ENABLE 0x00400000
Stefan Roese99644742005-11-29 18:18:21 +0100[diff] [blame]2523#define EBC_BXAP_BCT_MASK 0x00300000
2524#define EBC_BXAP_BCT_2TRANS 0x00000000
2525#define EBC_BXAP_BCT_4TRANS 0x00100000
2526#define EBC_BXAP_BCT_8TRANS 0x00200000
2527#define EBC_BXAP_BCT_16TRANS 0x00300000
wdenk6148e742005-04-03 20:55:38 +0000[diff] [blame]2528#define EBC_BXAP_CSN_ENCODE(n) ((((unsigned long)(n))&0x3)<<18)
2529#define EBC_BXAP_OEN_ENCODE(n) ((((unsigned long)(n))&0x3)<<16)
2530#define EBC_BXAP_WBN_ENCODE(n) ((((unsigned long)(n))&0x3)<<14)
2531#define EBC_BXAP_WBF_ENCODE(n) ((((unsigned long)(n))&0x3)<<12)
2532#define EBC_BXAP_TH_ENCODE(n) ((((unsigned long)(n))&0x7)<<9)
2533#define EBC_BXAP_RE_ENABLED 0x00000100
2534#define EBC_BXAP_RE_DISABLED 0x00000000
2535#define EBC_BXAP_SOR_DELAYED 0x00000000
2536#define EBC_BXAP_SOR_NONDELAYED 0x00000080
2537#define EBC_BXAP_BEM_WRITEONLY 0x00000000
2538#define EBC_BXAP_BEM_RW 0x00000040
2539#define EBC_BXAP_PEN_DISABLED 0x00000000
wdenk00fe1612004-03-14 00:07:33 +0000[diff] [blame]2540
wdenk6148e742005-04-03 20:55:38 +0000[diff] [blame]2541#define EBC_CFG_LE_MASK 0x80000000
2542#define EBC_CFG_LE_UNLOCK 0x00000000
2543#define EBC_CFG_LE_LOCK 0x80000000
2544#define EBC_CFG_PTD_MASK 0x40000000
2545#define EBC_CFG_PTD_ENABLE 0x00000000
2546#define EBC_CFG_PTD_DISABLE 0x40000000
2547#define EBC_CFG_RTC_MASK 0x38000000
2548#define EBC_CFG_RTC_16PERCLK 0x00000000
2549#define EBC_CFG_RTC_32PERCLK 0x08000000
2550#define EBC_CFG_RTC_64PERCLK 0x10000000
2551#define EBC_CFG_RTC_128PERCLK 0x18000000
2552#define EBC_CFG_RTC_256PERCLK 0x20000000
2553#define EBC_CFG_RTC_512PERCLK 0x28000000
2554#define EBC_CFG_RTC_1024PERCLK 0x30000000
2555#define EBC_CFG_RTC_2048PERCLK 0x38000000
2556#define EBC_CFG_ATC_MASK 0x04000000
2557#define EBC_CFG_ATC_HI 0x00000000
2558#define EBC_CFG_ATC_PREVIOUS 0x04000000
2559#define EBC_CFG_DTC_MASK 0x02000000
2560#define EBC_CFG_DTC_HI 0x00000000
2561#define EBC_CFG_DTC_PREVIOUS 0x02000000
2562#define EBC_CFG_CTC_MASK 0x01000000
2563#define EBC_CFG_CTC_HI 0x00000000
2564#define EBC_CFG_CTC_PREVIOUS 0x01000000
2565#define EBC_CFG_OEO_MASK 0x00800000
2566#define EBC_CFG_OEO_HI 0x00000000
2567#define EBC_CFG_OEO_PREVIOUS 0x00800000
2568#define EBC_CFG_EMC_MASK 0x00400000
2569#define EBC_CFG_EMC_NONDEFAULT 0x00000000
2570#define EBC_CFG_EMC_DEFAULT 0x00400000
2571#define EBC_CFG_PME_MASK 0x00200000
2572#define EBC_CFG_PME_DISABLE 0x00000000
2573#define EBC_CFG_PME_ENABLE 0x00200000
2574#define EBC_CFG_PMT_MASK 0x001F0000
2575#define EBC_CFG_PMT_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12)
2576#define EBC_CFG_PR_MASK 0x0000C000
2577#define EBC_CFG_PR_16 0x00000000
2578#define EBC_CFG_PR_32 0x00004000
2579#define EBC_CFG_PR_64 0x00008000
2580#define EBC_CFG_PR_128 0x0000C000
wdenk00fe1612004-03-14 00:07:33 +0000[diff] [blame]2581
2582/*-----------------------------------------------------------------------------+
Stefan Roese99644742005-11-29 18:18:21 +0100[diff] [blame]2583| SDR0 Bit Settings
wdenk00fe1612004-03-14 00:07:33 +0000[diff] [blame]2584+-----------------------------------------------------------------------------*/
Stefan Roeseb39ef632007-03-08 10:06:09 +0100[diff] [blame]2585#if defined(CONFIG_440SP)
2586#define SDR0_SRST 0x0200
2587
2588#define SDR0_DDR0 0x00E1
2589#define SDR0_DDR0_DPLLRST 0x80000000
2590#define SDR0_DDR0_DDRM_MASK 0x60000000
2591#define SDR0_DDR0_DDRM_DDR1 0x20000000
2592#define SDR0_DDR0_DDRM_DDR2 0x40000000
2593#define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n))&0x03)<<29)
2594#define SDR0_DDR0_DDRM_DECODE(n) ((((unsigned long)(n))>>29)&0x03)
2595#define SDR0_DDR0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x2FF)<<0)
2596#define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF)
2597#endif
2598
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]2599#if defined(CONFIG_440SPE)
2600#define SDR0_CP440 0x0180
2601#define SDR0_CP440_ERPN_MASK 0x30000000
2602#define SDR0_CP440_ERPN_MASK_HI 0x3000
2603#define SDR0_CP440_ERPN_MASK_LO 0x0000
2604#define SDR0_CP440_ERPN_EBC 0x10000000
2605#define SDR0_CP440_ERPN_EBC_HI 0x1000
2606#define SDR0_CP440_ERPN_EBC_LO 0x0000
2607#define SDR0_CP440_ERPN_PCI 0x20000000
2608#define SDR0_CP440_ERPN_PCI_HI 0x2000
2609#define SDR0_CP440_ERPN_PCI_LO 0x0000
2610#define SDR0_CP440_ERPN_ENCODE(n) ((((unsigned long)(n))&0x03)<<28)
2611#define SDR0_CP440_ERPN_DECODE(n) ((((unsigned long)(n))>>28)&0x03)
2612#define SDR0_CP440_NTO1_MASK 0x00000002
2613#define SDR0_CP440_NTO1_NTOP 0x00000000
2614#define SDR0_CP440_NTO1_NTO1 0x00000002
2615#define SDR0_CP440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1)
2616#define SDR0_CP440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01)
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]2617
2618#define SDR0_SDSTP0 0x0020
2619#define SDR0_SDSTP0_ENG_MASK 0x80000000
2620#define SDR0_SDSTP0_ENG_PLLDIS 0x00000000
2621#define SDR0_SDSTP0_ENG_PLLENAB 0x80000000
2622#define SDR0_SDSTP0_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
2623#define SDR0_SDSTP0_ENG_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
2624#define SDR0_SDSTP0_SRC_MASK 0x40000000
2625#define SDR0_SDSTP0_SRC_PLLOUTA 0x00000000
2626#define SDR0_SDSTP0_SRC_PLLOUTB 0x40000000
2627#define SDR0_SDSTP0_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
2628#define SDR0_SDSTP0_SRC_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
2629#define SDR0_SDSTP0_SEL_MASK 0x38000000
2630#define SDR0_SDSTP0_SEL_PLLOUT 0x00000000
2631#define SDR0_SDSTP0_SEL_CPU 0x08000000
2632#define SDR0_SDSTP0_SEL_EBC 0x28000000
2633#define SDR0_SDSTP0_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<27)
2634#define SDR0_SDSTP0_SEL_DECODE(n) ((((unsigned long)(n))>>27)&0x07)
2635#define SDR0_SDSTP0_TUNE_MASK 0x07FE0000
2636#define SDR0_SDSTP0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<17)
2637#define SDR0_SDSTP0_TUNE_DECODE(n) ((((unsigned long)(n))>>17)&0x3FF)
2638#define SDR0_SDSTP0_FBDV_MASK 0x0001F000
2639#define SDR0_SDSTP0_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12)
2640#define SDR0_SDSTP0_FBDV_DECODE(n) ((((((unsigned long)(n))>>12)-1)&0x1F)+1)
2641#define SDR0_SDSTP0_FWDVA_MASK 0x00000F00
2642#define SDR0_SDSTP0_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<8)
2643#define SDR0_SDSTP0_FWDVA_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x0F)+1)
2644#define SDR0_SDSTP0_FWDVB_MASK 0x000000E0
2645#define SDR0_SDSTP0_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<5)
2646#define SDR0_SDSTP0_FWDVB_DECODE(n) ((((((unsigned long)(n))>>5)-1)&0x07)+1)
2647#define SDR0_SDSTP0_PRBDV0_MASK 0x0000001C
2648#define SDR0_SDSTP0_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<2)
2649#define SDR0_SDSTP0_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>2)-1)&0x07)+1)
2650#define SDR0_SDSTP0_OPBDV0_MASK 0x00000003
2651#define SDR0_SDSTP0_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<0)
2652#define SDR0_SDSTP0_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x03)+1)
2653
2654
2655#define SDR0_SDSTP1 0x0021
2656#define SDR0_SDSTP1_LFBDV_MASK 0xFC000000
2657#define SDR0_SDSTP1_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<26)
2658#define SDR0_SDSTP1_LFBDV_DECODE(n) ((((unsigned long)(n))>>26)&0x3F)
2659#define SDR0_SDSTP1_PERDV0_MASK 0x03000000
2660#define SDR0_SDSTP1_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
2661#define SDR0_SDSTP1_PERDV0_DECODE(n) ((((unsigned long)(n))>>24)&0x03)
2662#define SDR0_SDSTP1_MALDV0_MASK 0x00C00000
2663#define SDR0_SDSTP1_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<22)
2664#define SDR0_SDSTP1_MALDV0_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
2665#define SDR0_SDSTP1_DDR_MODE_MASK 0x00300000
2666#define SDR0_SDSTP1_DDR1_MODE 0x00100000
2667#define SDR0_SDSTP1_DDR2_MODE 0x00200000
2668#define SDR0_SDSTP1_DDR_ENCODE(n) ((((unsigned long)(n))&0x03)<<20)
2669#define SDR0_SDSTP1_DDR_DECODE(n) ((((unsigned long)(n))>>20)&0x03)
2670#define SDR0_SDSTP1_ERPN_MASK 0x00080000
2671#define SDR0_SDSTP1_ERPN_EBC 0x00000000
2672#define SDR0_SDSTP1_ERPN_PCI 0x00080000
2673#define SDR0_SDSTP1_PAE_MASK 0x00040000
2674#define SDR0_SDSTP1_PAE_DISABLE 0x00000000
2675#define SDR0_SDSTP1_PAE_ENABLE 0x00040000
2676#define SDR0_SDSTP1_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<18)
2677#define SDR0_SDSTP1_PAE_DECODE(n) ((((unsigned long)(n))>>18)&0x01)
2678#define SDR0_SDSTP1_PHCE_MASK 0x00020000
2679#define SDR0_SDSTP1_PHCE_DISABLE 0x00000000
2680#define SDR0_SDSTP1_PHCE_ENABLE 0x00020000
2681#define SDR0_SDSTP1_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<17)
2682#define SDR0_SDSTP1_PHCE_DECODE(n) ((((unsigned long)(n))>>17)&0x01)
2683#define SDR0_SDSTP1_PISE_MASK 0x00010000
2684#define SDR0_SDSTP1_PISE_DISABLE 0x00000000
2685#define SDR0_SDSTP1_PISE_ENABLE 0x00001000
2686#define SDR0_SDSTP1_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<16)
2687#define SDR0_SDSTP1_PISE_DECODE(n) ((((unsigned long)(n))>>16)&0x01)
2688#define SDR0_SDSTP1_PCWE_MASK 0x00008000
2689#define SDR0_SDSTP1_PCWE_DISABLE 0x00000000
2690#define SDR0_SDSTP1_PCWE_ENABLE 0x00008000
2691#define SDR0_SDSTP1_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<15)
2692#define SDR0_SDSTP1_PCWE_DECODE(n) ((((unsigned long)(n))>>15)&0x01)
2693#define SDR0_SDSTP1_PPIM_MASK 0x00007800
2694#define SDR0_SDSTP1_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<11)
2695#define SDR0_SDSTP1_PPIM_DECODE(n) ((((unsigned long)(n))>>11)&0x0F)
2696#define SDR0_SDSTP1_PR64E_MASK 0x00000400
2697#define SDR0_SDSTP1_PR64E_DISABLE 0x00000000
2698#define SDR0_SDSTP1_PR64E_ENABLE 0x00000400
2699#define SDR0_SDSTP1_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<10)
2700#define SDR0_SDSTP1_PR64E_DECODE(n) ((((unsigned long)(n))>>10)&0x01)
2701#define SDR0_SDSTP1_PXFS_MASK 0x00000300
2702#define SDR0_SDSTP1_PXFS_100_133 0x00000000
2703#define SDR0_SDSTP1_PXFS_66_100 0x00000100
2704#define SDR0_SDSTP1_PXFS_50_66 0x00000200
2705#define SDR0_SDSTP1_PXFS_0_50 0x00000300
2706#define SDR0_SDSTP1_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
2707#define SDR0_SDSTP1_PXFS_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
2708#define SDR0_SDSTP1_EBCW_MASK 0x00000080 /* SOP */
2709#define SDR0_SDSTP1_EBCW_8_BITS 0x00000000 /* SOP */
2710#define SDR0_SDSTP1_EBCW_16_BITS 0x00000080 /* SOP */
2711#define SDR0_SDSTP1_DBGEN_MASK 0x00000030 /* $218C */
2712#define SDR0_SDSTP1_DBGEN_FUNC 0x00000000
2713#define SDR0_SDSTP1_DBGEN_TRACE 0x00000010
2714#define SDR0_SDSTP1_DBGEN_ENCODE(n) ((((unsigned long)(n))&0x03)<<4) /* $218C */
2715#define SDR0_SDSTP1_DBGEN_DECODE(n) ((((unsigned long)(n))>>4)&0x03) /* $218C */
2716#define SDR0_SDSTP1_ETH_MASK 0x00000004
2717#define SDR0_SDSTP1_ETH_10_100 0x00000000
2718#define SDR0_SDSTP1_ETH_GIGA 0x00000004
2719#define SDR0_SDSTP1_ETH_ENCODE(n) ((((unsigned long)(n))&0x01)<<2)
2720#define SDR0_SDSTP1_ETH_DECODE(n) ((((unsigned long)(n))>>2)&0x01)
2721#define SDR0_SDSTP1_NTO1_MASK 0x00000001
2722#define SDR0_SDSTP1_NTO1_DISABLE 0x00000000
2723#define SDR0_SDSTP1_NTO1_ENABLE 0x00000001
2724#define SDR0_SDSTP1_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<0)
2725#define SDR0_SDSTP1_NTO1_DECODE(n) ((((unsigned long)(n))>>0)&0x01)
2726
2727#define SDR0_SDSTP2 0x0022
2728#define SDR0_SDSTP2_P1AE_MASK 0x80000000
2729#define SDR0_SDSTP2_P1AE_DISABLE 0x00000000
2730#define SDR0_SDSTP2_P1AE_ENABLE 0x80000000
2731#define SDR0_SDSTP2_P1AE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
2732#define SDR0_SDSTP2_P1AE_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
2733#define SDR0_SDSTP2_P1HCE_MASK 0x40000000
2734#define SDR0_SDSTP2_P1HCE_DISABLE 0x00000000
2735#define SDR0_SDSTP2_P1HCE_ENABLE 0x40000000
2736#define SDR0_SDSTP2_P1HCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
2737#define SDR0_SDSTP2_P1HCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
2738#define SDR0_SDSTP2_P1ISE_MASK 0x20000000
2739#define SDR0_SDSTP2_P1ISE_DISABLE 0x00000000
2740#define SDR0_SDSTP2_P1ISE_ENABLE 0x20000000
2741#define SDR0_SDSTP2_P1ISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
2742#define SDR0_SDSTP2_P1ISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
2743#define SDR0_SDSTP2_P1CWE_MASK 0x10000000
2744#define SDR0_SDSTP2_P1CWE_DISABLE 0x00000000
2745#define SDR0_SDSTP2_P1CWE_ENABLE 0x10000000
2746#define SDR0_SDSTP2_P1CWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28)
2747#define SDR0_SDSTP2_P1CWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01)
2748#define SDR0_SDSTP2_P1PIM_MASK 0x0F000000
2749#define SDR0_SDSTP2_P1PIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24)
2750#define SDR0_SDSTP2_P1PIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
2751#define SDR0_SDSTP2_P1R64E_MASK 0x00800000
2752#define SDR0_SDSTP2_P1R64E_DISABLE 0x00000000
2753#define SDR0_SDSTP2_P1R64E_ENABLE 0x00800000
2754#define SDR0_SDSTP2_P1R64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23)
2755#define SDR0_SDSTP2_P1R64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01)
2756#define SDR0_SDSTP2_P1XFS_MASK 0x00600000
2757#define SDR0_SDSTP2_P1XFS_100_133 0x00000000
2758#define SDR0_SDSTP2_P1XFS_66_100 0x00200000
2759#define SDR0_SDSTP2_P1XFS_50_66 0x00400000
2760#define SDR0_SDSTP2_P1XFS_0_50 0x00600000
2761#define SDR0_SDSTP2_P1XFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21)
2762#define SDR0_SDSTP2_P1XFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03)
2763#define SDR0_SDSTP2_P2AE_MASK 0x00040000
2764#define SDR0_SDSTP2_P2AE_DISABLE 0x00000000
2765#define SDR0_SDSTP2_P2AE_ENABLE 0x00040000
2766#define SDR0_SDSTP2_P2AE_ENCODE(n) ((((unsigned long)(n))&0x01)<<18)
2767#define SDR0_SDSTP2_P2AE_DECODE(n) ((((unsigned long)(n))>>18)&0x01)
2768#define SDR0_SDSTP2_P2HCE_MASK 0x00020000
2769#define SDR0_SDSTP2_P2HCE_DISABLE 0x00000000
2770#define SDR0_SDSTP2_P2HCE_ENABLE 0x00020000
2771#define SDR0_SDSTP2_P2HCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<17)
2772#define SDR0_SDSTP2_P2HCE_DECODE(n) ((((unsigned long)(n))>>17)&0x01)
2773#define SDR0_SDSTP2_P2ISE_MASK 0x00010000
2774#define SDR0_SDSTP2_P2ISE_DISABLE 0x00000000
2775#define SDR0_SDSTP2_P2ISE_ENABLE 0x00010000
2776#define SDR0_SDSTP2_P2ISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<16)
2777#define SDR0_SDSTP2_P2ISE_DECODE(n) ((((unsigned long)(n))>>16)&0x01)
2778#define SDR0_SDSTP2_P2CWE_MASK 0x00008000
2779#define SDR0_SDSTP2_P2CWE_DISABLE 0x00000000
2780#define SDR0_SDSTP2_P2CWE_ENABLE 0x00008000
2781#define SDR0_SDSTP2_P2CWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<15)
2782#define SDR0_SDSTP2_P2CWE_DECODE(n) ((((unsigned long)(n))>>15)&0x01)
2783#define SDR0_SDSTP2_P2PIM_MASK 0x00007800
2784#define SDR0_SDSTP2_P2PIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<11)
2785#define SDR0_SDSTP2_P2PIM_DECODE(n) ((((unsigned long)(n))>>11)&0x0F)
2786#define SDR0_SDSTP2_P2XFS_MASK 0x00000300
2787#define SDR0_SDSTP2_P2XFS_100_133 0x00000000
2788#define SDR0_SDSTP2_P2XFS_66_100 0x00000100
2789#define SDR0_SDSTP2_P2XFS_50_66 0x00000200
2790#define SDR0_SDSTP2_P2XFS_0_50 0x00000100
2791#define SDR0_SDSTP2_P2XFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
2792#define SDR0_SDSTP2_P2XFS_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
2793
2794#define SDR0_SDSTP3 0x0023
2795
2796#define SDR0_PINSTP 0x0040
2797#define SDR0_PINSTP_BOOTSTRAP_MASK 0xC0000000 /* Strap Bits */
2798#define SDR0_PINSTP_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 (EBC boot) */
2799#define SDR0_PINSTP_BOOTSTRAP_SETTINGS1 0x40000000 /* Default strap settings 1 (PCI boot) */
2800#define SDR0_PINSTP_BOOTSTRAP_IIC_54_EN 0x80000000 /* Serial Device Enabled - Addr = 0x54 */
2801#define SDR0_PINSTP_BOOTSTRAP_IIC_50_EN 0xC0000000 /* Serial Device Enabled - Addr = 0x50 */
2802#define SDR0_SDCS 0x0060
2803#define SDR0_ECID0 0x0080
2804#define SDR0_ECID1 0x0081
2805#define SDR0_ECID2 0x0082
2806#define SDR0_JTAG 0x00C0
2807
2808#define SDR0_DDR0 0x00E1
2809#define SDR0_DDR0_DPLLRST 0x80000000
2810#define SDR0_DDR0_DDRM_MASK 0x60000000
2811#define SDR0_DDR0_DDRM_DDR1 0x20000000
2812#define SDR0_DDR0_DDRM_DDR2 0x40000000
2813#define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n))&0x03)<<29)
2814#define SDR0_DDR0_DDRM_DECODE(n) ((((unsigned long)(n))>>29)&0x03)
2815#define SDR0_DDR0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x2FF)<<0)
2816#define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF)
2817
2818#define SDR0_UART0 0x0120
2819#define SDR0_UART1 0x0121
2820#define SDR0_UART2 0x0122
2821#define SDR0_UARTX_UXICS_MASK 0xF0000000
2822#define SDR0_UARTX_UXICS_PLB 0x20000000
2823#define SDR0_UARTX_UXEC_MASK 0x00800000
2824#define SDR0_UARTX_UXEC_INT 0x00000000
2825#define SDR0_UARTX_UXEC_EXT 0x00800000
2826#define SDR0_UARTX_UXDIV_MASK 0x000000FF
2827#define SDR0_UARTX_UXDIV_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
2828#define SDR0_UARTX_UXDIV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0xFF)+1)
2829
2830#define SDR0_CP440 0x0180
2831#define SDR0_CP440_ERPN_MASK 0x30000000
2832#define SDR0_CP440_ERPN_MASK_HI 0x3000
2833#define SDR0_CP440_ERPN_MASK_LO 0x0000
2834#define SDR0_CP440_ERPN_EBC 0x10000000
2835#define SDR0_CP440_ERPN_EBC_HI 0x1000
2836#define SDR0_CP440_ERPN_EBC_LO 0x0000
2837#define SDR0_CP440_ERPN_PCI 0x20000000
2838#define SDR0_CP440_ERPN_PCI_HI 0x2000
2839#define SDR0_CP440_ERPN_PCI_LO 0x0000
2840#define SDR0_CP440_ERPN_ENCODE(n) ((((unsigned long)(n))&0x03)<<28)
2841#define SDR0_CP440_ERPN_DECODE(n) ((((unsigned long)(n))>>28)&0x03)
2842#define SDR0_CP440_NTO1_MASK 0x00000002
2843#define SDR0_CP440_NTO1_NTOP 0x00000000
2844#define SDR0_CP440_NTO1_NTO1 0x00000002
2845#define SDR0_CP440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1)
2846#define SDR0_CP440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01)
2847
2848#define SDR0_XCR0 0x01C0
2849#define SDR0_XCR1 0x01C3
2850#define SDR0_XCR2 0x01C6
2851#define SDR0_XCRn_PAE_MASK 0x80000000
2852#define SDR0_XCRn_PAE_DISABLE 0x00000000
2853#define SDR0_XCRn_PAE_ENABLE 0x80000000
2854#define SDR0_XCRn_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
2855#define SDR0_XCRn_PAE_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
2856#define SDR0_XCRn_PHCE_MASK 0x40000000
2857#define SDR0_XCRn_PHCE_DISABLE 0x00000000
2858#define SDR0_XCRn_PHCE_ENABLE 0x40000000
2859#define SDR0_XCRn_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
2860#define SDR0_XCRn_PHCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
2861#define SDR0_XCRn_PISE_MASK 0x20000000
2862#define SDR0_XCRn_PISE_DISABLE 0x00000000
2863#define SDR0_XCRn_PISE_ENABLE 0x20000000
2864#define SDR0_XCRn_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
2865#define SDR0_XCRn_PISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
2866#define SDR0_XCRn_PCWE_MASK 0x10000000
2867#define SDR0_XCRn_PCWE_DISABLE 0x00000000
2868#define SDR0_XCRn_PCWE_ENABLE 0x10000000
2869#define SDR0_XCRn_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28)
2870#define SDR0_XCRn_PCWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01)
2871#define SDR0_XCRn_PPIM_MASK 0x0F000000
2872#define SDR0_XCRn_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24)
2873#define SDR0_XCRn_PPIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
2874#define SDR0_XCRn_PR64E_MASK 0x00800000
2875#define SDR0_XCRn_PR64E_DISABLE 0x00000000
2876#define SDR0_XCRn_PR64E_ENABLE 0x00800000
2877#define SDR0_XCRn_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23)
2878#define SDR0_XCRn_PR64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01)
2879#define SDR0_XCRn_PXFS_MASK 0x00600000
2880#define SDR0_XCRn_PXFS_100_133 0x00000000
2881#define SDR0_XCRn_PXFS_66_100 0x00200000
2882#define SDR0_XCRn_PXFS_50_66 0x00400000
2883#define SDR0_XCRn_PXFS_0_33 0x00600000
2884#define SDR0_XCRn_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21)
2885#define SDR0_XCRn_PXFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03)
2886
2887#define SDR0_XPLLC0 0x01C1
2888#define SDR0_XPLLD0 0x01C2
2889#define SDR0_XPLLC1 0x01C4
2890#define SDR0_XPLLD1 0x01C5
2891#define SDR0_XPLLC2 0x01C7
2892#define SDR0_XPLLD2 0x01C8
2893#define SDR0_SRST 0x0200
2894#define SDR0_SLPIPE 0x0220
2895
2896#define SDR0_AMP0 0x0240
2897#define SDR0_AMP0_PRIORITY 0xFFFF0000
2898#define SDR0_AMP0_ALTERNATE_PRIORITY 0x0000FF00
2899#define SDR0_AMP0_RESERVED_BITS_MASK 0x000000FF
2900
2901#define SDR0_AMP1 0x0241
2902#define SDR0_AMP1_PRIORITY 0xFC000000
2903#define SDR0_AMP1_ALTERNATE_PRIORITY 0x0000E000
2904#define SDR0_AMP1_RESERVED_BITS_MASK 0x03FF1FFF
2905
2906#define SDR0_MIRQ0 0x0260
2907#define SDR0_MIRQ1 0x0261
2908#define SDR0_MALTBL 0x0280
2909#define SDR0_MALRBL 0x02A0
2910#define SDR0_MALTBS 0x02C0
2911#define SDR0_MALRBS 0x02E0
2912
2913/* Reserved for Customer Use */
2914#define SDR0_CUST0 0x4000
2915#define SDR0_CUST0_AUTONEG_MASK 0x8000000
2916#define SDR0_CUST0_NO_AUTONEG 0x0000000
2917#define SDR0_CUST0_AUTONEG 0x8000000
2918#define SDR0_CUST0_ETH_FORCE_MASK 0x6000000
2919#define SDR0_CUST0_ETH_FORCE_10MHZ 0x0000000
2920#define SDR0_CUST0_ETH_FORCE_100MHZ 0x2000000
2921#define SDR0_CUST0_ETH_FORCE_1000MHZ 0x4000000
2922#define SDR0_CUST0_ETH_DUPLEX_MASK 0x1000000
2923#define SDR0_CUST0_ETH_HALF_DUPLEX 0x0000000
2924#define SDR0_CUST0_ETH_FULL_DUPLEX 0x1000000
2925
2926#define SDR0_SDSTP4 0x4001
2927#define SDR0_CUST1 0x4002
2928#define SDR0_SDSTP5 0x4003
2929#define SDR0_CUST2 0x4004
2930#define SDR0_SDSTP6 0x4005
2931#define SDR0_CUST3 0x4006
2932#define SDR0_SDSTP7 0x4007
2933
2934#define SDR0_PFC0 0x4100
2935#define SDR0_PFC0_GPIO_0 0x80000000
2936#define SDR0_PFC0_PCIX0REQ2_N 0x00000000
2937#define SDR0_PFC0_GPIO_1 0x40000000
2938#define SDR0_PFC0_PCIX0REQ3_N 0x00000000
2939#define SDR0_PFC0_GPIO_2 0x20000000
2940#define SDR0_PFC0_PCIX0GNT2_N 0x00000000
2941#define SDR0_PFC0_GPIO_3 0x10000000
2942#define SDR0_PFC0_PCIX0GNT3_N 0x00000000
2943#define SDR0_PFC0_GPIO_4 0x08000000
2944#define SDR0_PFC0_PCIX1REQ2_N 0x00000000
2945#define SDR0_PFC0_GPIO_5 0x04000000
2946#define SDR0_PFC0_PCIX1REQ3_N 0x00000000
2947#define SDR0_PFC0_GPIO_6 0x02000000
2948#define SDR0_PFC0_PCIX1GNT2_N 0x00000000
2949#define SDR0_PFC0_GPIO_7 0x01000000
2950#define SDR0_PFC0_PCIX1GNT3_N 0x00000000
2951#define SDR0_PFC0_GPIO_8 0x00800000
2952#define SDR0_PFC0_PERREADY 0x00000000
2953#define SDR0_PFC0_GPIO_9 0x00400000
2954#define SDR0_PFC0_PERCS1_N 0x00000000
2955#define SDR0_PFC0_GPIO_10 0x00200000
2956#define SDR0_PFC0_PERCS2_N 0x00000000
2957#define SDR0_PFC0_GPIO_11 0x00100000
2958#define SDR0_PFC0_IRQ0 0x00000000
2959#define SDR0_PFC0_GPIO_12 0x00080000
2960#define SDR0_PFC0_IRQ1 0x00000000
2961#define SDR0_PFC0_GPIO_13 0x00040000
2962#define SDR0_PFC0_IRQ2 0x00000000
2963#define SDR0_PFC0_GPIO_14 0x00020000
2964#define SDR0_PFC0_IRQ3 0x00000000
2965#define SDR0_PFC0_GPIO_15 0x00010000
2966#define SDR0_PFC0_IRQ4 0x00000000
2967#define SDR0_PFC0_GPIO_16 0x00008000
2968#define SDR0_PFC0_IRQ5 0x00000000
2969#define SDR0_PFC0_GPIO_17 0x00004000
2970#define SDR0_PFC0_PERBE0_N 0x00000000
2971#define SDR0_PFC0_GPIO_18 0x00002000
2972#define SDR0_PFC0_PCI0GNT0_N 0x00000000
2973#define SDR0_PFC0_GPIO_19 0x00001000
2974#define SDR0_PFC0_PCI0GNT1_N 0x00000000
2975#define SDR0_PFC0_GPIO_20 0x00000800
2976#define SDR0_PFC0_PCI0REQ0_N 0x00000000
2977#define SDR0_PFC0_GPIO_21 0x00000400
2978#define SDR0_PFC0_PCI0REQ1_N 0x00000000
2979#define SDR0_PFC0_GPIO_22 0x00000200
2980#define SDR0_PFC0_PCI1GNT0_N 0x00000000
2981#define SDR0_PFC0_GPIO_23 0x00000100
2982#define SDR0_PFC0_PCI1GNT1_N 0x00000000
2983#define SDR0_PFC0_GPIO_24 0x00000080
2984#define SDR0_PFC0_PCI1REQ0_N 0x00000000
2985#define SDR0_PFC0_GPIO_25 0x00000040
2986#define SDR0_PFC0_PCI1REQ1_N 0x00000000
2987#define SDR0_PFC0_GPIO_26 0x00000020
2988#define SDR0_PFC0_PCI2GNT0_N 0x00000000
2989#define SDR0_PFC0_GPIO_27 0x00000010
2990#define SDR0_PFC0_PCI2GNT1_N 0x00000000
2991#define SDR0_PFC0_GPIO_28 0x00000008
2992#define SDR0_PFC0_PCI2REQ0_N 0x00000000
2993#define SDR0_PFC0_GPIO_29 0x00000004
2994#define SDR0_PFC0_PCI2REQ1_N 0x00000000
2995#define SDR0_PFC0_GPIO_30 0x00000002
2996#define SDR0_PFC0_UART1RX 0x00000000
2997#define SDR0_PFC0_GPIO_31 0x00000001
2998#define SDR0_PFC0_UART1TX 0x00000000
2999
3000#define SDR0_PFC1 0x4101
3001#define SDR0_PFC1_UART1_CTS_RTS_MASK 0x02000000
3002#define SDR0_PFC1_UART1_DSR_DTR 0x00000000
3003#define SDR0_PFC1_UART1_CTS_RTS 0x02000000
3004#define SDR0_PFC1_UART2_IN_SERVICE_MASK 0x01000000
3005#define SDR0_PFC1_UART2_NOT_IN_SERVICE 0x00000000
3006#define SDR0_PFC1_UART2_IN_SERVICE 0x01000000
3007#define SDR0_PFC1_ETH_GIGA_MASK 0x00200000
3008#define SDR0_PFC1_ETH_10_100 0x00000000
3009#define SDR0_PFC1_ETH_GIGA 0x00200000
3010#define SDR0_PFC1_ETH_GIGA_ENCODE(n) ((((unsigned long)(n))&0x1)<<21)
3011#define SDR0_PFC1_ETH_GIGA_DECODE(n) ((((unsigned long)(n))>>21)&0x01)
3012#define SDR0_PFC1_CPU_TRACE_MASK 0x00180000 /* $218C */
3013#define SDR0_PFC1_CPU_NO_TRACE 0x00000000
3014#define SDR0_PFC1_CPU_TRACE 0x00080000
3015#define SDR0_PFC1_CPU_TRACE_ENCODE(n) ((((unsigned long)(n))&0x3)<<19) /* $218C */
3016#define SDR0_PFC1_CPU_TRACE_DECODE(n) ((((unsigned long)(n))>>19)&0x03) /* $218C */
3017
3018#define SDR0_MFR 0x4300
3019#endif /* CONFIG_440SPE */
3020
3021
Stefan Roese99644742005-11-29 18:18:21 +0100[diff] [blame]3022#define SDR0_SDCS_SDD (0x80000000 >> 31)
wdenk00fe1612004-03-14 00:07:33 +0000[diff] [blame]3023
Stefan Roese99644742005-11-29 18:18:21 +0100[diff] [blame]3024#if defined(CONFIG_440GP)
3025#define CPC0_STRP1_PAE_MASK (0x80000000 >> 11)
3026#define CPC0_STRP1_PISE_MASK (0x80000000 >> 13)
3027#endif /* defined(CONFIG_440GP) */
3028#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
3029#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 13)
3030#define SDR0_SDSTP1_PISE_MASK (0x80000000 >> 15)
3031#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
Stefan Roese42fbddd2006-09-07 11:51:23 +0200[diff] [blame]3032#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
3033 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
Stefan Roese99644742005-11-29 18:18:21 +0100[diff] [blame]3034#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 21)
3035#define SDR0_SDSTP1_PAME_MASK (0x80000000 >> 27)
3036#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
wdenk00fe1612004-03-14 00:07:33 +0000[diff] [blame]3037
wdenk6148e742005-04-03 20:55:38 +0000[diff] [blame]3038#define SDR0_UARTX_UXICS_MASK 0xF0000000
3039#define SDR0_UARTX_UXICS_PLB 0x20000000
3040#define SDR0_UARTX_UXEC_MASK 0x00800000
3041#define SDR0_UARTX_UXEC_INT 0x00000000
3042#define SDR0_UARTX_UXEC_EXT 0x00800000
3043#define SDR0_UARTX_UXDTE_MASK 0x00400000
3044#define SDR0_UARTX_UXDTE_DISABLE 0x00000000
3045#define SDR0_UARTX_UXDTE_ENABLE 0x00400000
3046#define SDR0_UARTX_UXDRE_MASK 0x00200000
3047#define SDR0_UARTX_UXDRE_DISABLE 0x00000000
3048#define SDR0_UARTX_UXDRE_ENABLE 0x00200000
3049#define SDR0_UARTX_UXDC_MASK 0x00100000
3050#define SDR0_UARTX_UXDC_NOTCLEARED 0x00000000
3051#define SDR0_UARTX_UXDC_CLEARED 0x00100000
3052#define SDR0_UARTX_UXDIV_MASK 0x000000FF
3053#define SDR0_UARTX_UXDIV_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
3054#define SDR0_UARTX_UXDIV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0xFF)+1)
wdenk00fe1612004-03-14 00:07:33 +0000[diff] [blame]3055
wdenk6148e742005-04-03 20:55:38 +0000[diff] [blame]3056#define SDR0_CPU440_EARV_MASK 0x30000000
3057#define SDR0_CPU440_EARV_EBC 0x10000000
3058#define SDR0_CPU440_EARV_PCI 0x20000000
3059#define SDR0_CPU440_EARV_ENCODE(n) ((((unsigned long)(n))&0x03)<<28)
3060#define SDR0_CPU440_EARV_DECODE(n) ((((unsigned long)(n))>>28)&0x03)
3061#define SDR0_CPU440_NTO1_MASK 0x00000002
3062#define SDR0_CPU440_NTO1_NTOP 0x00000000
3063#define SDR0_CPU440_NTO1_NTO1 0x00000002
3064#define SDR0_CPU440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1)
3065#define SDR0_CPU440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01)
wdenk00fe1612004-03-14 00:07:33 +0000[diff] [blame]3066
wdenk6148e742005-04-03 20:55:38 +0000[diff] [blame]3067#define SDR0_XCR_PAE_MASK 0x80000000
3068#define SDR0_XCR_PAE_DISABLE 0x00000000
3069#define SDR0_XCR_PAE_ENABLE 0x80000000
3070#define SDR0_XCR_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
3071#define SDR0_XCR_PAE_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
3072#define SDR0_XCR_PHCE_MASK 0x40000000
3073#define SDR0_XCR_PHCE_DISABLE 0x00000000
3074#define SDR0_XCR_PHCE_ENABLE 0x40000000
3075#define SDR0_XCR_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
3076#define SDR0_XCR_PHCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
3077#define SDR0_XCR_PISE_MASK 0x20000000
3078#define SDR0_XCR_PISE_DISABLE 0x00000000
3079#define SDR0_XCR_PISE_ENABLE 0x20000000
3080#define SDR0_XCR_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
3081#define SDR0_XCR_PISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
3082#define SDR0_XCR_PCWE_MASK 0x10000000
3083#define SDR0_XCR_PCWE_DISABLE 0x00000000
3084#define SDR0_XCR_PCWE_ENABLE 0x10000000
3085#define SDR0_XCR_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28)
3086#define SDR0_XCR_PCWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01)
3087#define SDR0_XCR_PPIM_MASK 0x0F000000
3088#define SDR0_XCR_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24)
3089#define SDR0_XCR_PPIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
3090#define SDR0_XCR_PR64E_MASK 0x00800000
3091#define SDR0_XCR_PR64E_DISABLE 0x00000000
3092#define SDR0_XCR_PR64E_ENABLE 0x00800000
3093#define SDR0_XCR_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23)
3094#define SDR0_XCR_PR64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01)
3095#define SDR0_XCR_PXFS_MASK 0x00600000
3096#define SDR0_XCR_PXFS_HIGH 0x00000000
3097#define SDR0_XCR_PXFS_MED 0x00200000
3098#define SDR0_XCR_PXFS_LOW 0x00400000
3099#define SDR0_XCR_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21)
3100#define SDR0_XCR_PXFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03)
3101#define SDR0_XCR_PDM_MASK 0x00000040
3102#define SDR0_XCR_PDM_MULTIPOINT 0x00000000
3103#define SDR0_XCR_PDM_P2P 0x00000040
3104#define SDR0_XCR_PDM_ENCODE(n) ((((unsigned long)(n))&0x01)<<19)
3105#define SDR0_XCR_PDM_DECODE(n) ((((unsigned long)(n))>>19)&0x01)
wdenk00fe1612004-03-14 00:07:33 +0000[diff] [blame]3106
3107#define SDR0_PFC0_UART1_DSR_CTS_EN_MASK 0x00030000
wdenk6148e742005-04-03 20:55:38 +0000[diff] [blame]3108#define SDR0_PFC0_GEIE_MASK 0x00003E00
3109#define SDR0_PFC0_GEIE_TRE 0x00003E00
3110#define SDR0_PFC0_GEIE_NOTRE 0x00000000
3111#define SDR0_PFC0_TRE_MASK 0x00000100
3112#define SDR0_PFC0_TRE_DISABLE 0x00000000
3113#define SDR0_PFC0_TRE_ENABLE 0x00000100
3114#define SDR0_PFC0_TRE_ENCODE(n) ((((unsigned long)(n))&0x01)<<8)
3115#define SDR0_PFC0_TRE_DECODE(n) ((((unsigned long)(n))>>8)&0x01)
wdenk00fe1612004-03-14 00:07:33 +0000[diff] [blame]3116
wdenk6148e742005-04-03 20:55:38 +0000[diff] [blame]3117#define SDR0_PFC1_UART1_DSR_CTS_MASK 0x02000000
3118#define SDR0_PFC1_EPS_MASK 0x01C00000
3119#define SDR0_PFC1_EPS_GROUP0 0x00000000
3120#define SDR0_PFC1_EPS_GROUP1 0x00400000
3121#define SDR0_PFC1_EPS_GROUP2 0x00800000
3122#define SDR0_PFC1_EPS_GROUP3 0x00C00000
3123#define SDR0_PFC1_EPS_GROUP4 0x01000000
3124#define SDR0_PFC1_EPS_GROUP5 0x01400000
3125#define SDR0_PFC1_EPS_GROUP6 0x01800000
3126#define SDR0_PFC1_EPS_GROUP7 0x01C00000
3127#define SDR0_PFC1_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<22)
3128#define SDR0_PFC1_EPS_DECODE(n) ((((unsigned long)(n))>>22)&0x07)
3129#define SDR0_PFC1_RMII_MASK 0x00200000
3130#define SDR0_PFC1_RMII_100MBIT 0x00000000
3131#define SDR0_PFC1_RMII_10MBIT 0x00200000
3132#define SDR0_PFC1_RMII_ENCODE(n) ((((unsigned long)(n))&0x01)<<21)
3133#define SDR0_PFC1_RMII_DECODE(n) ((((unsigned long)(n))>>21)&0x01)
3134#define SDR0_PFC1_CTEMS_MASK 0x00100000
3135#define SDR0_PFC1_CTEMS_EMS 0x00000000
3136#define SDR0_PFC1_CTEMS_CPUTRACE 0x00100000
wdenk00fe1612004-03-14 00:07:33 +0000[diff] [blame]3137
wdenk6148e742005-04-03 20:55:38 +0000[diff] [blame]3138#define SDR0_MFR_TAH0_MASK 0x80000000
3139#define SDR0_MFR_TAH0_ENABLE 0x00000000
3140#define SDR0_MFR_TAH0_DISABLE 0x80000000
3141#define SDR0_MFR_TAH1_MASK 0x40000000
3142#define SDR0_MFR_TAH1_ENABLE 0x00000000
3143#define SDR0_MFR_TAH1_DISABLE 0x40000000
3144#define SDR0_MFR_PCM_MASK 0x20000000
3145#define SDR0_MFR_PCM_PPC440GX 0x00000000
3146#define SDR0_MFR_PCM_PPC440GP 0x20000000
3147#define SDR0_MFR_ECS_MASK 0x10000000
3148#define SDR0_MFR_ECS_INTERNAL 0x10000000
3149
Stefan Roese326c9712005-08-01 16:41:48 +0200[diff] [blame]3150#define SDR0_MFR_ETH0_CLK_SEL 0x08000000 /* Ethernet0 Clock Select */
3151#define SDR0_MFR_ETH1_CLK_SEL 0x04000000 /* Ethernet1 Clock Select */
3152#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
3153#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
3154#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
3155#define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */
3156#define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */
3157#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
3158#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
3159#define SDR0_MFR_ERRATA3_EN0 0x00800000
3160#define SDR0_MFR_ERRATA3_EN1 0x00400000
Stefan Roese42fbddd2006-09-07 11:51:23 +0200[diff] [blame]3161#if defined(CONFIG_440GX) /* test-only: only 440GX or 440SPE??? */
Stefan Roese326c9712005-08-01 16:41:48 +0200[diff] [blame]3162#define SDR0_MFR_PKT_REJ_MASK 0x00300000 /* Pkt Rej. Enable Mask */
3163#define SDR0_MFR_PKT_REJ_EN 0x00300000 /* Pkt Rej. Enable on both EMAC3 0-1 */
3164#define SDR0_MFR_PKT_REJ_EN0 0x00200000 /* Pkt Rej. Enable on EMAC3(0) */
3165#define SDR0_MFR_PKT_REJ_EN1 0x00100000 /* Pkt Rej. Enable on EMAC3(1) */
3166#define SDR0_MFR_PKT_REJ_POL 0x00080000 /* Packet Reject Polarity */
Stefan Roese42fbddd2006-09-07 11:51:23 +0200[diff] [blame]3167#endif
3168
3169#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
3170#define SDR0_PFC1_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<22)
3171#define SDR0_PFC1_EPS_DECODE(n) ((((unsigned long)(n))>>22)&0x07)
3172#define SDR0_PFC2_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<29)
3173#define SDR0_PFC2_EPS_DECODE(n) ((((unsigned long)(n))>>29)&0x07)
3174#endif
3175
3176#define SDR0_MFR_ECS_MASK 0x10000000
3177#define SDR0_MFR_ECS_INTERNAL 0x10000000
3178
3179#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
3180#define SDR0_SRST0 0x200
3181#define SDR0_SRST0_BGO 0x80000000 /* PLB to OPB bridge */
3182#define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */
3183#define SDR0_SRST0_EBC 0x20000000 /* External bus controller */
3184#define SDR0_SRST0_OPB 0x10000000 /* OPB arbiter */
3185#define SDR0_SRST0_UART0 0x08000000 /* Universal asynchronous receiver/transmitter 0 */
3186#define SDR0_SRST0_UART1 0x04000000 /* Universal asynchronous receiver/transmitter 1 */
3187#define SDR0_SRST0_IIC0 0x02000000 /* Inter integrated circuit 0 */
3188#define SDR0_SRST0_USB2H 0x01000000 /* USB2.0 Host */
3189#define SDR0_SRST0_GPIO 0x00800000 /* General purpose I/O */
3190#define SDR0_SRST0_GPT 0x00400000 /* General purpose timer */
3191#define SDR0_SRST0_DMC 0x00200000 /* DDR SDRAM memory controller */
3192#define SDR0_SRST0_PCI 0x00100000 /* PCI */
3193#define SDR0_SRST0_EMAC0 0x00080000 /* Ethernet media access controller 0 */
3194#define SDR0_SRST0_EMAC1 0x00040000 /* Ethernet media access controller 1 */
3195#define SDR0_SRST0_CPM0 0x00020000 /* Clock and power management */
3196#define SDR0_SRST0_ZMII 0x00010000 /* ZMII bridge */
3197#define SDR0_SRST0_UIC0 0x00008000 /* Universal interrupt controller 0 */
3198#define SDR0_SRST0_UIC1 0x00004000 /* Universal interrupt controller 1 */
3199#define SDR0_SRST0_IIC1 0x00002000 /* Inter integrated circuit 1 */
3200#define SDR0_SRST0_SCP 0x00001000 /* Serial communications port */
3201#define SDR0_SRST0_BGI 0x00000800 /* OPB to PLB bridge */
3202#define SDR0_SRST0_DMA 0x00000400 /* Direct memory access controller */
3203#define SDR0_SRST0_DMAC 0x00000200 /* DMA channel */
3204#define SDR0_SRST0_MAL 0x00000100 /* Media access layer */
3205#define SDR0_SRST0_USB2D 0x00000080 /* USB2.0 device */
3206#define SDR0_SRST0_GPTR 0x00000040 /* General purpose timer */
3207#define SDR0_SRST0_P4P3 0x00000010 /* PLB4 to PLB3 bridge */
3208#define SDR0_SRST0_P3P4 0x00000008 /* PLB3 to PLB4 bridge */
3209#define SDR0_SRST0_PLB3 0x00000004 /* PLB3 arbiter */
3210#define SDR0_SRST0_UART2 0x00000002 /* Universal asynchronous receiver/transmitter 2 */
3211#define SDR0_SRST0_UART3 0x00000001 /* Universal asynchronous receiver/transmitter 3 */
3212
3213#define SDR0_SRST1 0x201
3214#define SDR0_SRST1_NDFC 0x80000000 /* Nand flash controller */
3215#define SDR0_SRST1_OPBA1 0x40000000 /* OPB Arbiter attached to PLB4 */
3216#define SDR0_SRST1_P4OPB0 0x20000000 /* PLB4 to OPB Bridge0 */
3217#define SDR0_SRST1_PLB42OPB0 SDR0_SRST1_P4OPB0
3218#define SDR0_SRST1_DMA4 0x10000000 /* DMA to PLB4 */
3219#define SDR0_SRST1_DMA4CH 0x08000000 /* DMA Channel to PLB4 */
3220#define SDR0_SRST1_OPBA2 0x04000000 /* OPB Arbiter attached to PLB4 USB 2.0 Host */
3221#define SDR0_SRST1_OPB2PLB40 0x02000000 /* OPB to PLB4 Bridge attached to USB 2.0 Host */
3222#define SDR0_SRST1_PLB42OPB1 0x01000000 /* PLB4 to OPB Bridge attached to USB 2.0 Host */
3223#define SDR0_SRST1_CPM1 0x00800000 /* Clock and Power management 1 */
3224#define SDR0_SRST1_UIC2 0x00400000 /* Universal Interrupt Controller 2 */
3225#define SDR0_SRST1_CRYP0 0x00200000 /* Security Engine */
3226#define SDR0_SRST1_USB20PHY 0x00100000 /* USB 2.0 Phy */
3227#define SDR0_SRST1_USB2HUTMI 0x00080000 /* USB 2.0 Host UTMI Interface */
3228#define SDR0_SRST1_USB2HPHY 0x00040000 /* USB 2.0 Host Phy Interface */
3229#define SDR0_SRST1_SRAM0 0x00020000 /* Internal SRAM Controller */
3230#define SDR0_SRST1_RGMII0 0x00010000 /* RGMII Bridge */
3231#define SDR0_SRST1_ETHPLL 0x00008000 /* Ethernet PLL */
3232#define SDR0_SRST1_FPU 0x00004000 /* Floating Point Unit */
3233#define SDR0_SRST1_KASU0 0x00002000 /* Kasumi Engine */
3234
3235#else
Stefan Roese326c9712005-08-01 16:41:48 +0200[diff] [blame]3236
wdenk6148e742005-04-03 20:55:38 +0000[diff] [blame]3237#define SDR0_SRST_BGO 0x80000000
3238#define SDR0_SRST_PLB 0x40000000
3239#define SDR0_SRST_EBC 0x20000000
3240#define SDR0_SRST_OPB 0x10000000
3241#define SDR0_SRST_UART0 0x08000000
3242#define SDR0_SRST_UART1 0x04000000
3243#define SDR0_SRST_IIC0 0x02000000
3244#define SDR0_SRST_IIC1 0x01000000
3245#define SDR0_SRST_GPIO 0x00800000
3246#define SDR0_SRST_GPT 0x00400000
3247#define SDR0_SRST_DMC 0x00200000
3248#define SDR0_SRST_PCI 0x00100000
3249#define SDR0_SRST_EMAC0 0x00080000
3250#define SDR0_SRST_EMAC1 0x00040000
3251#define SDR0_SRST_CPM 0x00020000
3252#define SDR0_SRST_IMU 0x00010000
3253#define SDR0_SRST_UIC01 0x00008000
3254#define SDR0_SRST_UICB2 0x00004000
3255#define SDR0_SRST_SRAM 0x00002000
3256#define SDR0_SRST_EBM 0x00001000
3257#define SDR0_SRST_BGI 0x00000800
3258#define SDR0_SRST_DMA 0x00000400
3259#define SDR0_SRST_DMAC 0x00000200
3260#define SDR0_SRST_MAL 0x00000100
3261#define SDR0_SRST_ZMII 0x00000080
3262#define SDR0_SRST_GPTR 0x00000040
3263#define SDR0_SRST_PPM 0x00000020
3264#define SDR0_SRST_EMAC2 0x00000010
3265#define SDR0_SRST_EMAC3 0x00000008
3266#define SDR0_SRST_RGMII 0x00000001
wdenk00fe1612004-03-14 00:07:33 +0000[diff] [blame]3267
Stefan Roese42fbddd2006-09-07 11:51:23 +0200[diff] [blame]3268#endif
3269
wdenk00fe1612004-03-14 00:07:33 +0000[diff] [blame]3270/*-----------------------------------------------------------------------------+
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]3271| Clocking
3272+-----------------------------------------------------------------------------*/
Stefan Roese42fbddd2006-09-07 11:51:23 +0200[diff] [blame]3273#if !defined (CONFIG_440GX) && \
3274 !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \
3275 !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \
3276 !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]3277#define PLLSYS0_TUNE_MASK 0xffc00000 /* PLL TUNE bits */
3278#define PLLSYS0_FB_DIV_MASK 0x003c0000 /* Feedback divisor */
3279#define PLLSYS0_FWD_DIV_A_MASK 0x00038000 /* Forward divisor A */
3280#define PLLSYS0_FWD_DIV_B_MASK 0x00007000 /* Forward divisor B */
3281#define PLLSYS0_OPB_DIV_MASK 0x00000c00 /* OPB divisor */
3282#define PLLSYS0_EPB_DIV_MASK 0x00000300 /* EPB divisor */
3283#define PLLSYS0_EXTSL_MASK 0x00000080 /* PerClk feedback path */
3284#define PLLSYS0_RW_MASK 0x00000060 /* ROM width */
3285#define PLLSYS0_RL_MASK 0x00000010 /* ROM location */
3286#define PLLSYS0_ZMII_SEL_MASK 0x0000000c /* ZMII selection */
3287#define PLLSYS0_BYPASS_MASK 0x00000002 /* Bypass PLL */
3288#define PLLSYS0_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]3289
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]3290#define PLL_VCO_FREQ_MIN 500 /* Min VCO freq (MHz) */
3291#define PLL_VCO_FREQ_MAX 1000 /* Max VCO freq (MHz) */
3292#define PLL_CPU_FREQ_MAX 400 /* Max CPU freq (MHz) */
3293#define PLL_PLB_FREQ_MAX 133 /* Max PLB freq (MHz) */
Stefan Roeseb30f2a12005-08-08 12:42:22 +0200[diff] [blame]3294#else /* !CONFIG_440GX or CONFIG_440EP or CONFIG_440GR */
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]3295#define PLLSYS0_ENG_MASK 0x80000000 /* 0 = SysClk, 1 = PLL VCO */
3296#define PLLSYS0_SRC_MASK 0x40000000 /* 0 = PLL A, 1 = PLL B */
3297#define PLLSYS0_SEL_MASK 0x38000000 /* 0 = PLL, 1 = CPU, 5 = PerClk */
3298#define PLLSYS0_TUNE_MASK 0x07fe0000 /* PLL Tune bits */
3299#define PLLSYS0_FB_DIV_MASK 0x0001f000 /* Feedback divisor */
3300#define PLLSYS0_FWD_DIV_A_MASK 0x00000f00 /* Fwd Div A */
3301#define PLLSYS0_FWD_DIV_B_MASK 0x000000e0 /* Fwd Div B */
3302#define PLLSYS0_PRI_DIV_B_MASK 0x0000001c /* PLL Primary Divisor B */
3303#define PLLSYS0_OPB_DIV_MASK 0x00000003 /* OPB Divisor */
3304
Stefan Roese326c9712005-08-01 16:41:48 +0200[diff] [blame]3305#define PLLC_ENG_MASK 0x20000000 /* PLL primary forward divisor source */
3306#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */
3307#define PLLD_FBDV_MASK 0x1f000000 /* PLL Feedback Divisor */
3308#define PLLD_FWDVA_MASK 0x000f0000 /* PLL Forward Divisor A */
3309#define PLLD_FWDVB_MASK 0x00000700 /* PLL Forward Divisor B */
3310#define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */
3311
3312#define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */
3313#define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */
3314#define PRADV_MASK 0x07000000 /* Primary Divisor A */
3315#define PRBDV_MASK 0x07000000 /* Primary Divisor B */
3316#define SPCID_MASK 0x03000000 /* Sync PCI Divisor */
3317
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]3318#define PLL_VCO_FREQ_MIN 500 /* Min VCO freq (MHz) */
3319#define PLL_VCO_FREQ_MAX 1000 /* Max VCO freq (MHz) */
3320#define PLL_CPU_FREQ_MAX 400 /* Max CPU freq (MHz) */
3321#define PLL_PLB_FREQ_MAX 133 /* Max PLB freq (MHz) */
3322
3323/* Strap 1 Register */
3324#define PLLSYS1_LF_DIV_MASK 0xfc000000 /* PLL Local Feedback Divisor */
3325#define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
3326#define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */
3327#define PLLSYS1_RW_MASK 0x00300000 /* ROM width */
3328#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */
3329#define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */
3330#define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */
3331#define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */
3332#define PLLSYS1_PCWE_MASK 0x00008000 /* PCI local cpu wait enable */
3333#define PLLSYS1_PPIM_MASK 0x00007800 /* PCI inbound map */
3334#define PLLSYS1_PR64E_MASK 0x00000400 /* PCI init Req64 enable */
3335#define PLLSYS1_PXFS_MASK 0x00000300 /* PCI-X Freq Sel */
3336#define PLLSYS1_RSVD_MASK 0x00000080 /* RSVD */
3337#define PLLSYS1_PDM_MASK 0x00000040 /* PCI-X Driver Mode */
3338#define PLLSYS1_EPS_MASK 0x00000038 /* Ethernet Pin Select */
3339#define PLLSYS1_RMII_MASK 0x00000004 /* RMII Mode */
3340#define PLLSYS1_TRE_MASK 0x00000002 /* GPIO Trace Enable */
3341#define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */
Stefan Roeseb30f2a12005-08-08 12:42:22 +0200[diff] [blame]3342#endif /* CONFIG_440GX */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]3343
Stefan Roese42fbddd2006-09-07 11:51:23 +0200[diff] [blame]3344#if defined (CONFIG_440EPX) || defined (CONFIG_440GRX)
3345/*--------------------------------------*/
3346#define CPR0_PLLC 0x40
3347#define CPR0_PLLC_RST_MASK 0x80000000
3348#define CPR0_PLLC_RST_PLLLOCKED 0x00000000
3349#define CPR0_PLLC_RST_PLLRESET 0x80000000
3350#define CPR0_PLLC_ENG_MASK 0x40000000
3351#define CPR0_PLLC_ENG_DISABLE 0x00000000
3352#define CPR0_PLLC_ENG_ENABLE 0x40000000
3353#define CPR0_PLLC_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
3354#define CPR0_PLLC_ENG_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
3355#define CPR0_PLLC_SRC_MASK 0x20000000
3356#define CPR0_PLLC_SRC_PLLOUTA 0x00000000
3357#define CPR0_PLLC_SRC_PLLOUTB 0x20000000
3358#define CPR0_PLLC_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
3359#define CPR0_PLLC_SRC_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
3360#define CPR0_PLLC_SEL_MASK 0x07000000
3361#define CPR0_PLLC_SEL_PLL 0x00000000
3362#define CPR0_PLLC_SEL_CPU 0x01000000
3363#define CPR0_PLLC_SEL_PER 0x05000000
3364#define CPR0_PLLC_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
3365#define CPR0_PLLC_SEL_DECODE(n) ((((unsigned long)(n))>>24)&0x07)
3366#define CPR0_PLLC_TUNE_MASK 0x000003FF
3367#define CPR0_PLLC_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
3368#define CPR0_PLLC_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
3369/*--------------------------------------*/
3370#define CPR0_PLLD 0x60
3371#define CPR0_PLLD_FBDV_MASK 0x1F000000
3372#define CPR0_PLLD_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
3373#define CPR0_PLLD_FBDV_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x1F)+1)
3374#define CPR0_PLLD_FWDVA_MASK 0x000F0000
3375#define CPR0_PLLD_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<16)
3376#define CPR0_PLLD_FWDVA_DECODE(n) ((((((unsigned long)(n))>>16)-1)&0x0F)+1)
3377#define CPR0_PLLD_FWDVB_MASK 0x00000700
3378#define CPR0_PLLD_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<8)
3379#define CPR0_PLLD_FWDVB_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x07)+1)
3380#define CPR0_PLLD_LFBDV_MASK 0x0000003F
3381#define CPR0_PLLD_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0)
3382#define CPR0_PLLD_LFBDV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x3F)+1)
3383/*--------------------------------------*/
3384#define CPR0_PRIMAD 0x80
3385#define CPR0_PRIMAD_PRADV0_MASK 0x07000000
3386#define CPR0_PRIMAD_PRADV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
3387#define CPR0_PRIMAD_PRADV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1)
3388/*--------------------------------------*/
3389#define CPR0_PRIMBD 0xA0
3390#define CPR0_PRIMBD_PRBDV0_MASK 0x07000000
3391#define CPR0_PRIMBD_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
3392#define CPR0_PRIMBD_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1)
3393/*--------------------------------------*/
3394#if 0
3395#define CPR0_CPM0_ER 0xB0 /* CPM Enable Register */
3396#define CPR0_CPM0_FR 0xB1 /* CPM Force Register */
3397#define CPR0_CPM0_SR 0xB2 /* CPM Status Register */
3398#define CPR0_CPM0_IIC0 0x80000000 /* Inter-Intergrated Circuit0 */
3399#define CPR0_CPM0_IIC1 0x40000000 /* Inter-Intergrated Circuit1 */
3400#define CPR0_CPM0_PCI 0x20000000 /* Peripheral Component Interconnect */
3401#define CPR0_CPM0_USB1H 0x08000000 /* USB1.1 Host */
3402#define CPR0_CPM0_FPU 0x04000000 /* PPC440 FPU */
3403#define CPR0_CPM0_CPU 0x02000000 /* PPC440x5 Processor Core */
3404#define CPR0_CPM0_DMA 0x01000000 /* Direct Memory Access Controller */
3405#define CPR0_CPM0_BGO 0x00800000 /* PLB to OPB Bridge */
3406#define CPR0_CPM0_BGI 0x00400000 /* OPB to PLB Bridge */
3407#define CPR0_CPM0_EBC 0x00200000 /* External Bus Controller */
3408#define CPR0_CPM0_NDFC 0x00100000 /* Nand Flash Controller */
3409#define CPR0_CPM0_MADMAL 0x00080000 /* DDR SDRAM Controller or MADMAL ??? */
3410#define CPR0_CPM0_DMC 0x00080000 /* DDR SDRAM Controller or MADMAL ??? */
3411#define CPR0_CPM0_PLB4 0x00040000 /* PLB4 Arbiter */
3412#define CPR0_CPM0_PLB4x3x 0x00020000 /* PLB4 to PLB3 */
3413#define CPR0_CPM0_PLB3x4x 0x00010000 /* PLB3 to PLB4 */
3414#define CPR0_CPM0_PLB3 0x00008000 /* PLB3 Arbiter */
3415#define CPR0_CPM0_PPM 0x00002000 /* PLB Performance Monitor */
3416#define CPR0_CPM0_UIC1 0x00001000 /* Universal Interrupt Controller 1 */
3417#define CPR0_CPM0_GPIO 0x00000800 /* General Purpose IO */
3418#define CPR0_CPM0_GPT 0x00000400 /* General Purpose Timer */
3419#define CPR0_CPM0_UART0 0x00000200 /* Universal Asynchronous Rcver/Xmitter 0 */
3420#define CPR0_CPM0_UART1 0x00000100 /* Universal Asynchronous Rcver/Xmitter 1 */
3421#define CPR0_CPM0_UIC0 0x00000080 /* Universal Interrupt Controller 0 */
3422#define CPR0_CPM0_TMRCLK 0x00000040 /* CPU Timer */
3423#define CPR0_CPM0_EMC0 0x00000020 /* Ethernet 0 */
3424#define CPR0_CPM0_EMC1 0x00000010 /* Ethernet 1 */
3425#define CPR0_CPM0_UART2 0x00000008 /* Universal Asynchronous Rcver/Xmitter 2 */
3426#define CPR0_CPM0_UART3 0x00000004 /* Universal Asynchronous Rcver/Xmitter 3 */
3427#define CPR0_CPM0_USB2D 0x00000002 /* USB2.0 Device */
3428#define CPR0_CPM0_USB2H 0x00000001 /* USB2.0 Host */
3429#endif
3430/*--------------------------------------*/
3431#define CPR0_OPBD 0xC0
3432#define CPR0_OPBD_OPBDV0_MASK 0x03000000
3433#define CPR0_OPBD_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
3434#define CPR0_OPBD_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
3435/*--------------------------------------*/
3436#define CPR0_PERD 0xE0
3437#define CPR0_PERD_PERDV0_MASK 0x07000000
3438#define CPR0_PERD_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
3439#define CPR0_PERD_PERDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1)
3440/*--------------------------------------*/
3441#define CPR0_MALD 0x100
3442#define CPR0_MALD_MALDV0_MASK 0x03000000
3443#define CPR0_MALD_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
3444#define CPR0_MALD_MALDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
3445/*--------------------------------------*/
3446#define CPR0_SPCID 0x120
3447#define CPR0_SPCID_SPCIDV0_MASK 0x03000000
3448#define CPR0_SPCID_SPCIDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
3449#define CPR0_SPCID_SPCIDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
3450/*--------------------------------------*/
3451#define CPR0_ICFG 0x140
3452#define CPR0_ICFG_RLI_MASK 0x80000000
3453#define CPR0_ICFG_RLI_RESETCPR 0x00000000
3454#define CPR0_ICFG_RLI_PRESERVECPR 0x80000000
3455#define CPR0_ICFG_ICS_MASK 0x00000007
3456#endif /* defined (CONFIG_440EPX) || defined (CONFIG_440GRX) */
3457
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]3458/*-----------------------------------------------------------------------------
3459| IIC Register Offsets
3460'----------------------------------------------------------------------------*/
wdenk6148e742005-04-03 20:55:38 +0000[diff] [blame]3461#define IICMDBUF 0x00
3462#define IICSDBUF 0x02
3463#define IICLMADR 0x04
3464#define IICHMADR 0x05
3465#define IICCNTL 0x06
3466#define IICMDCNTL 0x07
3467#define IICSTS 0x08
3468#define IICEXTSTS 0x09
3469#define IICLSADR 0x0A
3470#define IICHSADR 0x0B
3471#define IICCLKDIV 0x0C
3472#define IICINTRMSK 0x0D
3473#define IICXFRCNT 0x0E
3474#define IICXTCNTLSS 0x0F
3475#define IICDIRECTCNTL 0x10
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]3476
3477/*-----------------------------------------------------------------------------
3478| UART Register Offsets
3479'----------------------------------------------------------------------------*/
wdenk6148e742005-04-03 20:55:38 +0000[diff] [blame]3480#define DATA_REG 0x00
3481#define DL_LSB 0x00
3482#define DL_MSB 0x01
3483#define INT_ENABLE 0x01
3484#define FIFO_CONTROL 0x02
3485#define LINE_CONTROL 0x03
3486#define MODEM_CONTROL 0x04
3487#define LINE_STATUS 0x05
3488#define MODEM_STATUS 0x06
3489#define SCRATCH 0x07
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]3490
3491/*-----------------------------------------------------------------------------
3492| PCI Internal Registers et. al. (accessed via plb)
3493+----------------------------------------------------------------------------*/
wdenk00fe1612004-03-14 00:07:33 +0000[diff] [blame]3494#define PCIX0_CFGADR (CFG_PCI_BASE + 0x0ec00000)
3495#define PCIX0_CFGDATA (CFG_PCI_BASE + 0x0ec00004)
3496#define PCIX0_CFGBASE (CFG_PCI_BASE + 0x0ec80000)
3497#define PCIX0_IOBASE (CFG_PCI_BASE + 0x08000000)
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]3498
Stefan Roese42fbddd2006-09-07 11:51:23 +0200[diff] [blame]3499#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
3500 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
Stefan Roese326c9712005-08-01 16:41:48 +0200[diff] [blame]3501
3502/* PCI Local Configuration Registers
3503 --------------------------------- */
3504#define PCI_MMIO_LCR_BASE (CFG_PCI_BASE + 0x0f400000) /* Real => 0x0EF400000 */
3505
3506/* PCI Master Local Configuration Registers */
3507#define PCIX0_PMM0LA (PCI_MMIO_LCR_BASE + 0x00) /* PMM0 Local Address */
3508#define PCIX0_PMM0MA (PCI_MMIO_LCR_BASE + 0x04) /* PMM0 Mask/Attribute */
3509#define PCIX0_PMM0PCILA (PCI_MMIO_LCR_BASE + 0x08) /* PMM0 PCI Low Address */
3510#define PCIX0_PMM0PCIHA (PCI_MMIO_LCR_BASE + 0x0C) /* PMM0 PCI High Address */
3511#define PCIX0_PMM1LA (PCI_MMIO_LCR_BASE + 0x10) /* PMM1 Local Address */
3512#define PCIX0_PMM1MA (PCI_MMIO_LCR_BASE + 0x14) /* PMM1 Mask/Attribute */
3513#define PCIX0_PMM1PCILA (PCI_MMIO_LCR_BASE + 0x18) /* PMM1 PCI Low Address */
3514#define PCIX0_PMM1PCIHA (PCI_MMIO_LCR_BASE + 0x1C) /* PMM1 PCI High Address */
3515#define PCIX0_PMM2LA (PCI_MMIO_LCR_BASE + 0x20) /* PMM2 Local Address */
3516#define PCIX0_PMM2MA (PCI_MMIO_LCR_BASE + 0x24) /* PMM2 Mask/Attribute */
3517#define PCIX0_PMM2PCILA (PCI_MMIO_LCR_BASE + 0x28) /* PMM2 PCI Low Address */
3518#define PCIX0_PMM2PCIHA (PCI_MMIO_LCR_BASE + 0x2C) /* PMM2 PCI High Address */
3519
3520/* PCI Target Local Configuration Registers */
3521#define PCIX0_PTM1MS (PCI_MMIO_LCR_BASE + 0x30) /* PTM1 Memory Size/Attribute */
3522#define PCIX0_PTM1LA (PCI_MMIO_LCR_BASE + 0x34) /* PTM1 Local Addr. Reg */
3523#define PCIX0_PTM2MS (PCI_MMIO_LCR_BASE + 0x38) /* PTM2 Memory Size/Attribute */
3524#define PCIX0_PTM2LA (PCI_MMIO_LCR_BASE + 0x3C) /* PTM2 Local Addr. Reg */
3525
3526#else
3527
wdenk00fe1612004-03-14 00:07:33 +0000[diff] [blame]3528#define PCIX0_VENDID (PCIX0_CFGBASE + PCI_VENDOR_ID )
3529#define PCIX0_DEVID (PCIX0_CFGBASE + PCI_DEVICE_ID )
3530#define PCIX0_CMD (PCIX0_CFGBASE + PCI_COMMAND )
3531#define PCIX0_STATUS (PCIX0_CFGBASE + PCI_STATUS )
3532#define PCIX0_REVID (PCIX0_CFGBASE + PCI_REVISION_ID )
3533#define PCIX0_CLS (PCIX0_CFGBASE + PCI_CLASS_CODE)
3534#define PCIX0_CACHELS (PCIX0_CFGBASE + PCI_CACHE_LINE_SIZE )
3535#define PCIX0_LATTIM (PCIX0_CFGBASE + PCI_LATENCY_TIMER )
3536#define PCIX0_HDTYPE (PCIX0_CFGBASE + PCI_HEADER_TYPE )
3537#define PCIX0_BIST (PCIX0_CFGBASE + PCI_BIST )
3538#define PCIX0_BAR0 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_0 )
3539#define PCIX0_BAR1 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_1 )
3540#define PCIX0_BAR2 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_2 )
3541#define PCIX0_BAR3 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_3 )
3542#define PCIX0_BAR4 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_4 )
3543#define PCIX0_BAR5 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_5 )
3544#define PCIX0_CISPTR (PCIX0_CFGBASE + PCI_CARDBUS_CIS )
3545#define PCIX0_SBSYSVID (PCIX0_CFGBASE + PCI_SUBSYSTEM_VENDOR_ID )
3546#define PCIX0_SBSYSID (PCIX0_CFGBASE + PCI_SUBSYSTEM_ID )
3547#define PCIX0_EROMBA (PCIX0_CFGBASE + PCI_ROM_ADDRESS )
3548#define PCIX0_CAP (PCIX0_CFGBASE + PCI_CAPABILITY_LIST )
3549#define PCIX0_RES0 (PCIX0_CFGBASE + 0x0035 )
3550#define PCIX0_RES1 (PCIX0_CFGBASE + 0x0036 )
3551#define PCIX0_RES2 (PCIX0_CFGBASE + 0x0038 )
3552#define PCIX0_INTLN (PCIX0_CFGBASE + PCI_INTERRUPT_LINE )
3553#define PCIX0_INTPN (PCIX0_CFGBASE + PCI_INTERRUPT_PIN )
3554#define PCIX0_MINGNT (PCIX0_CFGBASE + PCI_MIN_GNT )
3555#define PCIX0_MAXLTNCY (PCIX0_CFGBASE + PCI_MAX_LAT )
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]3556
wdenk6148e742005-04-03 20:55:38 +0000[diff] [blame]3557#define PCIX0_BRDGOPT1 (PCIX0_CFGBASE + 0x0040)
3558#define PCIX0_BRDGOPT2 (PCIX0_CFGBASE + 0x0044)
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]3559
wdenk00fe1612004-03-14 00:07:33 +0000[diff] [blame]3560#define PCIX0_POM0LAL (PCIX0_CFGBASE + 0x0068)
3561#define PCIX0_POM0LAH (PCIX0_CFGBASE + 0x006c)
3562#define PCIX0_POM0SA (PCIX0_CFGBASE + 0x0070)
wdenk6148e742005-04-03 20:55:38 +0000[diff] [blame]3563#define PCIX0_POM0PCIAL (PCIX0_CFGBASE + 0x0074)
3564#define PCIX0_POM0PCIAH (PCIX0_CFGBASE + 0x0078)
wdenk00fe1612004-03-14 00:07:33 +0000[diff] [blame]3565#define PCIX0_POM1LAL (PCIX0_CFGBASE + 0x007c)
3566#define PCIX0_POM1LAH (PCIX0_CFGBASE + 0x0080)
3567#define PCIX0_POM1SA (PCIX0_CFGBASE + 0x0084)
wdenk6148e742005-04-03 20:55:38 +0000[diff] [blame]3568#define PCIX0_POM1PCIAL (PCIX0_CFGBASE + 0x0088)
3569#define PCIX0_POM1PCIAH (PCIX0_CFGBASE + 0x008c)
wdenk00fe1612004-03-14 00:07:33 +0000[diff] [blame]3570#define PCIX0_POM2SA (PCIX0_CFGBASE + 0x0090)
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]3571
wdenk00fe1612004-03-14 00:07:33 +0000[diff] [blame]3572#define PCIX0_PIM0SA (PCIX0_CFGBASE + 0x0098)
3573#define PCIX0_PIM0LAL (PCIX0_CFGBASE + 0x009c)
3574#define PCIX0_PIM0LAH (PCIX0_CFGBASE + 0x00a0)
3575#define PCIX0_PIM1SA (PCIX0_CFGBASE + 0x00a4)
3576#define PCIX0_PIM1LAL (PCIX0_CFGBASE + 0x00a8)
3577#define PCIX0_PIM1LAH (PCIX0_CFGBASE + 0x00ac)
3578#define PCIX0_PIM2SA (PCIX0_CFGBASE + 0x00b0)
3579#define PCIX0_PIM2LAL (PCIX0_CFGBASE + 0x00b4)
3580#define PCIX0_PIM2LAH (PCIX0_CFGBASE + 0x00b8)
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]3581
wdenk00fe1612004-03-14 00:07:33 +0000[diff] [blame]3582#define PCIX0_STS (PCIX0_CFGBASE + 0x00e0)
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]3583
Stefan Roeseb30f2a12005-08-08 12:42:22 +0200[diff] [blame]3584#endif /* !defined(CONFIG_440EP) !defined(CONFIG_440GR) */
Stefan Roese326c9712005-08-01 16:41:48 +0200[diff] [blame]3585
Stefan Roese42fbddd2006-09-07 11:51:23 +0200[diff] [blame]3586#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
3587
3588/* USB2.0 Device */
3589#define USB2D0_BASE CFG_USB2D0_BASE
3590
3591#define USB2D0_INTRIN (USB2D0_BASE + 0x00000000)
3592
3593#define USB2D0_INTRIN (USB2D0_BASE + 0x00000000) /* Interrupt register for Endpoint 0 plus IN Endpoints 1 to 3 */
3594#define USB2D0_POWER (USB2D0_BASE + 0x00000000) /* Power management register */
3595#define USB2D0_FADDR (USB2D0_BASE + 0x00000000) /* Function address register */
3596#define USB2D0_INTRINE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for USB2D0_INTRIN */
3597#define USB2D0_INTROUT (USB2D0_BASE + 0x00000000) /* Interrupt register for OUT Endpoints 1 to 3 */
3598#define USB2D0_INTRUSBE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for USB2D0_INTRUSB */
3599#define USB2D0_INTRUSB (USB2D0_BASE + 0x00000000) /* Interrupt register for common USB interrupts */
3600#define USB2D0_INTROUTE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for IntrOut */
3601#define USB2D0_TSTMODE (USB2D0_BASE + 0x00000000) /* Enables the USB 2.0 test modes */
3602#define USB2D0_INDEX (USB2D0_BASE + 0x00000000) /* Index register for selecting the Endpoint status/control registers */
3603#define USB2D0_FRAME (USB2D0_BASE + 0x00000000) /* Frame number */
3604#define USB2D0_INCSR0 (USB2D0_BASE + 0x00000000) /* Control Status register for Endpoint 0. (Index register set to select Endpoint 0) */
3605#define USB2D0_INCSR (USB2D0_BASE + 0x00000000) /* Control Status register for IN Endpoint. (Index register set to select Endpoints 13) */
3606#define USB2D0_INMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet size for IN Endpoint. (Index register set to select Endpoints 13) */
3607#define USB2D0_OUTCSR (USB2D0_BASE + 0x00000000) /* Control Status register for OUT Endpoint. (Index register set to select Endpoints 13) */
3608#define USB2D0_OUTMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet size for OUT Endpoint. (Index register set to select Endpoints 13) */
3609#define USB2D0_OUTCOUNT0 (USB2D0_BASE + 0x00000000) /* Number of received bytes in Endpoint 0 FIFO. (Index register set to select Endpoint 0) */
3610#define USB2D0_OUTCOUNT (USB2D0_BASE + 0x00000000) /* Number of bytes in OUT Endpoint FIFO. (Index register set to select Endpoints 13) */
3611#endif
3612
Stefan Roese326c9712005-08-01 16:41:48 +0200[diff] [blame]3613/******************************************************************************
3614 * GPIO macro register defines
3615 ******************************************************************************/
Stefan Roesebad41112007-03-01 21:11:36 +0100[diff] [blame]3616#if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \
3617 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
Stefan Roese9eba0c82006-06-02 16:18:04 +0200[diff] [blame]3618#define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000700)
Stefan Roesec443fe92005-11-22 13:20:42 +0100[diff] [blame]3619
Stefan Roese9eba0c82006-06-02 16:18:04 +0200[diff] [blame]3620#define GPIO0_OR (GPIO0_BASE+0x0)
3621#define GPIO0_TCR (GPIO0_BASE+0x4)
3622#define GPIO0_ODR (GPIO0_BASE+0x18)
3623#define GPIO0_IR (GPIO0_BASE+0x1C)
Stefan Roesec443fe92005-11-22 13:20:42 +0100[diff] [blame]3624#endif /* CONFIG_440GP */
3625
Stefan Roese42fbddd2006-09-07 11:51:23 +0200[diff] [blame]3626#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
3627 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
Stefan Roese9eba0c82006-06-02 16:18:04 +0200[diff] [blame]3628#define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000B00)
3629#define GPIO1_BASE (CFG_PERIPHERAL_BASE+0x00000C00)
3630
Stefan Roese9eba0c82006-06-02 16:18:04 +0200[diff] [blame]3631#define GPIO0_OR (GPIO0_BASE+0x0)
3632#define GPIO0_TCR (GPIO0_BASE+0x4)
3633#define GPIO0_OSRL (GPIO0_BASE+0x8)
3634#define GPIO0_OSRH (GPIO0_BASE+0xC)
3635#define GPIO0_TSRL (GPIO0_BASE+0x10)
3636#define GPIO0_TSRH (GPIO0_BASE+0x14)
3637#define GPIO0_ODR (GPIO0_BASE+0x18)
3638#define GPIO0_IR (GPIO0_BASE+0x1C)
3639#define GPIO0_RR1 (GPIO0_BASE+0x20)
3640#define GPIO0_RR2 (GPIO0_BASE+0x24)
3641#define GPIO0_RR3 (GPIO0_BASE+0x28)
3642#define GPIO0_ISR1L (GPIO0_BASE+0x30)
3643#define GPIO0_ISR1H (GPIO0_BASE+0x34)
3644#define GPIO0_ISR2L (GPIO0_BASE+0x38)
3645#define GPIO0_ISR2H (GPIO0_BASE+0x3C)
3646#define GPIO0_ISR3L (GPIO0_BASE+0x40)
3647#define GPIO0_ISR3H (GPIO0_BASE+0x44)
3648
3649#define GPIO1_OR (GPIO1_BASE+0x0)
3650#define GPIO1_TCR (GPIO1_BASE+0x4)
3651#define GPIO1_OSRL (GPIO1_BASE+0x8)
3652#define GPIO1_OSRH (GPIO1_BASE+0xC)
3653#define GPIO1_TSRL (GPIO1_BASE+0x10)
3654#define GPIO1_TSRH (GPIO1_BASE+0x14)
3655#define GPIO1_ODR (GPIO1_BASE+0x18)
3656#define GPIO1_IR (GPIO1_BASE+0x1C)
3657#define GPIO1_RR1 (GPIO1_BASE+0x20)
3658#define GPIO1_RR2 (GPIO1_BASE+0x24)
3659#define GPIO1_RR3 (GPIO1_BASE+0x28)
3660#define GPIO1_ISR1L (GPIO1_BASE+0x30)
3661#define GPIO1_ISR1H (GPIO1_BASE+0x34)
3662#define GPIO1_ISR2L (GPIO1_BASE+0x38)
3663#define GPIO1_ISR2H (GPIO1_BASE+0x3C)
3664#define GPIO1_ISR3L (GPIO1_BASE+0x40)
3665#define GPIO1_ISR3H (GPIO1_BASE+0x44)
Stefan Roese326c9712005-08-01 16:41:48 +0200[diff] [blame]3666#endif
3667
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]3668#ifndef __ASSEMBLY__
3669
Stefan Roese0dd0e642007-07-31 08:37:01 +0200[diff] [blame]3670static inline u32 get_mcsr(void)
3671{
3672 u32 val;
3673
3674 asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
3675 return val;
3676}
3677
3678static inline void set_mcsr(u32 val)
3679{
3680 asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
3681}
3682
wdenk544e9732004-02-06 23:19:44 +0000[diff] [blame]3683#endif /* _ASMLANGUAGE */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]3684
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]3685#endif /* __PPC440_H__ */