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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Stelian Pop69c925f2008-05-08 18:52:23 +02002/*
3 * (C) Copyright 2007-2008
Stelian Pop5ee0c7f2011-11-01 00:00:39 +01004 * Stelian Pop <stelian@popies.net>
Stelian Pop69c925f2008-05-08 18:52:23 +02005 * Lead Tech Design <www.leadtechdesign.com>
6 *
7 * Configuation settings for the AT91SAM9263EK board.
Stelian Pop69c925f2008-05-08 18:52:23 +02008 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
Simon Glassfb64e362020-05-10 11:40:09 -060013#include <linux/stringify.h>
14
Xu, Hong504e4e12011-06-10 21:31:26 +000015/*
16 * SoC must be defined first, before hardware.h is included.
17 * In this case SoC is defined in boards.cfg.
18 */
19#include <asm/hardware.h>
20
Stelian Pop69c925f2008-05-08 18:52:23 +020021/* ARM asynchronous clock */
Xu, Hong504e4e12011-06-10 21:31:26 +000022#define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
23#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
Stelian Pop69c925f2008-05-08 18:52:23 +020024
Jean-Christophe PLAGNIOL-VILLARD32774732009-06-13 12:48:36 +020025#ifndef CONFIG_SYS_USE_BOOT_NORFLASH
Xu, Hong504e4e12011-06-10 21:31:26 +000026#else
27#define CONFIG_SYS_USE_NORFLASH
Jean-Christophe PLAGNIOL-VILLARD32774732009-06-13 12:48:36 +020028#endif
Stelian Pop69c925f2008-05-08 18:52:23 +020029
30/*
31 * Hardware drivers
32 */
Xu, Hong504e4e12011-06-10 21:31:26 +000033#define CONFIG_ATMEL_LEGACY
Stelian Pop69c925f2008-05-08 18:52:23 +020034
Stelian Pope068a9b2008-05-08 14:52:31 +020035/* LCD */
Stelian Pope068a9b2008-05-08 14:52:31 +020036#define LCD_BPP LCD_COLOR8
37#define CONFIG_LCD_LOGO 1
38#undef LCD_TEST_PATTERN
39#define CONFIG_LCD_INFO 1
40#define CONFIG_LCD_INFO_BELOW_LOGO 1
Stelian Pope068a9b2008-05-08 14:52:31 +020041#define CONFIG_ATMEL_LCD 1
42#define CONFIG_ATMEL_LCD_BGR555 1
Stelian Pope068a9b2008-05-08 14:52:31 +020043
Stelian Pop69c925f2008-05-08 18:52:23 +020044/* SDRAM */
Xu, Hong504e4e12011-06-10 21:31:26 +000045#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
46#define CONFIG_SYS_SDRAM_SIZE 0x04000000
47
48#define CONFIG_SYS_INIT_SP_ADDR \
Wenyou Yanga4952c12017-04-18 15:31:00 +080049 (ATMEL_BASE_SRAM1 + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
Stelian Pop69c925f2008-05-08 18:52:23 +020050
Stelian Pop69c925f2008-05-08 18:52:23 +020051/* NOR flash, if populated */
Jean-Christophe PLAGNIOL-VILLARD32774732009-06-13 12:48:36 +020052#ifdef CONFIG_SYS_USE_NORFLASH
Jean-Christophe PLAGNIOL-VILLARD32774732009-06-13 12:48:36 +020053#define PHYS_FLASH_1 0x10000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020054#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
55#define CONFIG_SYS_MAX_FLASH_SECT 256
Jean-Christophe PLAGNIOL-VILLARD32774732009-06-13 12:48:36 +020056
57#define CONFIG_SYS_MONITOR_SEC 1:0-3
58#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
59#define CONFIG_SYS_MONITOR_LEN (256 << 10)
Jean-Christophe PLAGNIOL-VILLARD32774732009-06-13 12:48:36 +020060
61/* Address and size of Primary Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD32774732009-06-13 12:48:36 +020062
Jean-Christophe PLAGNIOL-VILLARD32774732009-06-13 12:48:36 +020063#define CONFIG_EXTRA_ENV_SETTINGS \
Marek Vasutfd5ba892012-09-23 17:41:23 +020064 "monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
Jean-Christophe PLAGNIOL-VILLARD32774732009-06-13 12:48:36 +020065 "update=" \
66 "protect off ${monitor_base} +${filesize};" \
67 "erase ${monitor_base} +${filesize};" \
Andreas Bießmann46a8ab72012-06-28 02:32:32 +000068 "cp.b ${fileaddr} ${monitor_base} ${filesize};" \
Jean-Christophe PLAGNIOL-VILLARD32774732009-06-13 12:48:36 +020069 "protect on ${monitor_base} +${filesize}\0"
70
71#ifndef CONFIG_SKIP_LOWLEVEL_INIT
72#define MASTER_PLL_MUL 171
73#define MASTER_PLL_DIV 14
Jens Scharsigc3c10ea2010-02-03 22:47:18 +010074#define MASTER_PLL_OUT 3
Jean-Christophe PLAGNIOL-VILLARD32774732009-06-13 12:48:36 +020075
76/* clocks */
77#define CONFIG_SYS_MOR_VAL \
Jens Scharsigc3c10ea2010-02-03 22:47:18 +010078 (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
79#define CONFIG_SYS_PLLAR_VAL \
80 (AT91_PMC_PLLAR_29 | \
81 AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \
82 AT91_PMC_PLLXR_PLLCOUNT(63) | \
Wolfgang Denk62fb2b42021-09-27 17:42:39 +020083 AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \
Jens Scharsigc3c10ea2010-02-03 22:47:18 +010084 AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
Jean-Christophe PLAGNIOL-VILLARD32774732009-06-13 12:48:36 +020085
86/* PCK/2 = MCK Master Clock from PLLA */
87#define CONFIG_SYS_MCKR1_VAL \
Jens Scharsigc3c10ea2010-02-03 22:47:18 +010088 (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \
89 AT91_PMC_MCKR_MDIV_2)
90
Jean-Christophe PLAGNIOL-VILLARD32774732009-06-13 12:48:36 +020091/* PCK/2 = MCK Master Clock from PLLA */
92#define CONFIG_SYS_MCKR2_VAL \
Wolfgang Denk62fb2b42021-09-27 17:42:39 +020093 (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \
Jens Scharsigc3c10ea2010-02-03 22:47:18 +010094 AT91_PMC_MCKR_MDIV_2)
Jean-Christophe PLAGNIOL-VILLARD32774732009-06-13 12:48:36 +020095
96/* define PDC[31:16] as DATA[31:16] */
97#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
98/* no pull-up for D[31:16] */
99#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
100/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
Jens Scharsigc3c10ea2010-02-03 22:47:18 +0100101#define CONFIG_SYS_MATRIX_EBICSA_VAL \
102 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \
103 AT91_MATRIX_CSA_EBI_CS1A)
Jean-Christophe PLAGNIOL-VILLARD32774732009-06-13 12:48:36 +0200104
105/* SDRAM */
106/* SDRAMC_MR Mode register */
107#define CONFIG_SYS_SDRC_MR_VAL1 0
108/* SDRAMC_TR - Refresh Timer register */
109#define CONFIG_SYS_SDRC_TR_VAL1 0x13C
110/* SDRAMC_CR - Configuration register*/
111#define CONFIG_SYS_SDRC_CR_VAL \
112 (AT91_SDRAMC_NC_9 | \
113 AT91_SDRAMC_NR_13 | \
114 AT91_SDRAMC_NB_4 | \
115 AT91_SDRAMC_CAS_3 | \
116 AT91_SDRAMC_DBW_32 | \
117 (1 << 8) | /* Write Recovery Delay */ \
118 (7 << 12) | /* Row Cycle Delay */ \
119 (2 << 16) | /* Row Precharge Delay */ \
120 (2 << 20) | /* Row to Column Delay */ \
121 (5 << 24) | /* Active to Precharge Delay */ \
122 (1 << 28)) /* Exit Self Refresh to Active Delay */
123
124/* Memory Device Register -> SDRAM */
125#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
126#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
127#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
128#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
129#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
130#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
131#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
132#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
133#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
134#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
135#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
136#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
137#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
138#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
139#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
140#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
141#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
142#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
143
144/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
Jens Scharsigc3c10ea2010-02-03 22:47:18 +0100145#define CONFIG_SYS_SMC0_SETUP0_VAL \
146 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
147 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
148#define CONFIG_SYS_SMC0_PULSE0_VAL \
149 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
150 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
Jean-Christophe PLAGNIOL-VILLARD32774732009-06-13 12:48:36 +0200151#define CONFIG_SYS_SMC0_CYCLE0_VAL \
Jens Scharsigc3c10ea2010-02-03 22:47:18 +0100152 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
Jean-Christophe PLAGNIOL-VILLARD32774732009-06-13 12:48:36 +0200153#define CONFIG_SYS_SMC0_MODE0_VAL \
Jens Scharsigc3c10ea2010-02-03 22:47:18 +0100154 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
155 AT91_SMC_MODE_DBW_16 | \
156 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))
Jean-Christophe PLAGNIOL-VILLARD32774732009-06-13 12:48:36 +0200157
158/* user reset enable */
159#define CONFIG_SYS_RSTC_RMR_VAL \
160 (AT91_RSTC_KEY | \
Jens Scharsigc3c10ea2010-02-03 22:47:18 +0100161 AT91_RSTC_MR_URSTEN | \
162 AT91_RSTC_MR_ERSTL(15))
Jean-Christophe PLAGNIOL-VILLARD32774732009-06-13 12:48:36 +0200163
164/* Disable Watchdog */
165#define CONFIG_SYS_WDTC_WDMR_VAL \
Jens Scharsigc3c10ea2010-02-03 22:47:18 +0100166 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
167 AT91_WDT_MR_WDV(0xfff) | \
168 AT91_WDT_MR_WDDIS | \
169 AT91_WDT_MR_WDD(0xfff))
170
Jean-Christophe PLAGNIOL-VILLARD32774732009-06-13 12:48:36 +0200171#endif
Simon Glassfb64e362020-05-10 11:40:09 -0600172#include <linux/stringify.h>
Stelian Pop69c925f2008-05-08 18:52:23 +0200173#endif
174
175/* NAND flash */
Jean-Christophe PLAGNIOL-VILLARDc9539ba2009-03-22 10:22:34 +0100176#ifdef CONFIG_CMD_NAND
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200177#define CONFIG_SYS_MAX_NAND_DEVICE 1
Xu, Hong504e4e12011-06-10 21:31:26 +0000178#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200179#define CONFIG_SYS_NAND_DBW_8 1
Jean-Christophe PLAGNIOL-VILLARDc9539ba2009-03-22 10:22:34 +0100180/* our ALE is AD21 */
181#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
182/* our CLE is AD22 */
183#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
Xu, Hong504e4e12011-06-10 21:31:26 +0000184#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
185#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22
Jean-Christophe PLAGNIOL-VILLARDc9539ba2009-03-22 10:22:34 +0100186#endif
Stelian Pop69c925f2008-05-08 18:52:23 +0200187
188/* Ethernet */
Stelian Pop69c925f2008-05-08 18:52:23 +0200189#define CONFIG_RESET_PHY_R 1
Heiko Schocher8a84ae12013-11-18 08:07:23 +0100190#define CONFIG_AT91_WANTS_COMMON_PHY
Stelian Pop69c925f2008-05-08 18:52:23 +0200191
192/* USB */
Jean-Christophe PLAGNIOL-VILLARDd42643f2009-03-27 23:26:44 +0100193#define CONFIG_USB_ATMEL
Bo Shen4a985df2013-10-21 16:14:00 +0800194#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
Stelian Pop69c925f2008-05-08 18:52:23 +0200195#define CONFIG_USB_OHCI_NEW 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200196#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
197#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
198#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
199#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
Stelian Pop69c925f2008-05-08 18:52:23 +0200200
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200201#ifdef CONFIG_SYS_USE_DATAFLASH
Stelian Pop69c925f2008-05-08 18:52:23 +0200202
203/* bootstrap + u-boot + env + linux in dataflash on CS0 */
Stelian Pop69c925f2008-05-08 18:52:23 +0200204
Jean-Christophe PLAGNIOL-VILLARD32774732009-06-13 12:48:36 +0200205#elif CONFIG_SYS_USE_NANDFLASH
Stelian Pop69c925f2008-05-08 18:52:23 +0200206
207/* bootstrap + u-boot + env + linux in nandflash */
Stelian Pop69c925f2008-05-08 18:52:23 +0200208#endif
209
Stelian Pop69c925f2008-05-08 18:52:23 +0200210#endif