blob: 4571a228c59e338855eb95a080c4a41ce5639133 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
York Sun03017032015-03-20 19:28:23 -07002/*
3 * Copyright 2015 Freescale Semiconductor, Inc.
York Sun03017032015-03-20 19:28:23 -07004 */
5
6#include <common.h>
7#include <fsl_ddr_sdram.h>
8#include <fsl_ddr_dimm_params.h>
Simon Glass0f2af882020-05-10 11:40:05 -06009#include <log.h>
York Suncbe8e1c2016-04-04 11:41:26 -070010#include <asm/arch/soc.h>
Simon Glass243182c2017-05-17 08:23:06 -060011#include <asm/arch/clock.h>
York Sun03017032015-03-20 19:28:23 -070012#include "ddr.h"
13
14DECLARE_GLOBAL_DATA_PTR;
15
16void fsl_ddr_board_options(memctl_options_t *popts,
17 dimm_params_t *pdimm,
18 unsigned int ctrl_num)
19{
Prabhakar Kushwaha122bcfd2015-11-09 16:42:07 +053020#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
York Sun03017032015-03-20 19:28:23 -070021 u8 dq_mapping_0, dq_mapping_2, dq_mapping_3;
Prabhakar Kushwaha122bcfd2015-11-09 16:42:07 +053022#endif
York Sun03017032015-03-20 19:28:23 -070023 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
24 ulong ddr_freq;
25 int slot;
26
27 if (ctrl_num > 2) {
28 printf("Not supported controller number %d\n", ctrl_num);
29 return;
30 }
31
32 for (slot = 0; slot < CONFIG_DIMM_SLOTS_PER_CTLR; slot++) {
33 if (pdimm[slot].n_ranks)
34 break;
35 }
36
37 if (slot >= CONFIG_DIMM_SLOTS_PER_CTLR)
38 return;
39
40 /*
41 * we use identical timing for all slots. If needed, change the code
42 * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
43 */
44 if (popts->registered_dimm_en)
45 pbsp = rdimms[ctrl_num];
46 else
47 pbsp = udimms[ctrl_num];
48
49
50 /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
51 * freqency and n_banks specified in board_specific_parameters table.
52 */
53 ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
54 while (pbsp->datarate_mhz_high) {
55 if (pbsp->n_ranks == pdimm[slot].n_ranks &&
56 (pdimm[slot].rank_density >> 30) >= pbsp->rank_gb) {
57 if (ddr_freq <= pbsp->datarate_mhz_high) {
58 popts->clk_adjust = pbsp->clk_adjust;
59 popts->wrlvl_start = pbsp->wrlvl_start;
60 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
61 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
62 goto found;
63 }
64 pbsp_highest = pbsp;
65 }
66 pbsp++;
67 }
68
69 if (pbsp_highest) {
70 printf("Error: board specific timing not found for data rate %lu MT/s\n"
71 "Trying to use the highest speed (%u) parameters\n",
72 ddr_freq, pbsp_highest->datarate_mhz_high);
73 popts->clk_adjust = pbsp_highest->clk_adjust;
74 popts->wrlvl_start = pbsp_highest->wrlvl_start;
75 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
76 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
77 } else {
78 panic("DIMM is not supported by this board");
79 }
80found:
81 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
82 "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n",
83 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
84 pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
85 pbsp->wrlvl_ctl_3);
Prabhakar Kushwaha122bcfd2015-11-09 16:42:07 +053086#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
York Sun03017032015-03-20 19:28:23 -070087 if (ctrl_num == CONFIG_DP_DDR_CTRL) {
York Sun12020ed2018-01-29 09:44:40 -080088 if (popts->registered_dimm_en)
89 printf("WARN: RDIMM not supported.\n");
York Sun03017032015-03-20 19:28:23 -070090 /* force DDR bus width to 32 bits */
91 popts->data_bus_width = 1;
92 popts->otf_burst_chop_en = 0;
93 popts->burst_length = DDR_BL8;
94 popts->bstopre = 0; /* enable auto precharge */
95 /*
96 * Layout optimization results byte mapping
97 * Byte 0 -> Byte ECC
98 * Byte 1 -> Byte 3
99 * Byte 2 -> Byte 2
100 * Byte 3 -> Byte 1
101 * Byte ECC -> Byte 0
102 */
103 dq_mapping_0 = pdimm[slot].dq_mapping[0];
104 dq_mapping_2 = pdimm[slot].dq_mapping[2];
105 dq_mapping_3 = pdimm[slot].dq_mapping[3];
106 pdimm[slot].dq_mapping[0] = pdimm[slot].dq_mapping[8];
107 pdimm[slot].dq_mapping[1] = pdimm[slot].dq_mapping[9];
108 pdimm[slot].dq_mapping[2] = pdimm[slot].dq_mapping[6];
109 pdimm[slot].dq_mapping[3] = pdimm[slot].dq_mapping[7];
110 pdimm[slot].dq_mapping[6] = dq_mapping_2;
111 pdimm[slot].dq_mapping[7] = dq_mapping_3;
112 pdimm[slot].dq_mapping[8] = dq_mapping_0;
113 pdimm[slot].dq_mapping[9] = 0;
114 pdimm[slot].dq_mapping[10] = 0;
115 pdimm[slot].dq_mapping[11] = 0;
116 pdimm[slot].dq_mapping[12] = 0;
117 pdimm[slot].dq_mapping[13] = 0;
118 pdimm[slot].dq_mapping[14] = 0;
119 pdimm[slot].dq_mapping[15] = 0;
120 pdimm[slot].dq_mapping[16] = 0;
121 pdimm[slot].dq_mapping[17] = 0;
122 }
Prabhakar Kushwaha122bcfd2015-11-09 16:42:07 +0530123#endif
York Sun03017032015-03-20 19:28:23 -0700124 /* To work at higher than 1333MT/s */
125 popts->half_strength_driver_enable = 0;
126 /*
127 * Write leveling override
128 */
129 popts->wrlvl_override = 1;
130 popts->wrlvl_sample = 0x0; /* 32 clocks */
131
132 /*
133 * Rtt and Rtt_WR override
134 */
135 popts->rtt_override = 0;
136
137 /* Enable ZQ calibration */
138 popts->zq_en = 1;
139
Shengzhou Liu29a53012016-11-15 17:15:21 +0800140 /* optimize cpo for erratum A-009942 */
141 popts->cpo_sample = 0x6e;
142
York Sun03017032015-03-20 19:28:23 -0700143 if (ddr_freq < 2350) {
York Sundb389772015-11-04 10:03:23 -0800144 if (pdimm[0].n_ranks == 2 && pdimm[1].n_ranks == 2) {
145 /* four chip-selects */
146 popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
147 DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
148 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm);
149 popts->twot_en = 1; /* enable 2T timing */
150 } else {
151 popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
152 DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
153 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
154 DDR_CDR2_VREF_RANGE_2;
155 }
York Sun03017032015-03-20 19:28:23 -0700156 } else {
157 popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
158 DDR_CDR1_ODT(DDR_CDR_ODT_100ohm);
159 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_100ohm) |
160 DDR_CDR2_VREF_RANGE_2;
161 }
162}
163
Rajesh Bhagatd5691be2018-12-27 04:37:59 +0000164#ifdef CONFIG_TFABOOT
Simon Glass0e0ac202017-04-06 12:47:04 -0600165int fsl_initdram(void)
York Sun03017032015-03-20 19:28:23 -0700166{
Rajesh Bhagatd5691be2018-12-27 04:37:59 +0000167 gd->ram_size = tfa_get_dram_size();
168
169 if (!gd->ram_size)
170 gd->ram_size = fsl_ddr_sdram_size();
171
172 return 0;
173}
174#else
175int fsl_initdram(void)
176{
Scott Wood8e728cd2015-03-24 13:25:02 -0700177#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
Simon Glass39f90ba2017-03-31 08:40:25 -0600178 gd->ram_size = fsl_ddr_sdram_size();
Scott Wood8e728cd2015-03-24 13:25:02 -0700179#else
York Sun03017032015-03-20 19:28:23 -0700180 puts("Initializing DDR....using SPD\n");
181
Simon Glass39f90ba2017-03-31 08:40:25 -0600182 gd->ram_size = fsl_ddr_sdram();
Scott Wood8e728cd2015-03-24 13:25:02 -0700183#endif
York Sun03017032015-03-20 19:28:23 -0700184
Simon Glass39f90ba2017-03-31 08:40:25 -0600185 return 0;
York Sun03017032015-03-20 19:28:23 -0700186}
Rajesh Bhagatd5691be2018-12-27 04:37:59 +0000187#endif /* CONFIG_TFABOOT */