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git01.mediatek.com / filogic / uboot / fce8e5c0a77fb511f6f905d8db02961f79bbf9b0 / . / drivers / pinctrl / Kconfig
blob: 0a4dd3c0cfd1f587fa10ef7d3e7db707c4795225 [file] [log] [blame]
Masahiro Yamadaf8efa632015-08-27 12:44:29 +0900[diff] [blame]1#
2# PINCTRL infrastructure and drivers
3#
4
5menu "Pin controllers"
6
7config PINCTRL
8 bool "Support pin controllers"
9 depends on DM
10 help
11 This enables the basic support for pinctrl framework. You may want
12 to enable some more options depending on what you want to do.
13
14config PINCTRL_FULL
15 bool "Support full pin controllers"
16 depends on PINCTRL && OF_CONTROL
17 default y
18 help
19 This provides Linux-compatible device tree interface for the pinctrl
20 subsystem. This feature depends on device tree configuration because
21 it parses a device tree to look for the pinctrl device which the
22 peripheral device is associated with.
23
24 If this option is disabled (it is the only possible choice for non-DT
25 boards), the pinctrl core provides no systematic mechanism for
26 identifying peripheral devices, applying needed pinctrl settings.
27 It is totally up to the implementation of each low-level driver.
28 You can save memory footprint in return for some limitations.
29
30config PINCTRL_GENERIC
31 bool "Support generic pin controllers"
32 depends on PINCTRL_FULL
33 default y
34 help
35 Say Y here if you want to use the pinctrl subsystem through the
36 generic DT interface. If enabled, some functions become available
37 to parse common properties such as "pins", "groups", "functions" and
38 some pin configuration parameters. It would be easier if you only
39 need the generic DT interface for pin muxing and pin configuration.
40 If you need to handle vendor-specific DT properties, you can disable
41 this option and implement your own set_state callback in the pinctrl
42 operations.
43
44config PINMUX
45 bool "Support pin multiplexing controllers"
46 depends on PINCTRL_GENERIC
47 default y
48 help
49 This option enables pin multiplexing through the generic pinctrl
Simon Glass8d6510d2015-08-30 16:55:12 -0600[diff] [blame]50 framework. Most SoCs have their own own multiplexing arrangement
51 where a single pin can be used for several functions. An SoC pinctrl
52 driver allows the required function to be selected for each pin.
53 The driver is typically controlled by the device tree.
Masahiro Yamadaf8efa632015-08-27 12:44:29 +0900[diff] [blame]54
55config PINCONF
56 bool "Support pin configuration controllers"
57 depends on PINCTRL_GENERIC
58 help
59 This option enables pin configuration through the generic pinctrl
60 framework.
61
62config SPL_PINCTRL
Philipp Tomsich2b1c2042017-07-26 12:27:42 +0200[diff] [blame]63 bool "Support pin controllers in SPL"
Masahiro Yamadaf8efa632015-08-27 12:44:29 +0900[diff] [blame]64 depends on SPL && SPL_DM
65 help
66 This option is an SPL-variant of the PINCTRL option.
67 See the help of PINCTRL for details.
68
69config SPL_PINCTRL_FULL
70 bool "Support full pin controllers in SPL"
71 depends on SPL_PINCTRL && SPL_OF_CONTROL
Vikas Manocha50218ae2017-05-28 12:55:10 -0700[diff] [blame]72 default n if TARGET_STM32F746_DISCO
Masahiro Yamadaf8efa632015-08-27 12:44:29 +0900[diff] [blame]73 default y
74 help
75 This option is an SPL-variant of the PINCTRL_FULL option.
76 See the help of PINCTRL_FULL for details.
77
78config SPL_PINCTRL_GENERIC
79 bool "Support generic pin controllers in SPL"
80 depends on SPL_PINCTRL_FULL
81 default y
82 help
83 This option is an SPL-variant of the PINCTRL_GENERIC option.
84 See the help of PINCTRL_GENERIC for details.
85
86config SPL_PINMUX
87 bool "Support pin multiplexing controllers in SPL"
88 depends on SPL_PINCTRL_GENERIC
89 default y
90 help
91 This option is an SPL-variant of the PINMUX option.
92 See the help of PINMUX for details.
Simon Glass8d6510d2015-08-30 16:55:12 -0600[diff] [blame]93 The pinctrl subsystem can add a substantial overhead to the SPL
94 image since it typically requires quite a few tables either in the
95 driver or in the device tree. If this is acceptable and you need
96 to adjust pin multiplexing in SPL in order to boot into U-Boot,
97 enable this option. You will need to enable device tree in SPL
98 for this to work.
Masahiro Yamadaf8efa632015-08-27 12:44:29 +0900[diff] [blame]99
100config SPL_PINCONF
101 bool "Support pin configuration controllers in SPL"
102 depends on SPL_PINCTRL_GENERIC
103 help
104 This option is an SPL-variant of the PINCONF option.
105 See the help of PINCONF for details.
106
107if PINCTRL || SPL_PINCTRL
108
Philipp Tomsicha1dcf3c2017-04-19 16:46:37 +0200[diff] [blame]109config PINCTRL_AR933X
Wills Wang77ae2382016-03-16 16:59:55 +0800[diff] [blame]110 bool "QCA/Athores ar933x pin control driver"
111 depends on DM && SOC_AR933X
112 help
113 Support pin multiplexing control on QCA/Athores ar933x SoCs.
114 The driver is controlled by a device tree node which contains
115 both the GPIO definitions and pin control functions for each
116 available multiplex function.
117
Philipp Tomsicha1dcf3c2017-04-19 16:46:37 +0200[diff] [blame]118config PINCTRL_AT91
119 bool "AT91 pinctrl driver"
120 depends on DM
121 help
122 This option is to enable the AT91 pinctrl driver for AT91 PIO
123 controller.
124
125 AT91 PIO controller is a combined gpio-controller, pin-mux and
126 pin-config module. Each I/O pin may be dedicated as a general-purpose
127 I/O or be assigned to a function of an embedded peripheral. Each I/O
128 pin has a glitch filter providing rejection of glitches lower than
129 one-half of peripheral clock cycle and a debouncing filter providing
130 rejection of unwanted pulses from key or push button operations. You
131 can also control the multi-driver capability, pull-up and pull-down
132 feature on each I/O pin.
133
134config PINCTRL_AT91PIO4
135 bool "AT91 PIO4 pinctrl driver"
136 depends on DM
137 help
138 This option is to enable the AT91 pinctrl driver for AT91 PIO4
139 controller which is available on SAMA5D2 SoC.
140
141config PINCTRL_PIC32
142 bool "Microchip PIC32 pin-control and pin-mux driver"
143 depends on DM && MACH_PIC32
144 default y
145 help
146 Supports individual pin selection and configuration for each
147 remappable peripheral available on Microchip PIC32
148 SoCs. This driver is controlled by a device tree node which
149 contains both GPIO defintion and pin control functions.
150
151config PINCTRL_QCA953X
Wills Wanga56de4c2016-03-16 16:59:56 +0800[diff] [blame]152 bool "QCA/Athores qca953x pin control driver"
153 depends on DM && SOC_QCA953X
154 help
155 Support pin multiplexing control on QCA/Athores qca953x SoCs.
Wills Wanga56de4c2016-03-16 16:59:56 +0800[diff] [blame]156
Philipp Tomsicha1dcf3c2017-04-19 16:46:37 +0200[diff] [blame]157 The driver is controlled by a device tree node which contains both
158 the GPIO definitions and pin control functions for each available
159 multiplex function.
160
161config PINCTRL_ROCKCHIP_RK3036
Heiko Stübner5c91e2b2016-07-16 00:17:15 +0200[diff] [blame]162 bool "Rockchip rk3036 pin control driver"
Simon Glass88442962015-08-30 16:55:35 -0600[diff] [blame]163 depends on DM
164 help
Philipp Tomsicha1dcf3c2017-04-19 16:46:37 +0200[diff] [blame]165 Support pin multiplexing control on Rockchip rk3036 SoCs.
166
167 The driver is controlled by a device tree node which contains both
168 the GPIO definitions and pin control functions for each available
169 multiplex function.
Simon Glass88442962015-08-30 16:55:35 -0600[diff] [blame]170
Kever Yang18bbf962017-11-28 16:04:18 +0800[diff] [blame]171config PINCTRL_ROCKCHIP_RK3128
172 bool "Rockchip rk3128 pin control driver"
173 depends on DM
174 help
175 Support pin multiplexing control on Rockchip rk3128 SoCs.
176
177 The driver is controlled by a device tree node which contains both
178 the GPIO definitions and pin control functions for each available
179 multiplex function.
180
Philipp Tomsicha1dcf3c2017-04-19 16:46:37 +0200[diff] [blame]181config PINCTRL_ROCKCHIP_RK3188
Philipp Tomsicha0ee8d12017-03-17 20:41:03 +0100[diff] [blame]182 bool "Rockchip rk3188 pin control driver"
Heiko Stübner36d6b162017-02-18 19:46:31 +0100[diff] [blame]183 depends on DM
184 help
Philipp Tomsicha1dcf3c2017-04-19 16:46:37 +0200[diff] [blame]185 Support pin multiplexing control on Rockchip rk3188 SoCs.
Heiko Stübner36d6b162017-02-18 19:46:31 +0100[diff] [blame]186
Philipp Tomsicha1dcf3c2017-04-19 16:46:37 +0200[diff] [blame]187 The driver is controlled by a device tree node which contains both
188 the GPIO definitions and pin control functions for each available
189 multiplex function.
huang lin4ccd9952015-11-17 14:20:20 +0800[diff] [blame]190
Kever Yang5f948962017-06-23 17:17:50 +0800[diff] [blame]191config PINCTRL_ROCKCHIP_RK322X
192 bool "Rockchip rk322x pin control driver"
193 depends on DM
194 help
195 Support pin multiplexing control on Rockchip rk322x SoCs.
196
197 The driver is controlled by a device tree node which contains both
198 the GPIO definitions and pin control functions for each available
199 multiplex function.
200
Philipp Tomsicha1dcf3c2017-04-19 16:46:37 +0200[diff] [blame]201config PINCTRL_ROCKCHIP_RK3288
202 bool "Rockchip rk3288 pin control driver"
Wenyou Yangc24e0132017-03-23 12:44:37 +0800[diff] [blame]203 depends on DM
204 help
Philipp Tomsicha1dcf3c2017-04-19 16:46:37 +0200[diff] [blame]205 Support pin multiplexing control on Rockchip rk3288 SoCs.
Wenyou Yangc24e0132017-03-23 12:44:37 +0800[diff] [blame]206
Philipp Tomsicha1dcf3c2017-04-19 16:46:37 +0200[diff] [blame]207 The driver is controlled by a device tree node which contains both
208 the GPIO definitions and pin control functions for each available
209 multiplex function.
Wenyou Yang309686c2016-07-20 17:16:27 +0800[diff] [blame]210
Philipp Tomsicha1dcf3c2017-04-19 16:46:37 +0200[diff] [blame]211config PINCTRL_ROCKCHIP_RK3328
Philipp Tomsicha0ee8d12017-03-17 20:41:03 +0100[diff] [blame]212 bool "Rockchip rk3328 pin control driver"
Kever Yangd73a4e82017-02-23 15:37:53 +0800[diff] [blame]213 depends on DM
214 help
Philipp Tomsicha1dcf3c2017-04-19 16:46:37 +0200[diff] [blame]215 Support pin multiplexing control on Rockchip rk3328 SoCs.
216
217 The driver is controlled by a device tree node which contains both
218 the GPIO definitions and pin control functions for each available
219 multiplex function.
Kever Yangd73a4e82017-02-23 15:37:53 +0800[diff] [blame]220
Andy Yan717733f2017-05-15 17:50:35 +0800[diff] [blame]221config PINCTRL_ROCKCHIP_RK3368
222 bool "Rockchip RK3368 pin control driver"
223 depends on DM
224 help
225 Support pin multiplexing control on Rockchip rk3368 SoCs.
226
227 The driver is controlled by a device tree node which contains both
228 the GPIO definitions and pin control functions for each available
229 multiplex function.
230
Philipp Tomsicha1dcf3c2017-04-19 16:46:37 +0200[diff] [blame]231config PINCTRL_ROCKCHIP_RK3399
Philipp Tomsicha0ee8d12017-03-17 20:41:03 +0100[diff] [blame]232 bool "Rockchip rk3399 pin control driver"
Kever Yangc4d9c492016-08-16 17:58:11 +0800[diff] [blame]233 depends on DM
234 help
Philipp Tomsicha1dcf3c2017-04-19 16:46:37 +0200[diff] [blame]235 Support pin multiplexing control on Rockchip rk3399 SoCs.
236
237 The driver is controlled by a device tree node which contains both
238 the GPIO definitions and pin control functions for each available
239 multiplex function.
Kever Yangc4d9c492016-08-16 17:58:11 +0800[diff] [blame]240
Andy Yan96c3da92017-06-01 18:00:10 +0800[diff] [blame]241config PINCTRL_ROCKCHIP_RV1108
242 bool "Rockchip rv1108 pin control driver"
243 depends on DM
244 help
245 Support pin multiplexing control on Rockchip rv1108 SoC.
246
247 The driver is controlled by a device tree node which contains
248 both the GPIO definitions and pin control functions for each
249 available multiplex function.
250
Masahiro Yamada0b53a752015-08-27 12:44:30 +0900[diff] [blame]251config PINCTRL_SANDBOX
252 bool "Sandbox pinctrl driver"
253 depends on SANDBOX
254 help
Philipp Tomsicha1dcf3c2017-04-19 16:46:37 +0200[diff] [blame]255 This enables pinctrl driver for sandbox.
Masahiro Yamada0b53a752015-08-27 12:44:30 +0900[diff] [blame]256
Philipp Tomsicha1dcf3c2017-04-19 16:46:37 +0200[diff] [blame]257 Currently, this driver actually does nothing but print debug
258 messages when pinctrl operations are invoked.
259
260config PINCTRL_SINGLE
261 bool "Single register pin-control and pin-multiplex driver"
262 depends on DM
Purna Chandra Mandaldb4fbfc2016-01-28 15:30:12 +0530[diff] [blame]263 help
Philipp Tomsicha1dcf3c2017-04-19 16:46:37 +0200[diff] [blame]264 This enables pinctrl driver for systems using a single register for
265 pin configuration and multiplexing. TI's AM335X SoCs are examples of
266 such systems.
267
268 Depending on the platform make sure to also enable OF_TRANSLATE and
269 eventually SPL_OF_TRANSLATE to get correct address translations.
Purna Chandra Mandaldb4fbfc2016-01-28 15:30:12 +0530[diff] [blame]270
Patrice Chotard32cf0462017-02-21 13:37:10 +0100[diff] [blame]271config PINCTRL_STI
272 bool "STMicroelectronics STi pin-control and pin-mux driver"
273 depends on DM && ARCH_STI
274 default y
275 help
276 Support pin multiplexing control on STMicrolectronics STi SoCs.
Philipp Tomsicha1dcf3c2017-04-19 16:46:37 +0200[diff] [blame]277
Patrice Chotard32cf0462017-02-21 13:37:10 +0100[diff] [blame]278 The driver is controlled by a device tree node which contains both
Philipp Tomsicha1dcf3c2017-04-19 16:46:37 +0200[diff] [blame]279 the GPIO definitions and pin control functions for each available
280 multiplex function.
Patrice Chotard32cf0462017-02-21 13:37:10 +0100[diff] [blame]281
Vikas Manocha07e9e412017-02-12 10:25:49 -0800[diff] [blame]282config PINCTRL_STM32
283 bool "ST STM32 pin control driver"
284 depends on DM
285 help
Philipp Tomsicha1dcf3c2017-04-19 16:46:37 +0200[diff] [blame]286 Supports pin multiplexing control on stm32 SoCs.
Vikas Manocha07e9e412017-02-12 10:25:49 -0800[diff] [blame]287
Philipp Tomsicha1dcf3c2017-04-19 16:46:37 +0200[diff] [blame]288 The driver is controlled by a device tree node which contains both
289 the GPIO definitions and pin control functions for each available
290 multiplex function.
Felix Brack7bc23542017-03-22 11:26:44 +0100[diff] [blame]291
maxims@google.com54651aa2017-04-17 12:00:27 -0700[diff] [blame]292config ASPEED_AST2500_PINCTRL
293 bool "Aspeed AST2500 pin control driver"
294 depends on DM && PINCTRL_GENERIC && ASPEED_AST2500
295 default y
296 help
297 Support pin multiplexing control on Aspeed ast2500 SoC. The driver uses
298 Generic Pinctrl framework and is compatible with the Linux driver,
299 i.e. it uses the same device tree configuration.
300
Masahiro Yamadaf8efa632015-08-27 12:44:29 +0900[diff] [blame]301endif
302
Beniamino Galvani2176d732016-08-16 11:49:49 +0200[diff] [blame]303source "drivers/pinctrl/meson/Kconfig"
Peng Fane2fd36cc2016-02-03 10:06:07 +0800[diff] [blame]304source "drivers/pinctrl/nxp/Kconfig"
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]305source "drivers/pinctrl/renesas/Kconfig"
Masahiro Yamada847e618b82015-09-11 20:17:32 +0900[diff] [blame]306source "drivers/pinctrl/uniphier/Kconfig"
Thomas Abrahamcf18bff2016-04-23 22:18:08 +0530[diff] [blame]307source "drivers/pinctrl/exynos/Kconfig"
Konstantin Porotchkinaed83152016-12-08 12:22:29 +0200[diff] [blame]308source "drivers/pinctrl/mvebu/Kconfig"
Alexander Graffce8e5c2018-01-23 18:05:21 +0100[diff] [blame^]309source "drivers/pinctrl/broadcom/Kconfig"
Masahiro Yamada847e618b82015-09-11 20:17:32 +0900[diff] [blame]310
Masahiro Yamadaf8efa632015-08-27 12:44:29 +0900[diff] [blame]311endmenu