blob: ebaa943198464857ed342c0ae5d380018819764b [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Ian Campbell6efe3692014-05-05 11:52:26 +01002/*
3 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
4 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
5 *
6 * (C) Copyright 2007-2011
7 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
8 * Tom Cubie <tangliang@allwinnertech.com>
9 *
10 * Some board init for the Allwinner A10-evb board.
Ian Campbell6efe3692014-05-05 11:52:26 +010011 */
12
13#include <common.h>
Tom Rini8c70baa2021-12-14 13:36:40 -050014#include <clock_legacy.h>
Jagan Teki73a3ecf2018-05-07 13:03:36 +053015#include <dm.h>
Simon Glass313112a2019-08-01 09:46:46 -060016#include <env.h>
Simon Glassf11478f2019-12-28 10:45:07 -070017#include <hang.h>
Simon Glass2dc9c342020-05-10 11:40:01 -060018#include <image.h>
Simon Glass8e16b1e2019-12-28 10:45:05 -070019#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060020#include <log.h>
Hans de Goede63deaa82014-10-02 21:13:54 +020021#include <mmc.h>
Hans de Goeded9ee84b2015-10-03 15:18:33 +020022#include <axp_pmic.h>
Jagan Teki73a3ecf2018-05-07 13:03:36 +053023#include <generic-phy.h>
24#include <phy-sun4i-usb.h>
Ian Campbell6efe3692014-05-05 11:52:26 +010025#include <asm/arch/clock.h>
Jonathan Liuabc1aae2014-06-14 08:59:09 +020026#include <asm/arch/cpu.h>
Luc Verhaegen4869a8c2014-08-13 07:55:07 +020027#include <asm/arch/display.h>
Ian Campbell6efe3692014-05-05 11:52:26 +010028#include <asm/arch/dram.h>
Ian Campbellb4e9f2f2014-05-05 14:42:31 +010029#include <asm/arch/mmc.h>
Samuel Holland9c7cefc2020-10-24 10:21:52 -050030#include <asm/arch/prcm.h>
Chris Morgan2ff2a1d2022-01-21 13:37:32 +000031#include <asm/arch/pmic_bus.h>
Hans de Goedea146c502016-07-09 09:56:56 +020032#include <asm/arch/spl.h>
Andre Przywara1823c232022-03-15 00:00:53 +000033#include <asm/arch/sys_proto.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060034#include <asm/global_data.h>
Simon Glassdbd79542020-05-10 11:40:11 -060035#include <linux/delay.h>
Simon Glassbdd5f812023-09-14 18:21:46 -060036#include <linux/printk.h>
Siarhei Siamashka26c50fb2016-03-29 17:29:10 +020037#ifndef CONFIG_ARM64
38#include <asm/armv7.h>
39#endif
Hans de Goeded9d05652015-04-23 23:23:50 +020040#include <asm/gpio.h>
Jonathan Liuabc1aae2014-06-14 08:59:09 +020041#include <asm/io.h>
Philipp Tomsich36b26d12018-11-25 19:22:18 +010042#include <u-boot/crc.h>
Simon Glass9d1f6192019-08-02 09:44:25 -060043#include <env_internal.h>
Masahiro Yamada75f82d02018-03-05 01:20:11 +090044#include <linux/libfdt.h>
Andre Heiderbf8c8102021-10-01 19:29:00 +010045#include <fdt_support.h>
Hans de Goede5ed52f62015-08-15 11:55:26 +020046#include <nand.h>
Jonathan Liuabc1aae2014-06-14 08:59:09 +020047#include <net.h>
Maxime Ripardae56d972017-08-23 10:08:29 +020048#include <spl.h>
Jelle van der Waa3f3a3092016-02-23 18:47:19 +010049#include <sy8106a.h>
Simon Glassd9a766f2017-05-17 08:23:00 -060050#include <asm/setup.h>
Arnaud Ferraris61485e92021-09-08 21:14:19 +020051#include <status_led.h>
Ian Campbell6efe3692014-05-05 11:52:26 +010052
53DECLARE_GLOBAL_DATA_PTR;
54
Jernej Skrabec07da8802017-04-27 00:03:35 +020055void i2c_init_board(void)
56{
57#ifdef CONFIG_I2C0_ENABLE
58#if defined(CONFIG_MACH_SUN4I) || \
59 defined(CONFIG_MACH_SUN5I) || \
60 defined(CONFIG_MACH_SUN7I) || \
61 defined(CONFIG_MACH_SUN8I_R40)
62 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
63 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
64 clock_twi_onoff(0, 1);
65#elif defined(CONFIG_MACH_SUN6I)
66 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
67 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
68 clock_twi_onoff(0, 1);
Icenowy Zheng365951a2020-10-26 22:19:34 +080069#elif defined(CONFIG_MACH_SUN8I_V3S)
70 sunxi_gpio_set_cfgpin(SUNXI_GPB(6), SUN8I_V3S_GPB_TWI0);
71 sunxi_gpio_set_cfgpin(SUNXI_GPB(7), SUN8I_V3S_GPB_TWI0);
72 clock_twi_onoff(0, 1);
Jernej Skrabec07da8802017-04-27 00:03:35 +020073#elif defined(CONFIG_MACH_SUN8I)
74 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
75 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
76 clock_twi_onoff(0, 1);
Stefan Mavrodievcabe9922019-01-08 12:04:30 +020077#elif defined(CONFIG_MACH_SUN50I)
78 sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_GPH_TWI0);
79 sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_GPH_TWI0);
80 clock_twi_onoff(0, 1);
Jernej Skrabec07da8802017-04-27 00:03:35 +020081#endif
82#endif
83
84#ifdef CONFIG_I2C1_ENABLE
85#if defined(CONFIG_MACH_SUN4I) || \
86 defined(CONFIG_MACH_SUN7I) || \
87 defined(CONFIG_MACH_SUN8I_R40)
88 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
89 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
90 clock_twi_onoff(1, 1);
91#elif defined(CONFIG_MACH_SUN5I)
92 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
93 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
94 clock_twi_onoff(1, 1);
95#elif defined(CONFIG_MACH_SUN6I)
96 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
97 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
98 clock_twi_onoff(1, 1);
99#elif defined(CONFIG_MACH_SUN8I)
100 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
101 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
102 clock_twi_onoff(1, 1);
Stefan Mavrodievcabe9922019-01-08 12:04:30 +0200103#elif defined(CONFIG_MACH_SUN50I)
104 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN50I_GPH_TWI1);
105 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN50I_GPH_TWI1);
106 clock_twi_onoff(1, 1);
Jernej Skrabec07da8802017-04-27 00:03:35 +0200107#endif
108#endif
109
Jernej Skrabec07da8802017-04-27 00:03:35 +0200110#ifdef CONFIG_R_I2C_ENABLE
Vasily Khoruzhick6f4c3442018-11-05 20:24:30 -0800111#ifdef CONFIG_MACH_SUN50I
112 clock_twi_onoff(5, 1);
113 sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI);
114 sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI);
Jernej Skrabec7de8eb02021-01-11 21:11:42 +0100115#elif CONFIG_MACH_SUN50I_H616
116 clock_twi_onoff(5, 1);
117 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN50I_H616_GPL_R_TWI);
118 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN50I_H616_GPL_R_TWI);
Vasily Khoruzhick6f4c3442018-11-05 20:24:30 -0800119#else
Jernej Skrabec07da8802017-04-27 00:03:35 +0200120 clock_twi_onoff(5, 1);
121 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
122 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
123#endif
Vasily Khoruzhick6f4c3442018-11-05 20:24:30 -0800124#endif
Jernej Skrabec07da8802017-04-27 00:03:35 +0200125}
126
Andre Przywarab176bf32022-01-11 12:46:04 +0000127/*
128 * Try to use the environment from the boot source first.
129 * For MMC, this means a FAT partition on the boot device (SD or eMMC).
130 * If the raw MMC environment is also enabled, this is tried next.
Samuel Hollandf7135742022-04-20 23:15:39 +0100131 * When booting from NAND we try UBI first, then NAND directly.
Andre Przywarab176bf32022-01-11 12:46:04 +0000132 * SPI flash falls back to FAT (on SD card).
133 */
Maxime Ripard9ba2ac72018-01-23 21:17:03 +0100134enum env_location env_get_location(enum env_operation op, int prio)
135{
Samuel Hollandf7135742022-04-20 23:15:39 +0100136 if (prio > 1)
137 return ENVL_UNKNOWN;
Maxime Ripard9ba2ac72018-01-23 21:17:03 +0100138
Samuel Hollandf7135742022-04-20 23:15:39 +0100139 /* NOWHERE is exclusive, no other option can be defined. */
140 if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE))
141 return ENVL_NOWHERE;
Maxime Ripard9ba2ac72018-01-23 21:17:03 +0100142
Andre Przywarab176bf32022-01-11 12:46:04 +0000143 switch (sunxi_get_boot_device()) {
144 case BOOT_DEVICE_MMC1:
145 case BOOT_DEVICE_MMC2:
Samuel Hollandf7135742022-04-20 23:15:39 +0100146 if (prio == 0 && IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
147 return ENVL_FAT;
148 if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC))
149 return ENVL_MMC;
Andre Przywarab176bf32022-01-11 12:46:04 +0000150 break;
151 case BOOT_DEVICE_NAND:
Samuel Hollandf7135742022-04-20 23:15:39 +0100152 if (prio == 0 && IS_ENABLED(CONFIG_ENV_IS_IN_UBI))
153 return ENVL_UBI;
Andre Przywarab176bf32022-01-11 12:46:04 +0000154 if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
Samuel Hollandf7135742022-04-20 23:15:39 +0100155 return ENVL_NAND;
Andre Przywarab176bf32022-01-11 12:46:04 +0000156 break;
157 case BOOT_DEVICE_SPI:
Samuel Hollandf7135742022-04-20 23:15:39 +0100158 if (prio == 0 && IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
159 return ENVL_SPI_FLASH;
160 if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
161 return ENVL_FAT;
Andre Przywarab176bf32022-01-11 12:46:04 +0000162 break;
163 case BOOT_DEVICE_BOARD:
164 break;
Maxime Ripard9ba2ac72018-01-23 21:17:03 +0100165 default:
Andre Przywarab176bf32022-01-11 12:46:04 +0000166 break;
Maxime Ripard9ba2ac72018-01-23 21:17:03 +0100167 }
Andre Przywarab176bf32022-01-11 12:46:04 +0000168
Samuel Hollandf7135742022-04-20 23:15:39 +0100169 /*
170 * If we come here for the first time, we *must* return a valid
171 * environment location other than ENVL_UNKNOWN, or the setup sequence
172 * in board_f() will silently hang. This is arguably a bug in
173 * env_init(), but for now pick one environment for which we know for
174 * sure to have a driver for. For all defconfigs this is either FAT
175 * or UBI, or NOWHERE, which is already handled above.
176 */
177 if (prio == 0) {
178 if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
Andre Przywarab176bf32022-01-11 12:46:04 +0000179 return ENVL_FAT;
Samuel Hollandf7135742022-04-20 23:15:39 +0100180 if (IS_ENABLED(CONFIG_ENV_IS_IN_UBI))
181 return ENVL_UBI;
Andre Przywarab176bf32022-01-11 12:46:04 +0000182 }
183
184 return ENVL_UNKNOWN;
Maxime Ripard9ba2ac72018-01-23 21:17:03 +0100185}
Maxime Ripard9ba2ac72018-01-23 21:17:03 +0100186
Ian Campbell6efe3692014-05-05 11:52:26 +0100187/* add board specific code here */
188int board_init(void)
189{
Mylène Josserand147c6062017-04-02 12:59:10 +0200190 __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
Ian Campbell6efe3692014-05-05 11:52:26 +0100191
192 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
193
Icenowy Zheng3a3b7342022-01-29 10:23:05 -0500194#if !defined(CONFIG_ARM64) && !defined(CONFIG_MACH_SUNIV)
Ian Campbell6efe3692014-05-05 11:52:26 +0100195 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
196 debug("id_pfr1: 0x%08x\n", id_pfr1);
197 /* Generic Timer Extension available? */
Siarhei Siamashka26c50fb2016-03-29 17:29:10 +0200198 if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) {
199 uint32_t freq;
200
Ian Campbell6efe3692014-05-05 11:52:26 +0100201 debug("Setting CNTFRQ\n");
Siarhei Siamashka26c50fb2016-03-29 17:29:10 +0200202
203 /*
204 * CNTFRQ is a secure register, so we will crash if we try to
205 * write this from the non-secure world (read is OK, though).
206 * In case some bootcode has already set the correct value,
207 * we avoid the risk of writing to it.
208 */
209 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
Peng Fane7c59392022-04-13 17:47:22 +0800210 if (freq != CONFIG_COUNTER_FREQUENCY) {
Siarhei Siamashka26c50fb2016-03-29 17:29:10 +0200211 debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
Peng Fane7c59392022-04-13 17:47:22 +0800212 freq, CONFIG_COUNTER_FREQUENCY);
Siarhei Siamashka26c50fb2016-03-29 17:29:10 +0200213#ifdef CONFIG_NON_SECURE
214 printf("arch timer frequency is wrong, but cannot adjust it\n");
215#else
216 asm volatile("mcr p15, 0, %0, c14, c0, 0"
Peng Fane7c59392022-04-13 17:47:22 +0800217 : : "r"(CONFIG_COUNTER_FREQUENCY));
Siarhei Siamashka26c50fb2016-03-29 17:29:10 +0200218#endif
219 }
Ian Campbell6efe3692014-05-05 11:52:26 +0100220 }
Icenowy Zheng3a3b7342022-01-29 10:23:05 -0500221#endif /* !CONFIG_ARM64 && !CONFIG_MACH_SUNIV */
Ian Campbell6efe3692014-05-05 11:52:26 +0100222
Hans de Goede3ae1d132015-04-25 17:25:14 +0200223 ret = axp_gpio_init();
224 if (ret)
225 return ret;
226
Andre Przywara3b2dbb52021-01-18 23:23:59 +0000227 /* strcmp() would look better, but doesn't get optimised away. */
228 if (CONFIG_SATAPWR[0]) {
229 satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
230 if (satapwr_pin >= 0) {
231 gpio_request(satapwr_pin, "satapwr");
232 gpio_direction_output(satapwr_pin, 1);
233
234 /*
235 * Give the attached SATA device time to power-up
236 * to avoid link timeouts
237 */
238 mdelay(500);
239 }
240 }
241
242 if (CONFIG_MACPWR[0]) {
243 macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
244 if (macpwr_pin >= 0) {
245 gpio_request(macpwr_pin, "macpwr");
246 gpio_direction_output(macpwr_pin, 1);
247 }
248 }
Hans de Goede42cbbe32016-03-17 13:53:03 +0100249
Igor Opaniukf7c91762021-02-09 13:52:45 +0200250#if CONFIG_IS_ENABLED(DM_I2C)
Jernej Skrabec9220d502017-04-27 00:03:36 +0200251 /*
252 * Temporary workaround for enabling I2C clocks until proper sunxi DM
253 * clk, reset and pinctrl drivers land.
254 */
255 i2c_init_board();
256#endif
Andre Przywarad7cea362019-01-29 15:54:14 +0000257
Andre Przywara1823c232022-03-15 00:00:53 +0000258 eth_init_board();
259
Samuel Holland75fe0f42021-10-08 00:17:24 -0500260 return 0;
Ian Campbell6efe3692014-05-05 11:52:26 +0100261}
262
Andre Przywara14a25392018-10-25 17:23:04 +0800263/*
264 * On older SoCs the SPL is actually at address zero, so using NULL as
265 * an error value does not work.
266 */
267#define INVALID_SPL_HEADER ((void *)~0UL)
268
269static struct boot_file_head * get_spl_header(uint8_t req_version)
270{
271 struct boot_file_head *spl = (void *)(ulong)SPL_ADDR;
272 uint8_t spl_header_version = spl->spl_signature[3];
273
274 /* Is there really the SPL header (still) there? */
275 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
276 return INVALID_SPL_HEADER;
277
278 if (spl_header_version < req_version) {
279 printf("sunxi SPL version mismatch: expected %u, got %u\n",
280 req_version, spl_header_version);
281 return INVALID_SPL_HEADER;
282 }
283
284 return spl;
285}
286
Samuel Hollandba44e942020-10-24 10:21:50 -0500287static const char *get_spl_dt_name(void)
288{
289 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
290
291 /* Check if there is a DT name stored in the SPL header. */
292 if (spl != INVALID_SPL_HEADER && spl->dt_name_offset)
293 return (char *)spl + spl->dt_name_offset;
294
295 return NULL;
296}
Samuel Hollandba44e942020-10-24 10:21:50 -0500297
Ian Campbell6efe3692014-05-05 11:52:26 +0100298int dram_init(void)
299{
Andre Przywara08ee1ba2018-10-25 17:23:07 +0800300 struct boot_file_head *spl = get_spl_header(SPL_DRAM_HEADER_VERSION);
301
302 if (spl == INVALID_SPL_HEADER)
303 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0,
304 PHYS_SDRAM_0_SIZE);
305 else
306 gd->ram_size = (phys_addr_t)spl->dram_size << 20;
307
308 if (gd->ram_size > CONFIG_SUNXI_DRAM_MAX_SIZE)
309 gd->ram_size = CONFIG_SUNXI_DRAM_MAX_SIZE;
Ian Campbell6efe3692014-05-05 11:52:26 +0100310
311 return 0;
312}
313
Samuel Holland890f7de2023-01-22 16:06:35 -0600314#if defined(CONFIG_NAND_SUNXI) && defined(CONFIG_SPL_BUILD)
Karol Gugala7bea8932015-07-23 14:33:01 +0200315static void nand_pinmux_setup(void)
316{
317 unsigned int pin;
Karol Gugala7bea8932015-07-23 14:33:01 +0200318
Hans de Goeded2236782015-08-15 13:17:49 +0200319 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
Karol Gugala7bea8932015-07-23 14:33:01 +0200320 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
321
Hans de Goeded2236782015-08-15 13:17:49 +0200322#if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
323 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
324 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
325#endif
326 /* sun4i / sun7i do have a PC23, but it is not used for nand,
327 * only sun7i has a PC24 */
328#ifdef CONFIG_MACH_SUN7I
Karol Gugala7bea8932015-07-23 14:33:01 +0200329 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
Hans de Goeded2236782015-08-15 13:17:49 +0200330#endif
Karol Gugala7bea8932015-07-23 14:33:01 +0200331}
332
333static void nand_clock_setup(void)
334{
335 struct sunxi_ccm_reg *const ccm =
336 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
Hans de Goedee5561a82015-08-15 11:58:03 +0200337
Karol Gugala7bea8932015-07-23 14:33:01 +0200338 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
Miquel Raynalebeeb802018-02-28 20:51:53 +0100339#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \
340 defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I
341 setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0));
342#endif
Karol Gugala7bea8932015-07-23 14:33:01 +0200343 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
344}
Hans de Goede5ed52f62015-08-15 11:55:26 +0200345
346void board_nand_init(void)
347{
348 nand_pinmux_setup();
349 nand_clock_setup();
350}
Andre Przywaraa9aab242022-11-28 00:02:56 +0000351#endif /* CONFIG_NAND_SUNXI */
Karol Gugala7bea8932015-07-23 14:33:01 +0200352
Masahiro Yamada0a780172017-05-09 20:31:39 +0900353#ifdef CONFIG_MMC
Ian Campbellb4e9f2f2014-05-05 14:42:31 +0100354static void mmc_pinmux_setup(int sdc)
355{
356 unsigned int pin;
357
358 switch (sdc) {
359 case 0:
Paul Kocialkowskid390d8c2015-03-22 18:12:23 +0100360 /* SDC0: PF0-PF5 */
Ian Campbellb4e9f2f2014-05-05 14:42:31 +0100361 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
Paul Kocialkowskiae358a42015-03-22 18:12:22 +0100362 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
Ian Campbellb4e9f2f2014-05-05 14:42:31 +0100363 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
364 sunxi_gpio_set_drv(pin, 2);
365 }
366 break;
367
368 case 1:
Chen-Yu Tsai111bc592016-11-30 16:28:34 +0800369#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
370 defined(CONFIG_MACH_SUN8I_R40)
Samuel Holland51951052021-09-12 10:28:35 -0500371 if (IS_ENABLED(CONFIG_MMC1_PINS_PH)) {
Paul Kocialkowskid390d8c2015-03-22 18:12:23 +0100372 /* SDC1: PH22-PH-27 */
373 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
374 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
375 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
376 sunxi_gpio_set_drv(pin, 2);
377 }
378 } else {
379 /* SDC1: PG0-PG5 */
380 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
381 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
382 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
383 sunxi_gpio_set_drv(pin, 2);
384 }
385 }
386#elif defined(CONFIG_MACH_SUN5I)
387 /* SDC1: PG3-PG8 */
Hans de Goede4dccfd42014-10-03 16:44:57 +0200388 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
Paul Kocialkowskiae358a42015-03-22 18:12:22 +0100389 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
Ian Campbellb4e9f2f2014-05-05 14:42:31 +0100390 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
391 sunxi_gpio_set_drv(pin, 2);
392 }
Paul Kocialkowskid390d8c2015-03-22 18:12:23 +0100393#elif defined(CONFIG_MACH_SUN6I)
394 /* SDC1: PG0-PG5 */
395 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
396 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
397 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
398 sunxi_gpio_set_drv(pin, 2);
399 }
400#elif defined(CONFIG_MACH_SUN8I)
Samuel Holland51951052021-09-12 10:28:35 -0500401 /* SDC1: PG0-PG5 */
402 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
403 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
404 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
405 sunxi_gpio_set_drv(pin, 2);
Paul Kocialkowskid390d8c2015-03-22 18:12:23 +0100406 }
407#endif
Ian Campbellb4e9f2f2014-05-05 14:42:31 +0100408 break;
409
410 case 2:
Paul Kocialkowskid390d8c2015-03-22 18:12:23 +0100411#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
412 /* SDC2: PC6-PC11 */
Ian Campbellb4e9f2f2014-05-05 14:42:31 +0100413 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
Paul Kocialkowskiae358a42015-03-22 18:12:22 +0100414 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
Ian Campbellb4e9f2f2014-05-05 14:42:31 +0100415 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
416 sunxi_gpio_set_drv(pin, 2);
417 }
Paul Kocialkowskid390d8c2015-03-22 18:12:23 +0100418#elif defined(CONFIG_MACH_SUN5I)
Samuel Holland51951052021-09-12 10:28:35 -0500419 /* SDC2: PC6-PC15 */
420 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
421 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
422 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
423 sunxi_gpio_set_drv(pin, 2);
Paul Kocialkowskid390d8c2015-03-22 18:12:23 +0100424 }
425#elif defined(CONFIG_MACH_SUN6I)
Samuel Holland51951052021-09-12 10:28:35 -0500426 /* SDC2: PC6-PC15, PC24 */
427 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
428 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
429 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
430 sunxi_gpio_set_drv(pin, 2);
Paul Kocialkowskid390d8c2015-03-22 18:12:23 +0100431 }
Samuel Holland51951052021-09-12 10:28:35 -0500432
433 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
434 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
435 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
Chen-Yu Tsai111bc592016-11-30 16:28:34 +0800436#elif defined(CONFIG_MACH_SUN8I_R40)
437 /* SDC2: PC6-PC15, PC24 */
438 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
439 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
440 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
441 sunxi_gpio_set_drv(pin, 2);
442 }
443
444 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
445 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
446 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
Siarhei Siamashka26c50fb2016-03-29 17:29:10 +0200447#elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
Paul Kocialkowskid390d8c2015-03-22 18:12:23 +0100448 /* SDC2: PC5-PC6, PC8-PC16 */
449 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
450 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
451 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
452 sunxi_gpio_set_drv(pin, 2);
453 }
454
455 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
456 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
457 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
458 sunxi_gpio_set_drv(pin, 2);
459 }
Icenowy Zhenga838a152018-07-21 16:20:29 +0800460#elif defined(CONFIG_MACH_SUN50I_H6)
461 /* SDC2: PC4-PC14 */
462 for (pin = SUNXI_GPC(4); pin <= SUNXI_GPC(14); pin++) {
463 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
464 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
465 sunxi_gpio_set_drv(pin, 2);
466 }
Andre Przywara96f55642021-04-26 00:38:04 +0100467#elif defined(CONFIG_MACH_SUN50I_H616)
468 /* SDC2: PC0-PC1, PC5-PC6, PC8-PC11, PC13-PC16 */
469 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(16); pin++) {
470 if (pin > SUNXI_GPC(1) && pin < SUNXI_GPC(5))
471 continue;
472 if (pin == SUNXI_GPC(7) || pin == SUNXI_GPC(12))
473 continue;
474 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
475 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
476 sunxi_gpio_set_drv(pin, 3);
477 }
Philipp Tomsicha0c7c712016-10-28 18:21:33 +0800478#elif defined(CONFIG_MACH_SUN9I)
479 /* SDC2: PC6-PC16 */
480 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
481 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
482 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
483 sunxi_gpio_set_drv(pin, 2);
484 }
Andre Przywara96f55642021-04-26 00:38:04 +0100485#else
486 puts("ERROR: No pinmux setup defined for MMC2!\n");
Paul Kocialkowskid390d8c2015-03-22 18:12:23 +0100487#endif
Ian Campbellb4e9f2f2014-05-05 14:42:31 +0100488 break;
489
490 case 3:
Chen-Yu Tsai111bc592016-11-30 16:28:34 +0800491#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
492 defined(CONFIG_MACH_SUN8I_R40)
Paul Kocialkowskid390d8c2015-03-22 18:12:23 +0100493 /* SDC3: PI4-PI9 */
Ian Campbellb4e9f2f2014-05-05 14:42:31 +0100494 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
Paul Kocialkowskid390d8c2015-03-22 18:12:23 +0100495 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
Ian Campbellb4e9f2f2014-05-05 14:42:31 +0100496 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
497 sunxi_gpio_set_drv(pin, 2);
498 }
Paul Kocialkowskid390d8c2015-03-22 18:12:23 +0100499#elif defined(CONFIG_MACH_SUN6I)
Samuel Holland51951052021-09-12 10:28:35 -0500500 /* SDC3: PC6-PC15, PC24 */
501 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
502 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
503 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
504 sunxi_gpio_set_drv(pin, 2);
Paul Kocialkowskid390d8c2015-03-22 18:12:23 +0100505 }
Samuel Holland51951052021-09-12 10:28:35 -0500506
507 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
508 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
509 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
Paul Kocialkowskid390d8c2015-03-22 18:12:23 +0100510#endif
Ian Campbellb4e9f2f2014-05-05 14:42:31 +0100511 break;
512
513 default:
514 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
515 break;
516 }
517}
518
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +0900519int board_mmc_init(struct bd_info *bis)
Ian Campbellb4e9f2f2014-05-05 14:42:31 +0100520{
Andre Przywaraff32afe2022-11-28 00:03:53 +0000521 /*
522 * The BROM always accesses MMC port 0 (typically an SD card), and
523 * most boards seem to have such a slot. The others haven't reported
524 * any problem with unconditionally enabling this in the SPL.
525 */
Samuel Holland35663cf2022-04-10 00:13:33 -0500526 if (!IS_ENABLED(CONFIG_UART0_PORT_F)) {
Andre Przywaraff32afe2022-11-28 00:03:53 +0000527 mmc_pinmux_setup(0);
528 if (!sunxi_mmc_init(0))
Samuel Holland35663cf2022-04-10 00:13:33 -0500529 return -1;
530 }
Hans de Goede63deaa82014-10-02 21:13:54 +0200531
Samuel Holland35663cf2022-04-10 00:13:33 -0500532 if (CONFIG_MMC_SUNXI_SLOT_EXTRA != -1) {
533 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
534 if (!sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA))
535 return -1;
536 }
Hans de Goede63deaa82014-10-02 21:13:54 +0200537
Ian Campbellb4e9f2f2014-05-05 14:42:31 +0100538 return 0;
539}
Samuel Hollandbc42abb2021-04-18 22:16:21 -0500540
541#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
542int mmc_get_env_dev(void)
543{
544 switch (sunxi_get_boot_device()) {
545 case BOOT_DEVICE_MMC1:
546 return 0;
547 case BOOT_DEVICE_MMC2:
548 return 1;
549 default:
550 return CONFIG_SYS_MMC_ENV_DEV;
551 }
552}
553#endif
Andre Przywaraa9aab242022-11-28 00:02:56 +0000554#endif /* CONFIG_MMC */
Ian Campbellb4e9f2f2014-05-05 14:42:31 +0100555
Ian Campbell6efe3692014-05-05 11:52:26 +0100556#ifdef CONFIG_SPL_BUILD
Andre Przywara08ee1ba2018-10-25 17:23:07 +0800557
558static void sunxi_spl_store_dram_size(phys_addr_t dram_size)
559{
560 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
561
562 if (spl == INVALID_SPL_HEADER)
563 return;
564
565 /* Promote the header version for U-Boot proper, if needed. */
566 if (spl->spl_signature[3] < SPL_DRAM_HEADER_VERSION)
567 spl->spl_signature[3] = SPL_DRAM_HEADER_VERSION;
568
569 spl->dram_size = dram_size >> 20;
570}
571
Ian Campbell6efe3692014-05-05 11:52:26 +0100572void sunxi_board_init(void)
573{
Henrik Nordstromaa382ad2014-06-13 22:55:50 +0200574 int power_failed = 0;
Ian Campbell6efe3692014-05-05 11:52:26 +0100575
Arnaud Ferraris61485e92021-09-08 21:14:19 +0200576#ifdef CONFIG_LED_STATUS
577 if (IS_ENABLED(CONFIG_SPL_DRIVERS_MISC))
578 status_led_init();
579#endif
580
Jelle van der Waa3f3a3092016-02-23 18:47:19 +0100581#ifdef CONFIG_SY8106A_POWER
582 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
583#endif
584
vishnupatekar1895dfd2015-11-29 01:07:22 +0800585#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
Jernej Skrabecfde828c2021-01-11 21:11:33 +0100586 defined CONFIG_AXP221_POWER || defined CONFIG_AXP305_POWER || \
587 defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
Hans de Goeded9ee84b2015-10-03 15:18:33 +0200588 power_failed = axp_init();
589
Chris Morgan2ff2a1d2022-01-21 13:37:32 +0000590 if (IS_ENABLED(CONFIG_AXP_DISABLE_BOOT_ON_POWERON) && !power_failed) {
591 u8 boot_reason;
592
593 pmic_bus_read(AXP_POWER_STATUS, &boot_reason);
594 if (boot_reason & AXP_POWER_STATUS_ALDO_IN) {
595 printf("Power on by plug-in, shutting down.\n");
596 pmic_bus_write(0x32, BIT(7));
597 }
598 }
599
Chen-Yu Tsaif1e66e72016-05-02 10:28:15 +0800600#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
601 defined CONFIG_AXP818_POWER
Hans de Goeded9ee84b2015-10-03 15:18:33 +0200602 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
Hans de Goede1f247362014-06-13 22:55:51 +0200603#endif
Jernej Skrabecfde828c2021-01-11 21:11:33 +0100604#if !defined(CONFIG_AXP305_POWER)
Hans de Goeded9ee84b2015-10-03 15:18:33 +0200605 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
606 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
Jernej Skrabecfde828c2021-01-11 21:11:33 +0100607#endif
vishnupatekar1895dfd2015-11-29 01:07:22 +0800608#if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
Hans de Goeded9ee84b2015-10-03 15:18:33 +0200609 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
Henrik Nordstromaa382ad2014-06-13 22:55:50 +0200610#endif
Chen-Yu Tsaif1e66e72016-05-02 10:28:15 +0800611#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
612 defined CONFIG_AXP818_POWER
Hans de Goeded9ee84b2015-10-03 15:18:33 +0200613 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
Oliver Schinagld3a558d2013-07-26 12:56:58 +0200614#endif
Henrik Nordstromaa382ad2014-06-13 22:55:50 +0200615
Chen-Yu Tsaif1e66e72016-05-02 10:28:15 +0800616#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
617 defined CONFIG_AXP818_POWER
Hans de Goeded9ee84b2015-10-03 15:18:33 +0200618 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
619#endif
Jernej Skrabecfde828c2021-01-11 21:11:33 +0100620#if !defined(CONFIG_AXP305_POWER)
Hans de Goeded9ee84b2015-10-03 15:18:33 +0200621 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
Jernej Skrabecfde828c2021-01-11 21:11:33 +0100622#endif
623#if !defined(CONFIG_AXP152_POWER) && !defined(CONFIG_AXP305_POWER)
Hans de Goeded9ee84b2015-10-03 15:18:33 +0200624 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
625#endif
626#ifdef CONFIG_AXP209_POWER
627 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
628#endif
629
Chen-Yu Tsaif1e66e72016-05-02 10:28:15 +0800630#if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
631 defined(CONFIG_AXP818_POWER)
Chen-Yu Tsai2e6911f2016-01-12 14:42:37 +0800632 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
633 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
Chen-Yu Tsaif1e66e72016-05-02 10:28:15 +0800634#if !defined CONFIG_AXP809_POWER
Chen-Yu Tsai2e6911f2016-01-12 14:42:37 +0800635 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
636 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
Chen-Yu Tsaif1e66e72016-05-02 10:28:15 +0800637#endif
Hans de Goeded9ee84b2015-10-03 15:18:33 +0200638 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
639 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
640 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
641#endif
Chen-Yu Tsaid028fba2016-03-30 00:26:48 +0800642
643#ifdef CONFIG_AXP818_POWER
644 power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
645 power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
646 power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
Chen-Yu Tsaif1e66e72016-05-02 10:28:15 +0800647#endif
648
649#if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
Chen-Yu Tsai0e3efd32016-05-02 10:28:12 +0800650 power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
Chen-Yu Tsaid028fba2016-03-30 00:26:48 +0800651#endif
Hans de Goeded9ee84b2015-10-03 15:18:33 +0200652#endif
From: Karl Palsson0a0bcde2018-12-19 13:00:39 +0000653 printf("DRAM:");
654 gd->ram_size = sunxi_dram_init();
655 printf(" %d MiB\n", (int)(gd->ram_size >> 20));
656 if (!gd->ram_size)
657 hang();
658
659 sunxi_spl_store_dram_size(gd->ram_size);
Andre Przywara08ee1ba2018-10-25 17:23:07 +0800660
Henrik Nordstromaa382ad2014-06-13 22:55:50 +0200661 /*
662 * Only clock up the CPU to full speed if we are reasonably
663 * assured it's being powered with suitable core voltage
664 */
665 if (!power_failed)
Tom Rini8c70baa2021-12-14 13:36:40 -0500666 clock_set_pll1(get_board_sys_clk());
Henrik Nordstromaa382ad2014-06-13 22:55:50 +0200667 else
From: Karl Palsson0a0bcde2018-12-19 13:00:39 +0000668 printf("Failed to set core voltage! Can't set CPU frequency\n");
Ian Campbell6efe3692014-05-05 11:52:26 +0100669}
Andre Przywaraa9aab242022-11-28 00:02:56 +0000670#endif /* CONFIG_SPL_BUILD */
Jonathan Liuabc1aae2014-06-14 08:59:09 +0200671
Paul Kocialkowskidbbccaf2015-03-22 18:07:13 +0100672#ifdef CONFIG_USB_GADGET
673int g_dnl_board_usb_cable_connected(void)
674{
Jagan Teki73a3ecf2018-05-07 13:03:36 +0530675 struct udevice *dev;
676 struct phy phy;
677 int ret;
678
Jean-Jacques Hiblot9dc0d5c2018-11-29 10:52:46 +0100679 ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev);
Jagan Teki73a3ecf2018-05-07 13:03:36 +0530680 if (ret) {
681 pr_err("%s: Cannot find USB device\n", __func__);
682 return ret;
683 }
684
685 ret = generic_phy_get_by_name(dev, "usb", &phy);
686 if (ret) {
687 pr_err("failed to get %s USB PHY\n", dev->name);
688 return ret;
689 }
690
691 ret = generic_phy_init(&phy);
692 if (ret) {
Patrick Delaunay287e33c2020-07-03 17:36:41 +0200693 pr_debug("failed to init %s USB PHY\n", dev->name);
Jagan Teki73a3ecf2018-05-07 13:03:36 +0530694 return ret;
695 }
696
Andre Przywarae79ee612021-11-02 19:45:47 +0000697 return sun4i_usb_phy_vbus_detect(&phy);
Paul Kocialkowskidbbccaf2015-03-22 18:07:13 +0100698}
Andre Przywaraa9aab242022-11-28 00:02:56 +0000699#endif /* CONFIG_USB_GADGET */
Paul Kocialkowskidbbccaf2015-03-22 18:07:13 +0100700
Paul Kocialkowski99ae0f62015-03-28 18:35:36 +0100701#ifdef CONFIG_SERIAL_TAG
702void get_board_serial(struct tag_serialnr *serialnr)
703{
704 char *serial_string;
705 unsigned long long serial;
706
Simon Glass64b723f2017-08-03 12:22:12 -0600707 serial_string = env_get("serial#");
Paul Kocialkowski99ae0f62015-03-28 18:35:36 +0100708
709 if (serial_string) {
710 serial = simple_strtoull(serial_string, NULL, 16);
711
712 serialnr->high = (unsigned int) (serial >> 32);
713 serialnr->low = (unsigned int) (serial & 0xffffffff);
714 } else {
715 serialnr->high = 0;
716 serialnr->low = 0;
717 }
718}
719#endif
720
Bernhard Nortmannead498a2015-09-17 18:52:52 +0200721/*
722 * Check the SPL header for the "sunxi" variant. If found: parse values
723 * that might have been passed by the loader ("fel" utility), and update
724 * the environment accordingly.
725 */
726static void parse_spl_header(const uint32_t spl_addr)
727{
Andre Przywara14a25392018-10-25 17:23:04 +0800728 struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
Bernhard Nortmanne9bbbe82016-06-09 07:37:35 +0200729
Andre Przywara14a25392018-10-25 17:23:04 +0800730 if (spl == INVALID_SPL_HEADER)
Bernhard Nortmanne9bbbe82016-06-09 07:37:35 +0200731 return;
Andre Przywara14a25392018-10-25 17:23:04 +0800732
Bernhard Nortmanne9bbbe82016-06-09 07:37:35 +0200733 if (!spl->fel_script_address)
734 return;
735
736 if (spl->fel_uEnv_length != 0) {
737 /*
738 * data is expected in uEnv.txt compatible format, so "env
739 * import -t" the string(s) at fel_script_address right away.
740 */
Andre Przywaraac4e6732016-09-05 01:32:41 +0100741 himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address,
Bernhard Nortmanne9bbbe82016-06-09 07:37:35 +0200742 spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
743 return;
Bernhard Nortmannead498a2015-09-17 18:52:52 +0200744 }
Bernhard Nortmanne9bbbe82016-06-09 07:37:35 +0200745 /* otherwise assume .scr format (mkimage-type script) */
Simon Glass4d949a22017-08-03 12:22:10 -0600746 env_set_hex("fel_scriptaddr", spl->fel_script_address);
Bernhard Nortmannead498a2015-09-17 18:52:52 +0200747}
Bernhard Nortmannead498a2015-09-17 18:52:52 +0200748
Andre Heiderebdc3d42021-10-01 19:29:00 +0100749static bool get_unique_sid(unsigned int *sid)
750{
751 if (sunxi_get_sid(sid) != 0)
752 return false;
753
754 if (!sid[0])
755 return false;
756
757 /*
758 * The single words 1 - 3 of the SID have quite a few bits
759 * which are the same on many models, so we take a crc32
760 * of all 3 words, to get a more unique value.
761 *
762 * Note we only do this on newer SoCs as we cannot change
763 * the algorithm on older SoCs since those have been using
764 * fixed mac-addresses based on only using word 3 for a
765 * long time and changing a fixed mac-address with an
766 * u-boot update is not good.
767 */
768#if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
769 !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
770 !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
771 sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
772#endif
773
774 /* Ensure the NIC specific bytes of the mac are not all 0 */
775 if ((sid[3] & 0xffffff) == 0)
776 sid[3] |= 0x800000;
777
778 return true;
779}
780
Hans de Goededa0ff7c2016-06-26 13:34:42 +0200781/*
782 * Note this function gets called multiple times.
783 * It must not make any changes to env variables which already exist.
784 */
785static void setup_environment(const void *fdt)
Jonathan Liuabc1aae2014-06-14 08:59:09 +0200786{
Paul Kocialkowski92935942015-03-28 18:35:35 +0100787 char serial_string[17] = { 0 };
Hans de Goede11d70982014-11-26 00:04:24 +0100788 unsigned int sid[4];
Paul Kocialkowski92935942015-03-28 18:35:35 +0100789 uint8_t mac_addr[6];
Hans de Goededa0ff7c2016-06-26 13:34:42 +0200790 char ethaddr[16];
Andre Heiderebdc3d42021-10-01 19:29:00 +0100791 int i;
Hans de Goedee5fe5482016-07-29 11:47:03 +0200792
Andre Heiderebdc3d42021-10-01 19:29:00 +0100793 if (!get_unique_sid(sid))
794 return;
Hans de Goedeabca8432016-07-27 17:58:06 +0200795
Andre Heiderebdc3d42021-10-01 19:29:00 +0100796 for (i = 0; i < 4; i++) {
797 sprintf(ethaddr, "ethernet%d", i);
798 if (!fdt_get_alias(fdt, ethaddr))
799 continue;
Hans de Goededa0ff7c2016-06-26 13:34:42 +0200800
Andre Heiderebdc3d42021-10-01 19:29:00 +0100801 if (i == 0)
802 strcpy(ethaddr, "ethaddr");
803 else
804 sprintf(ethaddr, "eth%daddr", i);
Hans de Goededa0ff7c2016-06-26 13:34:42 +0200805
Andre Heiderebdc3d42021-10-01 19:29:00 +0100806 if (env_get(ethaddr))
807 continue;
Hans de Goededa0ff7c2016-06-26 13:34:42 +0200808
Andre Heiderebdc3d42021-10-01 19:29:00 +0100809 /* Non OUI / registered MAC address */
810 mac_addr[0] = (i << 4) | 0x02;
811 mac_addr[1] = (sid[0] >> 0) & 0xff;
812 mac_addr[2] = (sid[3] >> 24) & 0xff;
813 mac_addr[3] = (sid[3] >> 16) & 0xff;
814 mac_addr[4] = (sid[3] >> 8) & 0xff;
815 mac_addr[5] = (sid[3] >> 0) & 0xff;
Jonathan Liuabc1aae2014-06-14 08:59:09 +0200816
Andre Heiderebdc3d42021-10-01 19:29:00 +0100817 eth_env_set_enetaddr(ethaddr, mac_addr);
818 }
Paul Kocialkowski92935942015-03-28 18:35:35 +0100819
Andre Heiderebdc3d42021-10-01 19:29:00 +0100820 if (!env_get("serial#")) {
821 snprintf(serial_string, sizeof(serial_string),
822 "%08x%08x", sid[0], sid[3]);
Jonathan Liuabc1aae2014-06-14 08:59:09 +0200823
Andre Heiderebdc3d42021-10-01 19:29:00 +0100824 env_set("serial#", serial_string);
Jonathan Liuabc1aae2014-06-14 08:59:09 +0200825 }
Hans de Goededa0ff7c2016-06-26 13:34:42 +0200826}
827
Hans de Goededa0ff7c2016-06-26 13:34:42 +0200828int misc_init_r(void)
829{
Samuel Holland87f940a2020-10-24 10:21:54 -0500830 const char *spl_dt_name;
Maxime Ripardae56d972017-08-23 10:08:29 +0200831 uint boot;
Hans de Goededa0ff7c2016-06-26 13:34:42 +0200832
Simon Glass6a38e412017-08-03 12:22:09 -0600833 env_set("fel_booted", NULL);
834 env_set("fel_scriptaddr", NULL);
Maxime Ripard65cefba2017-08-23 10:12:22 +0200835 env_set("mmc_bootdev", NULL);
Maxime Ripardae56d972017-08-23 10:08:29 +0200836
837 boot = sunxi_get_boot_device();
Hans de Goededa0ff7c2016-06-26 13:34:42 +0200838 /* determine if we are running in FEL mode */
Maxime Ripardae56d972017-08-23 10:08:29 +0200839 if (boot == BOOT_DEVICE_BOARD) {
Simon Glass6a38e412017-08-03 12:22:09 -0600840 env_set("fel_booted", "1");
Hans de Goededa0ff7c2016-06-26 13:34:42 +0200841 parse_spl_header(SPL_ADDR);
Maxime Ripard65cefba2017-08-23 10:12:22 +0200842 /* or if we booted from MMC, and which one */
843 } else if (boot == BOOT_DEVICE_MMC1) {
844 env_set("mmc_bootdev", "0");
845 } else if (boot == BOOT_DEVICE_MMC2) {
846 env_set("mmc_bootdev", "1");
Hans de Goededa0ff7c2016-06-26 13:34:42 +0200847 }
Hans de Goededa0ff7c2016-06-26 13:34:42 +0200848
Samuel Holland87f940a2020-10-24 10:21:54 -0500849 /* Set fdtfile to match the FIT configuration chosen in SPL. */
850 spl_dt_name = get_spl_dt_name();
851 if (spl_dt_name) {
852 char *prefix = IS_ENABLED(CONFIG_ARM64) ? "allwinner/" : "";
853 char str[64];
854
855 snprintf(str, sizeof(str), "%s%s.dtb", prefix, spl_dt_name);
856 env_set("fdtfile", str);
857 }
858
Hans de Goededa0ff7c2016-06-26 13:34:42 +0200859 setup_environment(gd->fdt_blob);
Jonathan Liuabc1aae2014-06-14 08:59:09 +0200860
Andy Shevchenko1facc0f2020-12-08 17:45:31 +0200861 return 0;
862}
863
864int board_late_init(void)
865{
Icenowy Zhengf4116b62017-09-28 22:16:38 +0800866#ifdef CONFIG_USB_ETHER
Maxime Ripardf54aba32017-09-06 22:25:03 +0200867 usb_ether_init();
Icenowy Zhengf4116b62017-09-28 22:16:38 +0800868#endif
Maxime Ripardf54aba32017-09-06 22:25:03 +0200869
Jonathan Liuabc1aae2014-06-14 08:59:09 +0200870 return 0;
871}
Luc Verhaegen4869a8c2014-08-13 07:55:07 +0200872
Andre Heiderbf8c8102021-10-01 19:29:00 +0100873static void bluetooth_dt_fixup(void *blob)
874{
875 /* Some devices ship with a Bluetooth controller default address.
876 * Set a valid address through the device tree.
877 */
878 uchar tmp[ETH_ALEN], bdaddr[ETH_ALEN];
879 unsigned int sid[4];
880 int i;
881
882 if (!CONFIG_BLUETOOTH_DT_DEVICE_FIXUP[0])
883 return;
884
885 if (eth_env_get_enetaddr("bdaddr", tmp)) {
886 /* Convert between the binary formats of the corresponding stacks */
887 for (i = 0; i < ETH_ALEN; ++i)
888 bdaddr[i] = tmp[ETH_ALEN - i - 1];
889 } else {
890 if (!get_unique_sid(sid))
891 return;
892
893 bdaddr[0] = ((sid[3] >> 0) & 0xff) ^ 1;
894 bdaddr[1] = (sid[3] >> 8) & 0xff;
895 bdaddr[2] = (sid[3] >> 16) & 0xff;
896 bdaddr[3] = (sid[3] >> 24) & 0xff;
897 bdaddr[4] = (sid[0] >> 0) & 0xff;
898 bdaddr[5] = 0x02;
899 }
900
901 do_fixup_by_compat(blob, CONFIG_BLUETOOTH_DT_DEVICE_FIXUP,
902 "local-bd-address", bdaddr, ETH_ALEN, 1);
903}
904
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +0900905int ft_board_setup(void *blob, struct bd_info *bd)
Luc Verhaegen4869a8c2014-08-13 07:55:07 +0200906{
Hans de Goede48a234a2016-03-22 22:51:52 +0100907 int __maybe_unused r;
908
Hans de Goededa0ff7c2016-06-26 13:34:42 +0200909 /*
Icenowy Zheng5a1456b2021-09-11 19:39:16 +0200910 * Call setup_environment and fdt_fixup_ethernet again
911 * in case the boot fdt has ethernet aliases the u-boot
912 * copy does not have.
Hans de Goededa0ff7c2016-06-26 13:34:42 +0200913 */
914 setup_environment(blob);
Icenowy Zheng5a1456b2021-09-11 19:39:16 +0200915 fdt_fixup_ethernet(blob);
Hans de Goededa0ff7c2016-06-26 13:34:42 +0200916
Andre Heiderbf8c8102021-10-01 19:29:00 +0100917 bluetooth_dt_fixup(blob);
918
Luc Verhaegen4869a8c2014-08-13 07:55:07 +0200919#ifdef CONFIG_VIDEO_DT_SIMPLEFB
Hans de Goede48a234a2016-03-22 22:51:52 +0100920 r = sunxi_simplefb_setup(blob);
921 if (r)
922 return r;
Luc Verhaegen4869a8c2014-08-13 07:55:07 +0200923#endif
Hans de Goede48a234a2016-03-22 22:51:52 +0100924 return 0;
Luc Verhaegen4869a8c2014-08-13 07:55:07 +0200925}
Andre Przywara1bd5ca32017-04-26 01:32:44 +0100926
927#ifdef CONFIG_SPL_LOAD_FIT
Samuel Holland64933e92020-10-24 10:21:53 -0500928static void set_spl_dt_name(const char *name)
929{
930 struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
931
932 if (spl == INVALID_SPL_HEADER)
933 return;
934
935 /* Promote the header version for U-Boot proper, if needed. */
936 if (spl->spl_signature[3] < SPL_DT_HEADER_VERSION)
937 spl->spl_signature[3] = SPL_DT_HEADER_VERSION;
938
939 strcpy((char *)&spl->string_pool, name);
940 spl->dt_name_offset = offsetof(struct boot_file_head, string_pool);
941}
942
Andre Przywara1bd5ca32017-04-26 01:32:44 +0100943int board_fit_config_name_match(const char *name)
944{
Samuel Hollandba44e942020-10-24 10:21:50 -0500945 const char *best_dt_name = get_spl_dt_name();
Samuel Holland64933e92020-10-24 10:21:53 -0500946 int ret;
Andre Przywara1bd5ca32017-04-26 01:32:44 +0100947
948#ifdef CONFIG_DEFAULT_DEVICE_TREE
Samuel Hollandba44e942020-10-24 10:21:50 -0500949 if (best_dt_name == NULL)
Samuel Holland37b86202020-10-24 10:21:49 -0500950 best_dt_name = CONFIG_DEFAULT_DEVICE_TREE;
Andre Przywara1bd5ca32017-04-26 01:32:44 +0100951#endif
952
Samuel Hollandba44e942020-10-24 10:21:50 -0500953 if (best_dt_name == NULL) {
954 /* No DT name was provided, so accept the first config. */
955 return 0;
956 }
Icenowy Zheng2a269d32018-10-25 17:23:02 +0800957#ifdef CONFIG_PINE64_DT_SELECTION
Samuel Hollandf2352dd2020-10-24 10:21:51 -0500958 if (strstr(best_dt_name, "-pine64-plus")) {
959 /* Differentiate the Pine A64 boards by their DRAM size. */
960 if ((gd->ram_size == 512 * 1024 * 1024))
961 best_dt_name = "sun50i-a64-pine64";
Andre Przywara1bd5ca32017-04-26 01:32:44 +0100962 }
Icenowy Zheng2a269d32018-10-25 17:23:02 +0800963#endif
Samuel Holland9c7cefc2020-10-24 10:21:52 -0500964#ifdef CONFIG_PINEPHONE_DT_SELECTION
965 if (strstr(best_dt_name, "-pinephone")) {
966 /* Differentiate the PinePhone revisions by GPIO inputs. */
967 prcm_apb0_enable(PRCM_APB0_GATE_PIO);
968 sunxi_gpio_set_pull(SUNXI_GPL(6), SUNXI_GPIO_PULL_UP);
969 sunxi_gpio_set_cfgpin(SUNXI_GPL(6), SUNXI_GPIO_INPUT);
970 udelay(100);
971
972 /* PL6 is pulled low by the modem on v1.2. */
973 if (gpio_get_value(SUNXI_GPL(6)) == 0)
974 best_dt_name = "sun50i-a64-pinephone-1.2";
975 else
976 best_dt_name = "sun50i-a64-pinephone-1.1";
977
978 sunxi_gpio_set_cfgpin(SUNXI_GPL(6), SUNXI_GPIO_DISABLE);
979 sunxi_gpio_set_pull(SUNXI_GPL(6), SUNXI_GPIO_PULL_DISABLE);
980 prcm_apb0_disable(PRCM_APB0_GATE_PIO);
981 }
982#endif
983
Samuel Holland64933e92020-10-24 10:21:53 -0500984 ret = strcmp(name, best_dt_name);
985
986 /*
987 * If one of the FIT configurations matches the most accurate DT name,
988 * update the SPL header to provide that DT name to U-Boot proper.
989 */
990 if (ret == 0)
991 set_spl_dt_name(best_dt_name);
992
993 return ret;
Andre Przywara1bd5ca32017-04-26 01:32:44 +0100994}
Andre Przywaraa9aab242022-11-28 00:02:56 +0000995#endif /* CONFIG_SPL_LOAD_FIT */