Masahiro Yamada | cc85b7b | 2015-07-26 02:46:26 +0900 | [diff] [blame] | 1 | # |
| 2 | # Multifunction miscellaneous devices |
| 3 | # |
| 4 | |
| 5 | menu "Multifunction device drivers" |
| 6 | |
Thomas Chou | b1ed686 | 2015-10-07 20:20:51 +0800 | [diff] [blame] | 7 | config MISC |
| 8 | bool "Enable Driver Model for Misc drivers" |
| 9 | depends on DM |
| 10 | help |
| 11 | Enable driver model for miscellaneous devices. This class is |
| 12 | used only for those do not fit other more general classes. A |
| 13 | set of generic read, write and ioctl methods may be used to |
| 14 | access the device. |
| 15 | |
Simon Glass | 605931c | 2018-11-18 08:14:27 -0700 | [diff] [blame] | 16 | config SPL_MISC |
| 17 | bool "Enable Driver Model for Misc drivers in SPL" |
| 18 | depends on SPL_DM |
Sean Anderson | 63c318f | 2022-04-22 16:11:37 -0400 | [diff] [blame] | 19 | default MISC |
Simon Glass | 605931c | 2018-11-18 08:14:27 -0700 | [diff] [blame] | 20 | help |
| 21 | Enable driver model for miscellaneous devices. This class is |
| 22 | used only for those do not fit other more general classes. A |
| 23 | set of generic read, write and ioctl methods may be used to |
| 24 | access the device. |
| 25 | |
| 26 | config TPL_MISC |
| 27 | bool "Enable Driver Model for Misc drivers in TPL" |
| 28 | depends on TPL_DM |
Sean Anderson | 63c318f | 2022-04-22 16:11:37 -0400 | [diff] [blame] | 29 | default MISC |
| 30 | help |
| 31 | Enable driver model for miscellaneous devices. This class is |
| 32 | used only for those do not fit other more general classes. A |
| 33 | set of generic read, write and ioctl methods may be used to |
| 34 | access the device. |
| 35 | |
| 36 | config VPL_MISC |
| 37 | bool "Enable Driver Model for Misc drivers in VPL" |
| 38 | depends on VPL_DM |
| 39 | default MISC |
Simon Glass | 605931c | 2018-11-18 08:14:27 -0700 | [diff] [blame] | 40 | help |
| 41 | Enable driver model for miscellaneous devices. This class is |
| 42 | used only for those do not fit other more general classes. A |
| 43 | set of generic read, write and ioctl methods may be used to |
| 44 | access the device. |
| 45 | |
Sean Anderson | 77c6629 | 2022-05-05 13:11:39 -0400 | [diff] [blame] | 46 | config NVMEM |
| 47 | bool "NVMEM support" |
| 48 | help |
| 49 | This adds support for a common interface to different types of |
| 50 | non-volatile memory. Consumers can use nvmem-cells properties to look |
| 51 | up hardware configuration data such as MAC addresses and calibration |
| 52 | settings. |
| 53 | |
| 54 | config SPL_NVMEM |
| 55 | bool "NVMEM support in SPL" |
| 56 | help |
| 57 | This adds support for a common interface to different types of |
| 58 | non-volatile memory. Consumers can use nvmem-cells properties to look |
| 59 | up hardware configuration data such as MAC addresses and calibration |
| 60 | settings. |
| 61 | |
Thomas Chou | 36b9c9a | 2015-10-14 08:43:31 +0800 | [diff] [blame] | 62 | config ALTERA_SYSID |
| 63 | bool "Altera Sysid support" |
| 64 | depends on MISC |
| 65 | help |
| 66 | Select this to enable a sysid for Altera devices. Please find |
| 67 | details on the "Embedded Peripherals IP User Guide" of Altera. |
| 68 | |
Marek Behún | ef2b6b1 | 2017-06-09 19:28:44 +0200 | [diff] [blame] | 69 | config ATSHA204A |
| 70 | bool "Support for Atmel ATSHA204A module" |
Pali Rohár | 2e26930 | 2022-04-12 11:20:44 +0200 | [diff] [blame] | 71 | select BITREVERSE |
Marek Behún | ef2b6b1 | 2017-06-09 19:28:44 +0200 | [diff] [blame] | 72 | depends on MISC |
| 73 | help |
| 74 | Enable support for I2C connected Atmel's ATSHA204A |
| 75 | CryptoAuthentication module found for example on the Turris Omnia |
| 76 | board. |
| 77 | |
Tim Harvey | b820460 | 2022-03-07 16:24:04 -0800 | [diff] [blame] | 78 | config GATEWORKS_SC |
| 79 | bool "Gateworks System Controller Support" |
| 80 | depends on MISC |
| 81 | help |
| 82 | Enable access for the Gateworks System Controller used on Gateworks |
| 83 | boards to provide a boot watchdog, power control, temperature monitor, |
| 84 | voltage ADCs, and EEPROM. |
| 85 | |
Philipp Tomsich | fcc1d63 | 2017-05-05 19:21:38 +0200 | [diff] [blame] | 86 | config ROCKCHIP_EFUSE |
| 87 | bool "Rockchip e-fuse support" |
| 88 | depends on MISC |
| 89 | help |
| 90 | Enable (read-only) access for the e-fuse block found in Rockchip |
| 91 | SoCs: accesses can either be made using byte addressing and a length |
| 92 | or through child-nodes that are generated based on the e-fuse map |
| 93 | retrieved from the DTS. |
| 94 | |
Finley Xiao | 20d52a0 | 2019-09-25 17:57:49 +0200 | [diff] [blame] | 95 | config ROCKCHIP_OTP |
| 96 | bool "Rockchip OTP Support" |
| 97 | depends on MISC |
| 98 | help |
| 99 | Enable (read-only) access for the one-time-programmable memory block |
| 100 | found in Rockchip SoCs: accesses can either be made using byte |
| 101 | addressing and a length or through child-nodes that are generated |
| 102 | based on the e-fuse map retrieved from the DTS. |
| 103 | |
Jonas Karlman | a937c3d | 2023-08-21 22:30:28 +0000 | [diff] [blame] | 104 | config ROCKCHIP_IODOMAIN |
| 105 | bool "Rockchip IO-domain driver support" |
| 106 | depends on DM_REGULATOR && ARCH_ROCKCHIP |
| 107 | default y if ROCKCHIP_RK3568 |
| 108 | help |
| 109 | Enable support for IO-domains in Rockchip SoCs. It is necessary |
| 110 | for the IO-domain setting of the SoC to match the voltage supplied |
| 111 | by the regulators. |
| 112 | |
Pragnesh Patel | 6e9661f | 2020-05-29 11:33:21 +0530 | [diff] [blame] | 113 | config SIFIVE_OTP |
| 114 | bool "SiFive eMemory OTP driver" |
| 115 | depends on MISC |
| 116 | help |
| 117 | Enable support for reading and writing the eMemory OTP on the |
| 118 | SiFive SoCs. |
| 119 | |
Tom Rini | 035e872 | 2022-11-19 18:45:33 -0500 | [diff] [blame] | 120 | config SMSC_LPC47M |
| 121 | bool "LPC47M SMSC driver" |
| 122 | |
| 123 | config SMSC_SIO1007 |
| 124 | bool "SIO1007 SMSC driver" |
| 125 | |
Liviu Dudau | 688db7f | 2018-09-28 13:43:31 +0100 | [diff] [blame] | 126 | config VEXPRESS_CONFIG |
| 127 | bool "Enable support for Arm Versatile Express config bus" |
| 128 | depends on MISC |
| 129 | help |
| 130 | If you say Y here, you will get support for accessing the |
| 131 | configuration bus on the Arm Versatile Express boards via |
| 132 | a sysreg driver. |
| 133 | |
Simon Glass | 036ca14 | 2023-09-10 13:13:02 -0600 | [diff] [blame] | 134 | config CBMEM_CONSOLE |
| 135 | bool "Write console output to coreboot cbmem" |
| 136 | depends on X86 |
| 137 | help |
| 138 | Enables console output to the cbmem console, which is a memory |
| 139 | region set up by coreboot to hold a record of all console output. |
| 140 | Enable this only if booting from coreboot. |
| 141 | |
Simon Glass | 5b79bb2 | 2015-02-13 12:20:47 -0700 | [diff] [blame] | 142 | config CMD_CROS_EC |
| 143 | bool "Enable crosec command" |
| 144 | depends on CROS_EC |
| 145 | help |
| 146 | Enable command-line access to the Chrome OS EC (Embedded |
| 147 | Controller). This provides the 'crosec' command which has |
| 148 | a number of sub-commands for performing EC tasks such as |
| 149 | updating its flash, accessing a small saved context area |
| 150 | and talking to the I2C bus behind the EC (if there is one). |
| 151 | |
| 152 | config CROS_EC |
| 153 | bool "Enable Chrome OS EC" |
| 154 | help |
| 155 | Enable access to the Chrome OS EC. This is a separate |
| 156 | microcontroller typically available on a SPI bus on Chromebooks. It |
| 157 | provides access to the keyboard, some internal storage and may |
| 158 | control access to the battery and main PMIC depending on the |
| 159 | device. You can use the 'crosec' command to access it. |
| 160 | |
Simon Glass | 605931c | 2018-11-18 08:14:27 -0700 | [diff] [blame] | 161 | config SPL_CROS_EC |
| 162 | bool "Enable Chrome OS EC in SPL" |
Tom Rini | 0f311f2 | 2022-05-10 12:51:47 -0400 | [diff] [blame] | 163 | depends on SPL_MISC |
Simon Glass | 605931c | 2018-11-18 08:14:27 -0700 | [diff] [blame] | 164 | help |
| 165 | Enable access to the Chrome OS EC in SPL. This is a separate |
| 166 | microcontroller typically available on a SPI bus on Chromebooks. It |
| 167 | provides access to the keyboard, some internal storage and may |
| 168 | control access to the battery and main PMIC depending on the |
| 169 | device. You can use the 'crosec' command to access it. |
| 170 | |
| 171 | config TPL_CROS_EC |
| 172 | bool "Enable Chrome OS EC in TPL" |
Tom Rini | 0f311f2 | 2022-05-10 12:51:47 -0400 | [diff] [blame] | 173 | depends on TPL_MISC |
Simon Glass | 605931c | 2018-11-18 08:14:27 -0700 | [diff] [blame] | 174 | help |
| 175 | Enable access to the Chrome OS EC in TPL. This is a separate |
| 176 | microcontroller typically available on a SPI bus on Chromebooks. It |
| 177 | provides access to the keyboard, some internal storage and may |
| 178 | control access to the battery and main PMIC depending on the |
| 179 | device. You can use the 'crosec' command to access it. |
| 180 | |
Simon Glass | e7ca7da | 2022-04-30 00:56:53 -0600 | [diff] [blame] | 181 | config VPL_CROS_EC |
| 182 | bool "Enable Chrome OS EC in VPL" |
Tom Rini | 0f311f2 | 2022-05-10 12:51:47 -0400 | [diff] [blame] | 183 | depends on VPL_MISC |
Simon Glass | e7ca7da | 2022-04-30 00:56:53 -0600 | [diff] [blame] | 184 | help |
| 185 | Enable access to the Chrome OS EC in VPL. This is a separate |
| 186 | microcontroller typically available on a SPI bus on Chromebooks. It |
| 187 | provides access to the keyboard, some internal storage and may |
| 188 | control access to the battery and main PMIC depending on the |
| 189 | device. You can use the 'crosec' command to access it. |
| 190 | |
Simon Glass | 5b79bb2 | 2015-02-13 12:20:47 -0700 | [diff] [blame] | 191 | config CROS_EC_I2C |
| 192 | bool "Enable Chrome OS EC I2C driver" |
| 193 | depends on CROS_EC |
| 194 | help |
| 195 | Enable I2C access to the Chrome OS EC. This is used on older |
| 196 | ARM Chromebooks such as snow and spring before the standard bus |
| 197 | changed to SPI. The EC will accept commands across the I2C using |
| 198 | a special message protocol, and provide responses. |
| 199 | |
| 200 | config CROS_EC_LPC |
| 201 | bool "Enable Chrome OS EC LPC driver" |
| 202 | depends on CROS_EC |
| 203 | help |
| 204 | Enable I2C access to the Chrome OS EC. This is used on x86 |
| 205 | Chromebooks such as link and falco. The keyboard is provided |
| 206 | through a legacy port interface, so on x86 machines the main |
| 207 | function of the EC is power and thermal management. |
| 208 | |
Simon Glass | 605931c | 2018-11-18 08:14:27 -0700 | [diff] [blame] | 209 | config SPL_CROS_EC_LPC |
| 210 | bool "Enable Chrome OS EC LPC driver in SPL" |
Tom Rini | 0f311f2 | 2022-05-10 12:51:47 -0400 | [diff] [blame] | 211 | depends on CROS_EC && SPL_MISC |
Simon Glass | 605931c | 2018-11-18 08:14:27 -0700 | [diff] [blame] | 212 | help |
| 213 | Enable I2C access to the Chrome OS EC. This is used on x86 |
| 214 | Chromebooks such as link and falco. The keyboard is provided |
| 215 | through a legacy port interface, so on x86 machines the main |
| 216 | function of the EC is power and thermal management. |
| 217 | |
| 218 | config TPL_CROS_EC_LPC |
| 219 | bool "Enable Chrome OS EC LPC driver in TPL" |
Tom Rini | 0f311f2 | 2022-05-10 12:51:47 -0400 | [diff] [blame] | 220 | depends on CROS_EC && TPL_MISC |
Simon Glass | 605931c | 2018-11-18 08:14:27 -0700 | [diff] [blame] | 221 | help |
| 222 | Enable I2C access to the Chrome OS EC. This is used on x86 |
| 223 | Chromebooks such as link and falco. The keyboard is provided |
| 224 | through a legacy port interface, so on x86 machines the main |
| 225 | function of the EC is power and thermal management. |
| 226 | |
Simon Glass | e7ca7da | 2022-04-30 00:56:53 -0600 | [diff] [blame] | 227 | config VPL_CROS_EC_LPC |
| 228 | bool "Enable Chrome OS EC LPC driver in VPL" |
Tom Rini | 0f311f2 | 2022-05-10 12:51:47 -0400 | [diff] [blame] | 229 | depends on CROS_EC && VPL_MISC |
Simon Glass | e7ca7da | 2022-04-30 00:56:53 -0600 | [diff] [blame] | 230 | help |
| 231 | Enable I2C access to the Chrome OS EC. This is used on x86 |
| 232 | Chromebooks such as link and falco. The keyboard is provided |
| 233 | through a legacy port interface, so on x86 machines the main |
| 234 | function of the EC is power and thermal management. |
| 235 | |
Simon Glass | c6e0669 | 2015-03-26 09:29:40 -0600 | [diff] [blame] | 236 | config CROS_EC_SANDBOX |
| 237 | bool "Enable Chrome OS EC sandbox driver" |
| 238 | depends on CROS_EC && SANDBOX |
| 239 | help |
| 240 | Enable a sandbox emulation of the Chrome OS EC. This supports |
| 241 | keyboard (use the -l flag to enable the LCD), verified boot context, |
| 242 | EC flash read/write/erase support and a few other things. It is |
| 243 | enough to perform a Chrome OS verified boot on sandbox. |
| 244 | |
Simon Glass | 605931c | 2018-11-18 08:14:27 -0700 | [diff] [blame] | 245 | config SPL_CROS_EC_SANDBOX |
| 246 | bool "Enable Chrome OS EC sandbox driver in SPL" |
| 247 | depends on SPL_CROS_EC && SANDBOX |
| 248 | help |
| 249 | Enable a sandbox emulation of the Chrome OS EC in SPL. This supports |
| 250 | keyboard (use the -l flag to enable the LCD), verified boot context, |
| 251 | EC flash read/write/erase support and a few other things. It is |
| 252 | enough to perform a Chrome OS verified boot on sandbox. |
| 253 | |
| 254 | config TPL_CROS_EC_SANDBOX |
| 255 | bool "Enable Chrome OS EC sandbox driver in TPL" |
| 256 | depends on TPL_CROS_EC && SANDBOX |
| 257 | help |
| 258 | Enable a sandbox emulation of the Chrome OS EC in TPL. This supports |
| 259 | keyboard (use the -l flag to enable the LCD), verified boot context, |
| 260 | EC flash read/write/erase support and a few other things. It is |
| 261 | enough to perform a Chrome OS verified boot on sandbox. |
| 262 | |
Simon Glass | e7ca7da | 2022-04-30 00:56:53 -0600 | [diff] [blame] | 263 | config VPL_CROS_EC_SANDBOX |
| 264 | bool "Enable Chrome OS EC sandbox driver in VPL" |
| 265 | depends on VPL_CROS_EC && SANDBOX |
| 266 | help |
| 267 | Enable a sandbox emulation of the Chrome OS EC in VPL. This supports |
| 268 | keyboard (use the -l flag to enable the LCD), verified boot context, |
| 269 | EC flash read/write/erase support and a few other things. It is |
| 270 | enough to perform a Chrome OS verified boot on sandbox. |
| 271 | |
Simon Glass | 5b79bb2 | 2015-02-13 12:20:47 -0700 | [diff] [blame] | 272 | config CROS_EC_SPI |
| 273 | bool "Enable Chrome OS EC SPI driver" |
| 274 | depends on CROS_EC |
| 275 | help |
| 276 | Enable SPI access to the Chrome OS EC. This is used on newer |
| 277 | ARM Chromebooks such as pit, pi and nyan-big. The SPI interface |
| 278 | provides a faster and more robust interface than I2C but the bugs |
| 279 | are less interesting. |
| 280 | |
Simon Glass | 58ed322 | 2017-05-17 03:25:02 -0600 | [diff] [blame] | 281 | config DS4510 |
| 282 | bool "Enable support for DS4510 CPU supervisor" |
| 283 | help |
| 284 | Enable support for the Maxim DS4510 CPU supervisor. It has an |
| 285 | integrated 64-byte EEPROM, four programmable non-volatile I/O pins |
| 286 | and a configurable timer for the supervisor function. The device is |
| 287 | connected over I2C. |
| 288 | |
Tom Rini | 66fa77a | 2022-11-19 18:45:11 -0500 | [diff] [blame] | 289 | config FSL_IIM |
| 290 | bool "Enable FSL IC Identification Module (IIM) driver" |
| 291 | depends on ARCH_MX31 || ARCH_MX5 |
| 292 | |
Peng Fan | fb6166a | 2015-08-26 15:41:33 +0800 | [diff] [blame] | 293 | config FSL_SEC_MON |
gaurav rana | 9aaea44 | 2015-02-27 09:44:22 +0530 | [diff] [blame] | 294 | bool "Enable FSL SEC_MON Driver" |
| 295 | help |
| 296 | Freescale Security Monitor block is responsible for monitoring |
| 297 | system states. |
| 298 | Security Monitor can be transitioned on any security failures, |
| 299 | like software violations or hardware security violations. |
Stefan Roese | 04b2275 | 2015-03-12 11:22:46 +0100 | [diff] [blame] | 300 | |
Tom Rini | 0b58c2e | 2022-06-16 14:04:39 -0400 | [diff] [blame] | 301 | choice |
| 302 | prompt "Security monitor interaction endianess" |
| 303 | depends on FSL_SEC_MON |
| 304 | default SYS_FSL_SEC_MON_BE if PPC |
| 305 | default SYS_FSL_SEC_MON_LE |
| 306 | |
| 307 | config SYS_FSL_SEC_MON_LE |
| 308 | bool "Security monitor interactions are little endian" |
| 309 | |
| 310 | config SYS_FSL_SEC_MON_BE |
| 311 | bool "Security monitor interactions are big endian" |
| 312 | |
| 313 | endchoice |
| 314 | |
Simon Glass | ff418d9 | 2019-12-06 21:41:58 -0700 | [diff] [blame] | 315 | config IRQ |
Wasim Khan | 55c9b9c | 2021-03-08 16:48:13 +0100 | [diff] [blame] | 316 | bool "Interrupt controller" |
Simon Glass | ff418d9 | 2019-12-06 21:41:58 -0700 | [diff] [blame] | 317 | help |
Wasim Khan | 55c9b9c | 2021-03-08 16:48:13 +0100 | [diff] [blame] | 318 | This enables support for interrupt controllers, including ITSS. |
Simon Glass | ff418d9 | 2019-12-06 21:41:58 -0700 | [diff] [blame] | 319 | Some devices have extra features, such as Apollo Lake. The |
| 320 | device has its own uclass since there are several operations |
| 321 | involved. |
| 322 | |
Paul Burton | 738d8a8 | 2018-12-16 19:25:19 -0300 | [diff] [blame] | 323 | config JZ4780_EFUSE |
| 324 | bool "Ingenic JZ4780 eFUSE support" |
| 325 | depends on ARCH_JZ47XX |
| 326 | help |
| 327 | This selects support for the eFUSE on Ingenic JZ4780 SoCs. |
| 328 | |
Sean Anderson | 6b39d35 | 2022-04-22 14:34:18 -0400 | [diff] [blame] | 329 | config LS2_SFP |
| 330 | bool "Layerscape Security Fuse Processor" |
| 331 | depends on FSL_LSCH2 || ARCH_LS1021A |
| 332 | depends on MISC |
| 333 | imply DM_REGULATOR |
| 334 | help |
| 335 | This adds support for the Security Fuse Processor found on Layerscape |
| 336 | SoCs. It contains various fuses related to secure boot, including the |
| 337 | Super Root Key hash, One-Time-Programmable Master Key, Debug |
| 338 | Challenge/Response values, and others. Fuses are numbered according |
| 339 | to their four-byte offset from the start of the bank. |
| 340 | |
| 341 | If you don't need to read/program fuses, say 'n'. |
| 342 | |
Peng Fan | e187225 | 2015-08-27 14:49:05 +0800 | [diff] [blame] | 343 | config MXC_OCOTP |
| 344 | bool "Enable MXC OCOTP Driver" |
Peng Fan | c45a81a | 2019-07-22 01:24:55 +0000 | [diff] [blame] | 345 | depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610 |
Marcel Ziswiler | f221314 | 2019-03-25 17:24:57 +0100 | [diff] [blame] | 346 | default y |
Peng Fan | e187225 | 2015-08-27 14:49:05 +0800 | [diff] [blame] | 347 | help |
| 348 | If you say Y here, you will get support for the One Time |
| 349 | Programmable memory pages that are stored on the some |
| 350 | Freescale i.MX processors. |
| 351 | |
Tom Rini | 5a0f9d8 | 2022-11-19 18:45:28 -0500 | [diff] [blame] | 352 | config MXS_OCOTP |
| 353 | bool "Enable MXS OCOTP Driver" |
| 354 | depends on ARCH_MX23 || ARCH_MX28 |
| 355 | help |
| 356 | If you say Y here, you will get support for the One Time |
| 357 | Programmable memory pages that are stored on the |
| 358 | Freescale i.MXS family of processors. |
| 359 | |
Jim Liu | cce4eed | 2022-06-24 16:24:37 +0800 | [diff] [blame] | 360 | config NPCM_HOST |
| 361 | bool "Enable support espi or LPC for Host" |
| 362 | depends on REGMAP && SYSCON |
| 363 | help |
| 364 | Enable NPCM BMC espi or LPC support for Host reading and writing. |
| 365 | |
Michael Scott | 9267614 | 2021-09-25 19:49:28 +0300 | [diff] [blame] | 366 | config SPL_MXC_OCOTP |
| 367 | bool "Enable MXC OCOTP driver in SPL" |
Jean-Marie Lemetayer | f17d43d | 2023-02-13 14:12:25 +0100 | [diff] [blame] | 368 | depends on SPL_DRIVERS_MISC && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610) |
Michael Scott | 9267614 | 2021-09-25 19:49:28 +0300 | [diff] [blame] | 369 | default y |
| 370 | help |
| 371 | If you say Y here, you will get support for the One Time |
| 372 | Programmable memory pages, that are stored on some |
| 373 | Freescale i.MX processors, in SPL. |
| 374 | |
Jim Liu | fab2eff | 2022-06-07 16:33:54 +0800 | [diff] [blame] | 375 | config NPCM_OTP |
| 376 | bool "Nnvoton NPCM BMC On-Chip OTP Memory Support" |
| 377 | depends on (ARM && ARCH_NPCM) |
Jim Liu | fab2eff | 2022-06-07 16:33:54 +0800 | [diff] [blame] | 378 | help |
| 379 | Support NPCM BMC OTP memory (fuse). |
| 380 | To compile this driver as a module, choose M here: the module |
| 381 | will be called npcm_otp. |
| 382 | |
Peng Fan | d5c3183 | 2023-06-15 18:09:05 +0800 | [diff] [blame] | 383 | config IMX_ELE |
| 384 | bool "Enable i.MX EdgeLock Enclave MU driver and API" |
Ye Li | c408ed3 | 2022-07-26 16:40:49 +0800 | [diff] [blame] | 385 | depends on MISC && (ARCH_IMX9 || ARCH_IMX8ULP) |
| 386 | help |
| 387 | If you say Y here to enable Message Unit driver to work with |
| 388 | Sentinel core on some NXP i.MX processors. |
| 389 | |
Stefan Roese | 4a269f2 | 2016-07-19 07:45:46 +0200 | [diff] [blame] | 390 | config NUVOTON_NCT6102D |
| 391 | bool "Enable Nuvoton NCT6102D Super I/O driver" |
| 392 | help |
| 393 | If you say Y here, you will get support for the Nuvoton |
| 394 | NCT6102D Super I/O driver. This can be used to enable or |
| 395 | disable the legacy UART, the watchdog or other devices |
| 396 | in the Nuvoton Super IO chips on X86 platforms. |
| 397 | |
Simon Glass | 2ee1f6a | 2019-12-06 21:41:55 -0700 | [diff] [blame] | 398 | config P2SB |
Wolfgang Wallner | f43b083 | 2020-07-01 13:37:23 +0200 | [diff] [blame] | 399 | bool "Intel Primary to Sideband Bridge" |
Simon Glass | 2ee1f6a | 2019-12-06 21:41:55 -0700 | [diff] [blame] | 400 | depends on X86 || SANDBOX |
| 401 | help |
Wolfgang Wallner | f43b083 | 2020-07-01 13:37:23 +0200 | [diff] [blame] | 402 | This enables support for the Intel Primary to Sideband Bridge, |
Simon Glass | 2ee1f6a | 2019-12-06 21:41:55 -0700 | [diff] [blame] | 403 | abbreviated to P2SB. The P2SB is used to access various peripherals |
| 404 | such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI |
| 405 | space. The space is segmented into different channels and peripherals |
| 406 | are accessed by device-specific means within those channels. Devices |
| 407 | should be added in the device tree as subnodes of the P2SB. A |
| 408 | Peripheral Channel Register? (PCR) API is provided to access those |
| 409 | devices - see pcr_readl(), etc. |
| 410 | |
| 411 | config SPL_P2SB |
Wolfgang Wallner | f43b083 | 2020-07-01 13:37:23 +0200 | [diff] [blame] | 412 | bool "Intel Primary to Sideband Bridge in SPL" |
Tom Rini | 0f311f2 | 2022-05-10 12:51:47 -0400 | [diff] [blame] | 413 | depends on SPL_MISC && (X86 || SANDBOX) |
Simon Glass | 2ee1f6a | 2019-12-06 21:41:55 -0700 | [diff] [blame] | 414 | help |
Wolfgang Wallner | f43b083 | 2020-07-01 13:37:23 +0200 | [diff] [blame] | 415 | The Primary to Sideband Bridge is used to access various peripherals |
Simon Glass | 2ee1f6a | 2019-12-06 21:41:55 -0700 | [diff] [blame] | 416 | through memory-mapped I/O in a large chunk of PCI space. The space is |
| 417 | segmented into different channels and peripherals are accessed by |
| 418 | device-specific means within those channels. Devices should be added |
| 419 | in the device tree as subnodes of the p2sb. |
| 420 | |
| 421 | config TPL_P2SB |
Wolfgang Wallner | f43b083 | 2020-07-01 13:37:23 +0200 | [diff] [blame] | 422 | bool "Intel Primary to Sideband Bridge in TPL" |
Tom Rini | 0f311f2 | 2022-05-10 12:51:47 -0400 | [diff] [blame] | 423 | depends on TPL_MISC && (X86 || SANDBOX) |
Simon Glass | 2ee1f6a | 2019-12-06 21:41:55 -0700 | [diff] [blame] | 424 | help |
Wolfgang Wallner | f43b083 | 2020-07-01 13:37:23 +0200 | [diff] [blame] | 425 | The Primary to Sideband Bridge is used to access various peripherals |
Simon Glass | 2ee1f6a | 2019-12-06 21:41:55 -0700 | [diff] [blame] | 426 | through memory-mapped I/O in a large chunk of PCI space. The space is |
| 427 | segmented into different channels and peripherals are accessed by |
| 428 | device-specific means within those channels. Devices should be added |
| 429 | in the device tree as subnodes of the p2sb. |
| 430 | |
Simon Glass | c979517 | 2016-01-21 19:43:31 -0700 | [diff] [blame] | 431 | config PWRSEQ |
| 432 | bool "Enable power-sequencing drivers" |
| 433 | depends on DM |
| 434 | help |
| 435 | Power-sequencing drivers provide support for controlling power for |
| 436 | devices. They are typically referenced by a phandle from another |
| 437 | device. When the device is started up, its power sequence can be |
| 438 | initiated. |
| 439 | |
| 440 | config SPL_PWRSEQ |
| 441 | bool "Enable power-sequencing drivers for SPL" |
Tom Rini | 0f311f2 | 2022-05-10 12:51:47 -0400 | [diff] [blame] | 442 | depends on SPL_MISC && PWRSEQ |
Simon Glass | c979517 | 2016-01-21 19:43:31 -0700 | [diff] [blame] | 443 | help |
| 444 | Power-sequencing drivers provide support for controlling power for |
| 445 | devices. They are typically referenced by a phandle from another |
| 446 | device. When the device is started up, its power sequence can be |
| 447 | initiated. |
| 448 | |
Stefan Roese | 04b2275 | 2015-03-12 11:22:46 +0100 | [diff] [blame] | 449 | config PCA9551_LED |
| 450 | bool "Enable PCA9551 LED driver" |
| 451 | help |
| 452 | Enable driver for PCA9551 LED controller. This controller |
| 453 | is connected via I2C. So I2C needs to be enabled. |
| 454 | |
| 455 | config PCA9551_I2C_ADDR |
| 456 | hex "I2C address of PCA9551 LED controller" |
| 457 | depends on PCA9551_LED |
| 458 | default 0x60 |
| 459 | help |
| 460 | The I2C address of the PCA9551 LED controller. |
Simon Glass | 1400086 | 2015-06-23 15:39:13 -0600 | [diff] [blame] | 461 | |
Patrick Delaunay | 0c4656b | 2018-05-17 15:24:06 +0200 | [diff] [blame] | 462 | config STM32MP_FUSE |
| 463 | bool "Enable STM32MP fuse wrapper providing the fuse API" |
| 464 | depends on ARCH_STM32MP && MISC |
| 465 | default y if CMD_FUSE |
| 466 | help |
| 467 | If you say Y here, you will get support for the fuse API (OTP) |
| 468 | for STM32MP architecture. |
| 469 | This API is needed for CMD_FUSE. |
| 470 | |
Christophe Kerello | 275f706 | 2017-09-13 18:00:08 +0200 | [diff] [blame] | 471 | config STM32_RCC |
| 472 | bool "Enable RCC driver for the STM32 SoC's family" |
Trevor Woerner | 2bcc1ed | 2020-05-06 08:02:42 -0400 | [diff] [blame] | 473 | depends on (ARCH_STM32 || ARCH_STM32MP) && MISC |
Christophe Kerello | 275f706 | 2017-09-13 18:00:08 +0200 | [diff] [blame] | 474 | help |
| 475 | Enable the STM32 RCC driver. The RCC block (Reset and Clock Control |
| 476 | block) is responsible of the management of the clock and reset |
| 477 | generation. |
| 478 | This driver is similar to an MFD driver in the Linux kernel. |
| 479 | |
Stephen Warren | f641700 | 2016-09-13 10:45:57 -0600 | [diff] [blame] | 480 | config TEGRA_CAR |
| 481 | bool "Enable support for the Tegra CAR driver" |
| 482 | depends on TEGRA_NO_BPMP |
| 483 | help |
| 484 | The Tegra CAR (Clock and Reset Controller) is a HW module that |
| 485 | controls almost all clocks and resets in a Tegra SoC. |
| 486 | |
Stephen Warren | a214892 | 2016-08-08 09:41:34 -0600 | [diff] [blame] | 487 | config TEGRA186_BPMP |
| 488 | bool "Enable support for the Tegra186 BPMP driver" |
| 489 | depends on TEGRA186 |
| 490 | help |
| 491 | The Tegra BPMP (Boot and Power Management Processor) is a separate |
| 492 | auxiliary CPU embedded into Tegra to perform power management work, |
| 493 | and controls related features such as clocks, resets, power domains, |
| 494 | PMIC I2C bus, etc. This driver provides the core low-level |
| 495 | communication path by which feature-specific drivers (such as clock) |
| 496 | can make requests to the BPMP. This driver is similar to an MFD |
| 497 | driver in the Linux kernel. |
| 498 | |
Simon Glass | 4bf8972 | 2020-12-23 08:11:18 -0700 | [diff] [blame] | 499 | config TEST_DRV |
| 500 | bool "Enable support for test drivers" |
| 501 | default y if SANDBOX |
| 502 | help |
| 503 | This enables drivers and uclasses that provides a way of testing the |
| 504 | operations of memory allocation and driver/uclass methods in driver |
| 505 | model. This should only be enabled for testing as it is not useful for |
| 506 | anything else. |
| 507 | |
Marek Vasut | 16637b4 | 2022-04-10 06:27:14 +0200 | [diff] [blame] | 508 | config USB_HUB_USB251XB |
| 509 | tristate "USB251XB Hub Controller Configuration Driver" |
| 510 | depends on I2C |
| 511 | help |
| 512 | This option enables support for configuration via SMBus of the |
| 513 | Microchip USB251x/xBi USB 2.0 Hub Controller series. Configuration |
| 514 | parameters may be set in devicetree or platform data. |
| 515 | Say Y or M here if you need to configure such a device via SMBus. |
| 516 | |
Adam Ford | c8cdce7 | 2018-08-06 14:26:50 -0500 | [diff] [blame] | 517 | config TWL4030_LED |
| 518 | bool "Enable TWL4030 LED controller" |
| 519 | help |
| 520 | Enable this to add support for the TWL4030 LED controller. |
| 521 | |
Stefan Roese | ba019ed | 2016-01-19 14:05:10 +0100 | [diff] [blame] | 522 | config WINBOND_W83627 |
| 523 | bool "Enable Winbond Super I/O driver" |
| 524 | help |
| 525 | If you say Y here, you will get support for the Winbond |
| 526 | W83627 Super I/O driver. This can be used to enable the |
| 527 | legacy UART or other devices in the Winbond Super IO chips |
| 528 | on X86 platforms. |
| 529 | |
Vladimir Zapolskiy | f7a6429 | 2023-04-21 20:50:33 +0300 | [diff] [blame] | 530 | config QCOM_GENI_SE |
| 531 | bool "Qualcomm GENI Serial Engine Driver" |
| 532 | depends on ARCH_SNAPDRAGON |
| 533 | help |
| 534 | The driver manages Generic Interface (GENI) firmware based |
| 535 | Qualcomm Technologies, Inc. Universal Peripheral (QUP) Wrapper. |
| 536 | |
Miao Yan | 4fcd7f2 | 2016-05-22 19:37:14 -0700 | [diff] [blame] | 537 | config QFW |
| 538 | bool |
| 539 | help |
Asherah Connor | 4ffa95d | 2021-03-19 18:21:40 +1100 | [diff] [blame] | 540 | Hidden option to enable QEMU fw_cfg interface and uclass. This will |
| 541 | be selected by either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE. |
| 542 | |
| 543 | config QFW_PIO |
| 544 | bool |
| 545 | depends on QFW |
| 546 | help |
| 547 | Hidden option to enable PIO QEMU fw_cfg interface. This will be |
| 548 | selected by the appropriate QEMU board. |
Miao Yan | 4fcd7f2 | 2016-05-22 19:37:14 -0700 | [diff] [blame] | 549 | |
Asherah Connor | f0c0e54 | 2021-03-19 18:21:42 +1100 | [diff] [blame] | 550 | config QFW_MMIO |
| 551 | bool |
| 552 | depends on QFW |
| 553 | help |
| 554 | Hidden option to enable MMIO QEMU fw_cfg interface. This will be |
| 555 | selected by the appropriate QEMU board. |
| 556 | |
mario.six@gdsys.cc | 7559ac4 | 2016-06-22 15:14:16 +0200 | [diff] [blame] | 557 | config I2C_EEPROM |
| 558 | bool "Enable driver for generic I2C-attached EEPROMs" |
| 559 | depends on MISC |
| 560 | help |
| 561 | Enable a generic driver for EEPROMs attached via I2C. |
Adam Ford | 5664f83 | 2017-08-13 09:00:28 -0500 | [diff] [blame] | 562 | |
Wenyou Yang | f791d56 | 2017-09-06 13:08:14 +0800 | [diff] [blame] | 563 | |
| 564 | config SPL_I2C_EEPROM |
| 565 | bool "Enable driver for generic I2C-attached EEPROMs for SPL" |
Tom Rini | 0f311f2 | 2022-05-10 12:51:47 -0400 | [diff] [blame] | 566 | depends on SPL_MISC |
Wenyou Yang | f791d56 | 2017-09-06 13:08:14 +0800 | [diff] [blame] | 567 | help |
| 568 | This option is an SPL-variant of the I2C_EEPROM option. |
| 569 | See the help of I2C_EEPROM for details. |
| 570 | |
Adam Ford | 5664f83 | 2017-08-13 09:00:28 -0500 | [diff] [blame] | 571 | config SYS_I2C_EEPROM_ADDR |
| 572 | hex "Chip address of the EEPROM device" |
Tom Rini | faed567 | 2021-08-17 17:59:45 -0400 | [diff] [blame] | 573 | depends on ID_EEPROM || I2C_EEPROM || SPL_I2C_EEPROM || CMD_EEPROM || ENV_IS_IN_EEPROM |
Tom Rini | f18679c | 2023-08-02 11:09:43 -0400 | [diff] [blame] | 574 | default 0x0 |
Adam Ford | 5664f83 | 2017-08-13 09:00:28 -0500 | [diff] [blame] | 575 | |
Tom Rini | faed567 | 2021-08-17 17:59:45 -0400 | [diff] [blame] | 576 | if I2C_EEPROM |
Adam Ford | 5664f83 | 2017-08-13 09:00:28 -0500 | [diff] [blame] | 577 | |
| 578 | config SYS_I2C_EEPROM_ADDR_OVERFLOW |
| 579 | hex "EEPROM Address Overflow" |
Tom Rini | f059955 | 2021-12-11 14:55:47 -0500 | [diff] [blame] | 580 | default 0x0 |
Adam Ford | 5664f83 | 2017-08-13 09:00:28 -0500 | [diff] [blame] | 581 | help |
| 582 | EEPROM chips that implement "address overflow" are ones |
| 583 | like Catalyst 24WC04/08/16 which has 9/10/11 bits of |
| 584 | address and the extra bits end up in the "chip address" bit |
| 585 | slots. This makes a 24WC08 (1Kbyte) chip look like four 256 |
| 586 | byte chips. |
| 587 | |
| 588 | endif |
| 589 | |
Mario Six | 7f504a0 | 2018-04-27 14:53:33 +0200 | [diff] [blame] | 590 | config GDSYS_RXAUI_CTRL |
| 591 | bool "Enable gdsys RXAUI control driver" |
| 592 | depends on MISC |
| 593 | help |
| 594 | Support gdsys FPGA's RXAUI control. |
Mario Six | 0cafb65 | 2018-07-31 14:24:15 +0200 | [diff] [blame] | 595 | |
| 596 | config GDSYS_IOEP |
| 597 | bool "Enable gdsys IOEP driver" |
| 598 | depends on MISC |
| 599 | help |
| 600 | Support gdsys FPGA's IO endpoint driver. |
Mario Six | 7fdcf28 | 2018-08-06 10:23:46 +0200 | [diff] [blame] | 601 | |
| 602 | config MPC83XX_SERDES |
| 603 | bool "Enable MPC83xx serdes driver" |
| 604 | depends on MISC |
| 605 | help |
| 606 | Support for serdes found on MPC83xx SoCs. |
| 607 | |
Tien Fong Chee | 5ca878b | 2018-07-06 16:28:03 +0800 | [diff] [blame] | 608 | config FS_LOADER |
| 609 | bool "Enable loader driver for file system" |
| 610 | help |
| 611 | This is file system generic loader which can be used to load |
| 612 | the file image from the storage into target such as memory. |
| 613 | |
| 614 | The consumer driver would then use this loader to program whatever, |
| 615 | ie. the FPGA device. |
| 616 | |
Keerthy | fe8f609 | 2022-01-27 13:16:53 +0100 | [diff] [blame] | 617 | config SPL_FS_LOADER |
Alexander Gendin | 1c1a884 | 2023-11-20 20:21:51 +0000 | [diff] [blame] | 618 | bool "Enable loader driver for file system in SPL" |
Tom Rini | 0f311f2 | 2022-05-10 12:51:47 -0400 | [diff] [blame] | 619 | depends on SPL |
Keerthy | fe8f609 | 2022-01-27 13:16:53 +0100 | [diff] [blame] | 620 | help |
| 621 | This is file system generic loader which can be used to load |
| 622 | the file image from the storage into target such as memory. |
| 623 | |
| 624 | The consumer driver would then use this loader to program whatever, |
| 625 | ie. the FPGA device. |
| 626 | |
Mario Six | 8862f45 | 2018-10-04 09:00:54 +0200 | [diff] [blame] | 627 | config GDSYS_SOC |
| 628 | bool "Enable gdsys SOC driver" |
| 629 | depends on MISC |
| 630 | help |
| 631 | Support for gdsys IHS SOC, a simple bus associated with each gdsys |
| 632 | IHS (Integrated Hardware Systems) FPGA, which holds all devices whose |
| 633 | register maps are contained within the FPGA's register map. |
| 634 | |
Mario Six | 1a9d43f | 2018-10-04 09:00:55 +0200 | [diff] [blame] | 635 | config IHS_FPGA |
| 636 | bool "Enable IHS FPGA driver" |
| 637 | depends on MISC |
| 638 | help |
| 639 | Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on |
| 640 | gdsys devices, which supply the majority of the functionality offered |
| 641 | by the devices. This driver supports both CON and CPU variants of the |
| 642 | devices, depending on the device tree entry. |
Tero Kristo | f81f4cd | 2020-02-14 11:18:15 +0200 | [diff] [blame] | 643 | config ESM_K3 |
| 644 | bool "Enable K3 ESM driver" |
| 645 | depends on ARCH_K3 |
| 646 | help |
| 647 | Support ESM (Error Signaling Module) on TI K3 SoCs. |
Mario Six | 1a9d43f | 2018-10-04 09:00:55 +0200 | [diff] [blame] | 648 | |
Eugen Hristev | 3bd5610 | 2019-10-09 09:23:39 +0000 | [diff] [blame] | 649 | config MICROCHIP_FLEXCOM |
| 650 | bool "Enable Microchip Flexcom driver" |
| 651 | depends on MISC |
| 652 | help |
| 653 | The Atmel Flexcom is just a wrapper which embeds a SPI controller, |
| 654 | an I2C controller and an USART. |
| 655 | Only one function can be used at a time and is chosen at boot time |
| 656 | according to the device tree. |
| 657 | |
Tero Kristo | 887dde5 | 2019-10-24 15:00:46 +0530 | [diff] [blame] | 658 | config K3_AVS0 |
| 659 | depends on ARCH_K3 && SPL_DM_REGULATOR |
| 660 | bool "AVS class 0 support for K3 devices" |
| 661 | help |
| 662 | K3 devices have the optimized voltage values for the main voltage |
| 663 | domains stored in efuse within the VTM IP. This driver reads the |
| 664 | optimized voltage from the efuse, so that it can be programmed |
| 665 | to the PMIC on board. |
| 666 | |
Tero Kristo | 1444e11 | 2020-02-14 11:18:16 +0200 | [diff] [blame] | 667 | config ESM_PMIC |
| 668 | bool "Enable PMIC ESM driver" |
| 669 | depends on DM_PMIC |
| 670 | help |
| 671 | Support ESM (Error Signal Monitor) on PMIC devices. ESM is used |
| 672 | typically to reboot the board in error condition. |
| 673 | |
Tom Rini | 05b419e | 2021-12-11 14:55:49 -0500 | [diff] [blame] | 674 | config FSL_IFC |
| 675 | bool |
| 676 | |
Michael Walle | 2184cc6 | 2022-02-25 18:06:24 +0530 | [diff] [blame] | 677 | config SL28CPLD |
| 678 | bool "Enable Kontron sl28cpld multi-function driver" |
| 679 | depends on DM_I2C |
| 680 | help |
| 681 | Support for the Kontron sl28cpld management controller. This is |
| 682 | the base driver which provides common access methods for the |
| 683 | sub-drivers. |
| 684 | |
Masahiro Yamada | cc85b7b | 2015-07-26 02:46:26 +0900 | [diff] [blame] | 685 | endmenu |