blob: b15926e8247b85c9cdc956a80a0ccbb7f7b74d54 [file] [log] [blame]
Simon Glass466c7852019-12-06 21:42:18 -07001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright 2019 Google LLC
4 */
5
6#include <common.h>
7#include <binman.h>
8#include <binman_sym.h>
Simon Glass1ea97892020-05-10 11:40:00 -06009#include <bootstage.h>
Simon Glass466c7852019-12-06 21:42:18 -070010#include <cbfs.h>
11#include <dm.h>
Simon Glassfc557362022-03-04 08:43:05 -070012#include <event.h>
Simon Glass466c7852019-12-06 21:42:18 -070013#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060014#include <log.h>
Simon Glass466c7852019-12-06 21:42:18 -070015#include <spi.h>
16#include <spl.h>
17#include <spi_flash.h>
18#include <asm/intel_pinctrl.h>
19#include <dm/uclass-internal.h>
20#include <asm/fsp2/fsp_internal.h>
21
Simon Glassfc557362022-03-04 08:43:05 -070022int fsp_setup_pinctrl(void *ctx, struct event *event)
Simon Glass466c7852019-12-06 21:42:18 -070023{
24 struct udevice *dev;
25 ofnode node;
26 int ret;
27
28 /* Make sure pads are set up early in U-Boot */
Simon Glassd89c4a32020-04-26 09:12:53 -060029 if (!ll_boot_init() || spl_phase() != PHASE_BOARD_F)
Simon Glass466c7852019-12-06 21:42:18 -070030 return 0;
31
32 /* Probe all pinctrl devices to set up the pads */
33 ret = uclass_first_device_err(UCLASS_PINCTRL, &dev);
34 if (ret)
35 return log_msg_ret("no fsp pinctrl", ret);
36 node = ofnode_path("fsp");
37 if (!ofnode_valid(node))
38 return log_msg_ret("no fsp params", -EINVAL);
39 ret = pinctrl_config_pads_for_node(dev, node);
40 if (ret)
41 return log_msg_ret("pad config", ret);
42
43 return ret;
44}
Simon Glassfc557362022-03-04 08:43:05 -070045EVENT_SPY(EVT_DM_POST_INIT, fsp_setup_pinctrl);
Simon Glass466c7852019-12-06 21:42:18 -070046
47#if !defined(CONFIG_TPL_BUILD)
48binman_sym_declare(ulong, intel_fsp_m, image_pos);
49binman_sym_declare(ulong, intel_fsp_m, size);
50
51/**
52 * get_cbfs_fsp() - Obtain the FSP by looking up in CBFS
53 *
54 * This looks up an FSP in a CBFS. It is used mostly for testing, when booting
55 * U-Boot from a hybrid image containing coreboot as the first-stage bootloader.
56 *
57 * The typical use for this feature is when building a Chrome OS image which
58 * includes coreboot in it. By adding U-Boot into the 'COREBOOT' CBFS as well,
59 * it is possible to make coreboot chain-load U-Boot. Thus the initial stages of
60 * the SoC init can be done by coreboot and the later stages by U-Boot. This is
61 * a convenient way to start the porting work. The jump to U-Boot can then be
62 * moved progressively earlier and earlier, until U-Boot takes over all the init
63 * and you have a native port.
64 *
65 * This function looks up a CBFS at a known location and reads the FSP-M from it
66 * so that U-Boot can init the memory.
67 *
68 * This function is not used in the normal boot but is kept here for future
69 * development.
70 *
71 * @type; Type to look up (only FSP_M supported at present)
72 * @map_base: Base memory address for mapped SPI
73 * @entry: Returns an entry containing the position of the FSP image
74 */
75static int get_cbfs_fsp(enum fsp_type_t type, ulong map_base,
76 struct binman_entry *entry)
77{
78 /*
79 * Use a hard-coded position of CBFS in the ROM for now. It would be
80 * possible to read the position using the FMAP in the ROM, but since
81 * this code is only used for development, it doesn't seem worth it.
82 * Use the 'cbfstool <image> layout' command to get these values, e.g.:
83 * 'COREBOOT' (CBFS, size 1814528, offset 2117632).
84 */
85 ulong cbfs_base = 0x205000;
Simon Glass466c7852019-12-06 21:42:18 -070086 struct cbfs_priv *cbfs;
87 int ret;
88
Simon Glass94649092021-03-15 18:00:12 +130089 ret = cbfs_init_mem(map_base + cbfs_base, CBFS_SIZE_UNKNOWN, true,
90 &cbfs);
Simon Glass466c7852019-12-06 21:42:18 -070091 if (ret)
92 return ret;
93 if (!ret) {
94 const struct cbfs_cachenode *node;
95
96 node = cbfs_find_file(cbfs, "fspm.bin");
97 if (!node)
98 return log_msg_ret("fspm node", -ENOENT);
99
100 entry->image_pos = (ulong)node->data;
101 entry->size = node->data_length;
102 }
103
104 return 0;
105}
106
107int fsp_locate_fsp(enum fsp_type_t type, struct binman_entry *entry,
108 bool use_spi_flash, struct udevice **devp,
109 struct fsp_header **hdrp, ulong *rom_offsetp)
110{
111 ulong mask = CONFIG_ROM_SIZE - 1;
112 struct udevice *dev;
113 ulong rom_offset = 0;
114 uint map_size;
115 ulong map_base;
116 uint offset;
117 int ret;
118
119 /*
120 * Find the devices but don't probe them, since we don't want to
121 * auto-config PCI before silicon init runs
122 */
123 ret = uclass_find_first_device(UCLASS_NORTHBRIDGE, &dev);
124 if (ret)
125 return log_msg_ret("Cannot get northbridge", ret);
126 if (!use_spi_flash) {
127 struct udevice *sf;
128
129 /* Just use the SPI driver to get the memory map */
130 ret = uclass_find_first_device(UCLASS_SPI_FLASH, &sf);
131 if (ret)
132 return log_msg_ret("Cannot get SPI flash", ret);
133 ret = dm_spi_get_mmap(sf, &map_base, &map_size, &offset);
134 if (ret)
135 return log_msg_ret("Could not get flash mmap", ret);
136 }
137
138 if (spl_phase() >= PHASE_BOARD_F) {
139 if (type != FSP_S)
140 return -EPROTONOSUPPORT;
141 ret = binman_entry_find("intel-fsp-s", entry);
142 if (ret)
143 return log_msg_ret("binman entry", ret);
144 if (!use_spi_flash)
145 rom_offset = (map_base & mask) - CONFIG_ROM_SIZE;
146 } else {
147 ret = -ENOENT;
148 if (false)
149 /*
150 * Support using a hybrid image build by coreboot. See
151 * the function comments for details
152 */
153 ret = get_cbfs_fsp(type, map_base, entry);
154 if (ret) {
155 ulong mask = CONFIG_ROM_SIZE - 1;
156
157 if (type != FSP_M)
158 return -EPROTONOSUPPORT;
159 entry->image_pos = binman_sym(ulong, intel_fsp_m,
160 image_pos);
161 entry->size = binman_sym(ulong, intel_fsp_m, size);
162 if (entry->image_pos != BINMAN_SYM_MISSING) {
163 ret = 0;
164 if (use_spi_flash)
165 entry->image_pos &= mask;
166 else
167 entry->image_pos += (map_base & mask);
168 } else {
169 ret = -ENOENT;
170 }
171 }
172 }
173 if (ret)
174 return log_msg_ret("Cannot find FSP", ret);
175 entry->image_pos += rom_offset;
176
177 /*
178 * Account for the time taken to read memory-mapped SPI flash since in
179 * this case we don't use the SPI driver and BOOTSTAGE_ID_ACCUM_SPI.
180 */
181 if (!use_spi_flash)
182 bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi");
183 ret = fsp_get_header(entry->image_pos, entry->size, use_spi_flash,
184 hdrp);
185 if (!use_spi_flash)
186 bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI);
187 if (ret)
188 return log_msg_ret("fsp_get_header", ret);
189 *devp = dev;
190 if (rom_offsetp)
191 *rom_offsetp = rom_offset;
192
193 return 0;
194}
195#endif