Simon Glass | 466c785 | 2019-12-06 21:42:18 -0700 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright 2019 Google LLC |
| 4 | */ |
| 5 | |
| 6 | #include <common.h> |
| 7 | #include <binman.h> |
| 8 | #include <binman_sym.h> |
Simon Glass | 1ea9789 | 2020-05-10 11:40:00 -0600 | [diff] [blame] | 9 | #include <bootstage.h> |
Simon Glass | 466c785 | 2019-12-06 21:42:18 -0700 | [diff] [blame] | 10 | #include <cbfs.h> |
| 11 | #include <dm.h> |
| 12 | #include <init.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame^] | 13 | #include <log.h> |
Simon Glass | 466c785 | 2019-12-06 21:42:18 -0700 | [diff] [blame] | 14 | #include <spi.h> |
| 15 | #include <spl.h> |
| 16 | #include <spi_flash.h> |
| 17 | #include <asm/intel_pinctrl.h> |
| 18 | #include <dm/uclass-internal.h> |
| 19 | #include <asm/fsp2/fsp_internal.h> |
| 20 | |
| 21 | int arch_cpu_init_dm(void) |
| 22 | { |
| 23 | struct udevice *dev; |
| 24 | ofnode node; |
| 25 | int ret; |
| 26 | |
| 27 | /* Make sure pads are set up early in U-Boot */ |
Simon Glass | d89c4a3 | 2020-04-26 09:12:53 -0600 | [diff] [blame] | 28 | if (!ll_boot_init() || spl_phase() != PHASE_BOARD_F) |
Simon Glass | 466c785 | 2019-12-06 21:42:18 -0700 | [diff] [blame] | 29 | return 0; |
| 30 | |
| 31 | /* Probe all pinctrl devices to set up the pads */ |
| 32 | ret = uclass_first_device_err(UCLASS_PINCTRL, &dev); |
| 33 | if (ret) |
| 34 | return log_msg_ret("no fsp pinctrl", ret); |
| 35 | node = ofnode_path("fsp"); |
| 36 | if (!ofnode_valid(node)) |
| 37 | return log_msg_ret("no fsp params", -EINVAL); |
| 38 | ret = pinctrl_config_pads_for_node(dev, node); |
| 39 | if (ret) |
| 40 | return log_msg_ret("pad config", ret); |
| 41 | |
| 42 | return ret; |
| 43 | } |
| 44 | |
| 45 | #if !defined(CONFIG_TPL_BUILD) |
| 46 | binman_sym_declare(ulong, intel_fsp_m, image_pos); |
| 47 | binman_sym_declare(ulong, intel_fsp_m, size); |
| 48 | |
| 49 | /** |
| 50 | * get_cbfs_fsp() - Obtain the FSP by looking up in CBFS |
| 51 | * |
| 52 | * This looks up an FSP in a CBFS. It is used mostly for testing, when booting |
| 53 | * U-Boot from a hybrid image containing coreboot as the first-stage bootloader. |
| 54 | * |
| 55 | * The typical use for this feature is when building a Chrome OS image which |
| 56 | * includes coreboot in it. By adding U-Boot into the 'COREBOOT' CBFS as well, |
| 57 | * it is possible to make coreboot chain-load U-Boot. Thus the initial stages of |
| 58 | * the SoC init can be done by coreboot and the later stages by U-Boot. This is |
| 59 | * a convenient way to start the porting work. The jump to U-Boot can then be |
| 60 | * moved progressively earlier and earlier, until U-Boot takes over all the init |
| 61 | * and you have a native port. |
| 62 | * |
| 63 | * This function looks up a CBFS at a known location and reads the FSP-M from it |
| 64 | * so that U-Boot can init the memory. |
| 65 | * |
| 66 | * This function is not used in the normal boot but is kept here for future |
| 67 | * development. |
| 68 | * |
| 69 | * @type; Type to look up (only FSP_M supported at present) |
| 70 | * @map_base: Base memory address for mapped SPI |
| 71 | * @entry: Returns an entry containing the position of the FSP image |
| 72 | */ |
| 73 | static int get_cbfs_fsp(enum fsp_type_t type, ulong map_base, |
| 74 | struct binman_entry *entry) |
| 75 | { |
| 76 | /* |
| 77 | * Use a hard-coded position of CBFS in the ROM for now. It would be |
| 78 | * possible to read the position using the FMAP in the ROM, but since |
| 79 | * this code is only used for development, it doesn't seem worth it. |
| 80 | * Use the 'cbfstool <image> layout' command to get these values, e.g.: |
| 81 | * 'COREBOOT' (CBFS, size 1814528, offset 2117632). |
| 82 | */ |
| 83 | ulong cbfs_base = 0x205000; |
| 84 | ulong cbfs_size = 0x1bb000; |
| 85 | struct cbfs_priv *cbfs; |
| 86 | int ret; |
| 87 | |
| 88 | ret = cbfs_init_mem(map_base + cbfs_base, cbfs_size, &cbfs); |
| 89 | if (ret) |
| 90 | return ret; |
| 91 | if (!ret) { |
| 92 | const struct cbfs_cachenode *node; |
| 93 | |
| 94 | node = cbfs_find_file(cbfs, "fspm.bin"); |
| 95 | if (!node) |
| 96 | return log_msg_ret("fspm node", -ENOENT); |
| 97 | |
| 98 | entry->image_pos = (ulong)node->data; |
| 99 | entry->size = node->data_length; |
| 100 | } |
| 101 | |
| 102 | return 0; |
| 103 | } |
| 104 | |
| 105 | int fsp_locate_fsp(enum fsp_type_t type, struct binman_entry *entry, |
| 106 | bool use_spi_flash, struct udevice **devp, |
| 107 | struct fsp_header **hdrp, ulong *rom_offsetp) |
| 108 | { |
| 109 | ulong mask = CONFIG_ROM_SIZE - 1; |
| 110 | struct udevice *dev; |
| 111 | ulong rom_offset = 0; |
| 112 | uint map_size; |
| 113 | ulong map_base; |
| 114 | uint offset; |
| 115 | int ret; |
| 116 | |
| 117 | /* |
| 118 | * Find the devices but don't probe them, since we don't want to |
| 119 | * auto-config PCI before silicon init runs |
| 120 | */ |
| 121 | ret = uclass_find_first_device(UCLASS_NORTHBRIDGE, &dev); |
| 122 | if (ret) |
| 123 | return log_msg_ret("Cannot get northbridge", ret); |
| 124 | if (!use_spi_flash) { |
| 125 | struct udevice *sf; |
| 126 | |
| 127 | /* Just use the SPI driver to get the memory map */ |
| 128 | ret = uclass_find_first_device(UCLASS_SPI_FLASH, &sf); |
| 129 | if (ret) |
| 130 | return log_msg_ret("Cannot get SPI flash", ret); |
| 131 | ret = dm_spi_get_mmap(sf, &map_base, &map_size, &offset); |
| 132 | if (ret) |
| 133 | return log_msg_ret("Could not get flash mmap", ret); |
| 134 | } |
| 135 | |
| 136 | if (spl_phase() >= PHASE_BOARD_F) { |
| 137 | if (type != FSP_S) |
| 138 | return -EPROTONOSUPPORT; |
| 139 | ret = binman_entry_find("intel-fsp-s", entry); |
| 140 | if (ret) |
| 141 | return log_msg_ret("binman entry", ret); |
| 142 | if (!use_spi_flash) |
| 143 | rom_offset = (map_base & mask) - CONFIG_ROM_SIZE; |
| 144 | } else { |
| 145 | ret = -ENOENT; |
| 146 | if (false) |
| 147 | /* |
| 148 | * Support using a hybrid image build by coreboot. See |
| 149 | * the function comments for details |
| 150 | */ |
| 151 | ret = get_cbfs_fsp(type, map_base, entry); |
| 152 | if (ret) { |
| 153 | ulong mask = CONFIG_ROM_SIZE - 1; |
| 154 | |
| 155 | if (type != FSP_M) |
| 156 | return -EPROTONOSUPPORT; |
| 157 | entry->image_pos = binman_sym(ulong, intel_fsp_m, |
| 158 | image_pos); |
| 159 | entry->size = binman_sym(ulong, intel_fsp_m, size); |
| 160 | if (entry->image_pos != BINMAN_SYM_MISSING) { |
| 161 | ret = 0; |
| 162 | if (use_spi_flash) |
| 163 | entry->image_pos &= mask; |
| 164 | else |
| 165 | entry->image_pos += (map_base & mask); |
| 166 | } else { |
| 167 | ret = -ENOENT; |
| 168 | } |
| 169 | } |
| 170 | } |
| 171 | if (ret) |
| 172 | return log_msg_ret("Cannot find FSP", ret); |
| 173 | entry->image_pos += rom_offset; |
| 174 | |
| 175 | /* |
| 176 | * Account for the time taken to read memory-mapped SPI flash since in |
| 177 | * this case we don't use the SPI driver and BOOTSTAGE_ID_ACCUM_SPI. |
| 178 | */ |
| 179 | if (!use_spi_flash) |
| 180 | bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi"); |
| 181 | ret = fsp_get_header(entry->image_pos, entry->size, use_spi_flash, |
| 182 | hdrp); |
| 183 | if (!use_spi_flash) |
| 184 | bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI); |
| 185 | if (ret) |
| 186 | return log_msg_ret("fsp_get_header", ret); |
| 187 | *devp = dev; |
| 188 | if (rom_offsetp) |
| 189 | *rom_offsetp = rom_offset; |
| 190 | |
| 191 | return 0; |
| 192 | } |
| 193 | #endif |