Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Copyright 2016 Freescale Semiconductor |
Yangbo Lu | bb32e68 | 2021-06-03 10:51:19 +0800 | [diff] [blame] | 4 | * Copyright 2019-2021 NXP |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __LS1046A_COMMON_H |
| 8 | #define __LS1046A_COMMON_H |
| 9 | |
Sumit Garg | c064fc7 | 2017-03-30 09:53:13 +0530 | [diff] [blame] | 10 | /* SPL build */ |
| 11 | #ifdef CONFIG_SPL_BUILD |
| 12 | #define SPL_NO_QBMAN |
| 13 | #define SPL_NO_FMAN |
| 14 | #define SPL_NO_ENV |
| 15 | #define SPL_NO_MISC |
| 16 | #define SPL_NO_QSPI |
| 17 | #define SPL_NO_USB |
| 18 | #define SPL_NO_SATA |
| 19 | #endif |
York Sun | 3e512d8 | 2018-06-26 14:48:29 -0700 | [diff] [blame] | 20 | #if defined(CONFIG_SPL_BUILD) && \ |
| 21 | (defined(CONFIG_NAND_BOOT) || defined(CONFIG_QSPI_BOOT)) |
Sumit Garg | c064fc7 | 2017-03-30 09:53:13 +0530 | [diff] [blame] | 22 | #define SPL_NO_MMC |
| 23 | #endif |
Laurentiu Tudor | ccb2fbf | 2023-08-23 16:25:46 +0300 | [diff] [blame] | 24 | #if defined(CONFIG_SPL_BUILD) |
Sumit Garg | c064fc7 | 2017-03-30 09:53:13 +0530 | [diff] [blame] | 25 | #define SPL_NO_IFC |
| 26 | #endif |
| 27 | |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 28 | #include <asm/arch/config.h> |
Bharat Bhushan | c882dd7 | 2017-03-22 12:06:28 +0530 | [diff] [blame] | 29 | #include <asm/arch/stream_id_lsch2.h> |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 30 | |
| 31 | /* Link Definitions */ |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 32 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 33 | #define CFG_SYS_DDR_SDRAM_BASE 0x80000000 |
Tom Rini | 376b88a | 2022-10-28 20:27:13 -0400 | [diff] [blame] | 34 | #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 35 | #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE |
| 36 | #define CFG_SYS_DDR_BLOCK2_BASE 0x880000000ULL |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 37 | |
Michael Walle | f056e0f | 2020-06-01 21:53:26 +0200 | [diff] [blame] | 38 | #define CPU_RELEASE_ADDR secondary_boot_addr |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 39 | |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 40 | /* Serial Port */ |
Tom Rini | df6a215 | 2022-11-16 13:10:28 -0500 | [diff] [blame] | 41 | #define CFG_SYS_NS16550_CLK (get_serial_clock()) |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 42 | |
Shaohui Xie | 085ac1c | 2016-09-07 17:56:14 +0800 | [diff] [blame] | 43 | /* NAND SPL */ |
| 44 | #ifdef CONFIG_NAND_BOOT |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 45 | #define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE |
| 46 | #define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE |
Shaohui Xie | 085ac1c | 2016-09-07 17:56:14 +0800 | [diff] [blame] | 47 | #endif |
| 48 | |
Biwen Li | 479b9bd | 2021-02-05 19:02:01 +0800 | [diff] [blame] | 49 | /* GPIO */ |
Biwen Li | 479b9bd | 2021-02-05 19:02:01 +0800 | [diff] [blame] | 50 | |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 51 | /* I2C */ |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 52 | |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 53 | /* FMan ucode */ |
Sumit Garg | c064fc7 | 2017-03-30 09:53:13 +0530 | [diff] [blame] | 54 | #ifndef SPL_NO_FMAN |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 55 | #ifdef CONFIG_SYS_DPAA_FMAN |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 56 | #define CFG_SYS_FM_MURAM_SIZE 0x60000 |
Sumit Garg | c064fc7 | 2017-03-30 09:53:13 +0530 | [diff] [blame] | 57 | #endif |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 58 | #endif |
| 59 | |
| 60 | /* Miscellaneous configurable options */ |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 61 | |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 62 | #define HWCONFIG_BUFFER_SIZE 128 |
| 63 | |
Qianyu Gong | 6264ab6 | 2017-06-15 11:10:09 +0800 | [diff] [blame] | 64 | #define BOOT_TARGET_DEVICES(func) \ |
Yuantian Tang | d24716d | 2018-01-03 15:53:09 +0800 | [diff] [blame] | 65 | func(SCSI, scsi, 0) \ |
Qianyu Gong | 6264ab6 | 2017-06-15 11:10:09 +0800 | [diff] [blame] | 66 | func(MMC, mmc, 0) \ |
Mian Yousaf Kaukab | e172158 | 2019-01-29 16:38:37 +0100 | [diff] [blame] | 67 | func(USB, usb, 0) \ |
| 68 | func(DHCP, dhcp, na) |
Qianyu Gong | 6264ab6 | 2017-06-15 11:10:09 +0800 | [diff] [blame] | 69 | #include <config_distro_bootcmd.h> |
Qianyu Gong | 6264ab6 | 2017-06-15 11:10:09 +0800 | [diff] [blame] | 70 | |
Vabhav Sharma | 5164191 | 2019-06-06 12:35:28 +0000 | [diff] [blame] | 71 | #if defined(CONFIG_TARGET_LS1046AFRWY) |
| 72 | #define LS1046A_BOOT_SRC_AND_HDR\ |
| 73 | "boot_scripts=ls1046afrwy_boot.scr\0" \ |
| 74 | "boot_script_hdr=hdr_ls1046afrwy_bs.out\0" |
Biwen Li | 88dd2e8 | 2020-04-20 18:29:06 +0800 | [diff] [blame] | 75 | #elif defined(CONFIG_TARGET_LS1046AQDS) |
| 76 | #define LS1046A_BOOT_SRC_AND_HDR\ |
| 77 | "boot_scripts=ls1046aqds_boot.scr\0" \ |
| 78 | "boot_script_hdr=hdr_ls1046aqds_bs.out\0" |
Vabhav Sharma | 5164191 | 2019-06-06 12:35:28 +0000 | [diff] [blame] | 79 | #else |
| 80 | #define LS1046A_BOOT_SRC_AND_HDR\ |
| 81 | "boot_scripts=ls1046ardb_boot.scr\0" \ |
| 82 | "boot_script_hdr=hdr_ls1046ardb_bs.out\0" |
| 83 | #endif |
Sumit Garg | c064fc7 | 2017-03-30 09:53:13 +0530 | [diff] [blame] | 84 | #ifndef SPL_NO_MISC |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 85 | /* Initial environment variables */ |
Tom Rini | c9edebe | 2022-12-04 10:03:50 -0500 | [diff] [blame] | 86 | #define CFG_EXTRA_ENV_SETTINGS \ |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 87 | "hwconfig=fsl_ddr:bank_intlv=auto\0" \ |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 88 | "ramdisk_addr=0x800000\0" \ |
| 89 | "ramdisk_size=0x2000000\0" \ |
Yuantian Tang | e1786d3 | 2020-02-19 17:02:22 +0800 | [diff] [blame] | 90 | "bootm_size=0x10000000\0" \ |
Biwen Li | 88dd2e8 | 2020-04-20 18:29:06 +0800 | [diff] [blame] | 91 | "kernel_addr=0x61000000\0" \ |
Qianyu Gong | 6264ab6 | 2017-06-15 11:10:09 +0800 | [diff] [blame] | 92 | "scriptaddr=0x80000000\0" \ |
Sumit Garg | 860a3bd | 2017-06-06 20:50:29 +0530 | [diff] [blame] | 93 | "scripthdraddr=0x80080000\0" \ |
Qianyu Gong | 6264ab6 | 2017-06-15 11:10:09 +0800 | [diff] [blame] | 94 | "fdtheader_addr_r=0x80100000\0" \ |
| 95 | "kernelheader_addr_r=0x80200000\0" \ |
| 96 | "load_addr=0xa0000000\0" \ |
Sumit Garg | 860a3bd | 2017-06-06 20:50:29 +0530 | [diff] [blame] | 97 | "kernel_addr_r=0x81000000\0" \ |
Qianyu Gong | 6264ab6 | 2017-06-15 11:10:09 +0800 | [diff] [blame] | 98 | "fdt_addr_r=0x90000000\0" \ |
| 99 | "ramdisk_addr_r=0xa0000000\0" \ |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 100 | "kernel_start=0x1000000\0" \ |
Priyanka Singh | a83b8db | 2020-01-22 10:29:46 +0000 | [diff] [blame] | 101 | "kernelheader_start=0x600000\0" \ |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 102 | "kernel_load=0xa0000000\0" \ |
| 103 | "kernel_size=0x2800000\0" \ |
Vinitha Pillai-B57223 | 0c6e10a | 2017-11-22 10:38:35 +0530 | [diff] [blame] | 104 | "kernelheader_size=0x40000\0" \ |
Shengzhou Liu | 47e7e03 | 2017-11-09 17:57:56 +0800 | [diff] [blame] | 105 | "kernel_addr_sd=0x8000\0" \ |
| 106 | "kernel_size_sd=0x14000\0" \ |
Priyanka Singh | a83b8db | 2020-01-22 10:29:46 +0000 | [diff] [blame] | 107 | "kernelhdr_addr_sd=0x3000\0" \ |
Vinitha Pillai-B57223 | 0c6e10a | 2017-11-22 10:38:35 +0530 | [diff] [blame] | 108 | "kernelhdr_size_sd=0x10\0" \ |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 109 | "console=ttyS0,115200\0" \ |
Tom Rini | 5ad8e11 | 2017-10-22 17:55:07 -0400 | [diff] [blame] | 110 | CONFIG_MTDPARTS_DEFAULT "\0" \ |
Qianyu Gong | 6264ab6 | 2017-06-15 11:10:09 +0800 | [diff] [blame] | 111 | BOOTENV \ |
Vabhav Sharma | 5164191 | 2019-06-06 12:35:28 +0000 | [diff] [blame] | 112 | LS1046A_BOOT_SRC_AND_HDR \ |
Qianyu Gong | 6264ab6 | 2017-06-15 11:10:09 +0800 | [diff] [blame] | 113 | "scan_dev_for_boot_part=" \ |
| 114 | "part list ${devtype} ${devnum} devplist; " \ |
| 115 | "env exists devplist || setenv devplist 1; " \ |
| 116 | "for distro_bootpart in ${devplist}; do " \ |
| 117 | "if fstype ${devtype} " \ |
| 118 | "${devnum}:${distro_bootpart} " \ |
| 119 | "bootfstype; then " \ |
| 120 | "run scan_dev_for_boot; " \ |
| 121 | "fi; " \ |
| 122 | "done\0" \ |
Sumit Garg | 860a3bd | 2017-06-06 20:50:29 +0530 | [diff] [blame] | 123 | "boot_a_script=" \ |
| 124 | "load ${devtype} ${devnum}:${distro_bootpart} " \ |
| 125 | "${scriptaddr} ${prefix}${script}; " \ |
| 126 | "env exists secureboot && load ${devtype} " \ |
| 127 | "${devnum}:${distro_bootpart} " \ |
Vinitha V Pillai | 25355ec | 2019-04-23 05:52:17 +0000 | [diff] [blame] | 128 | "${scripthdraddr} ${prefix}${boot_script_hdr}; " \ |
| 129 | "env exists secureboot " \ |
| 130 | "&& esbc_validate ${scripthdraddr};" \ |
Sumit Garg | 860a3bd | 2017-06-06 20:50:29 +0530 | [diff] [blame] | 131 | "source ${scriptaddr}\0" \ |
Qianyu Gong | 6264ab6 | 2017-06-15 11:10:09 +0800 | [diff] [blame] | 132 | "qspi_bootcmd=echo Trying load from qspi..;" \ |
| 133 | "sf probe && sf read $load_addr " \ |
Vinitha Pillai-B57223 | 0c6e10a | 2017-11-22 10:38:35 +0530 | [diff] [blame] | 134 | "$kernel_start $kernel_size; env exists secureboot " \ |
| 135 | "&& sf read $kernelheader_addr_r $kernelheader_start " \ |
| 136 | "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ |
| 137 | "bootm $load_addr#$board\0" \ |
Biwen Li | 88dd2e8 | 2020-04-20 18:29:06 +0800 | [diff] [blame] | 138 | "nand_bootcmd=echo Trying load from nand..;" \ |
| 139 | "nand info; nand read $load_addr " \ |
| 140 | "$kernel_start $kernel_size; env exists secureboot " \ |
| 141 | "&& nand read $kernelheader_addr_r $kernelheader_start " \ |
| 142 | "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ |
| 143 | "bootm $load_addr#$board\0" \ |
| 144 | "nor_bootcmd=echo Trying load from nor..;" \ |
| 145 | "cp.b $kernel_addr $load_addr " \ |
| 146 | "$kernel_size; env exists secureboot " \ |
| 147 | "&& cp.b $kernelheader_addr $kernelheader_addr_r " \ |
| 148 | "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ |
| 149 | "bootm $load_addr#$board\0" \ |
Shengzhou Liu | 47e7e03 | 2017-11-09 17:57:56 +0800 | [diff] [blame] | 150 | "sd_bootcmd=echo Trying load from SD ..;" \ |
| 151 | "mmcinfo; mmc read $load_addr " \ |
| 152 | "$kernel_addr_sd $kernel_size_sd && " \ |
Vinitha Pillai-B57223 | 0c6e10a | 2017-11-22 10:38:35 +0530 | [diff] [blame] | 153 | "env exists secureboot && mmc read $kernelheader_addr_r " \ |
| 154 | "$kernelhdr_addr_sd $kernelhdr_size_sd " \ |
| 155 | " && esbc_validate ${kernelheader_addr_r};" \ |
Shengzhou Liu | 47e7e03 | 2017-11-09 17:57:56 +0800 | [diff] [blame] | 156 | "bootm $load_addr#$board\0" |
Qianyu Gong | 6264ab6 | 2017-06-15 11:10:09 +0800 | [diff] [blame] | 157 | |
Sumit Garg | c064fc7 | 2017-03-30 09:53:13 +0530 | [diff] [blame] | 158 | #endif |
| 159 | |
Simon Glass | 89e0a3a | 2017-05-17 08:23:10 -0600 | [diff] [blame] | 160 | #include <asm/arch/soc.h> |
| 161 | |
Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 162 | #endif /* __LS1046A_COMMON_H */ |