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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Dinh Nguyen429642c2015-06-02 22:52:48 -05002/*
3 * Copyright Altera Corporation (C) 2014-2015
Dinh Nguyen429642c2015-06-02 22:52:48 -05004 */
5#include <common.h>
Simon Goldschmidt24910c32019-04-16 22:04:39 +02006#include <dm.h>
Marek Vasut1b1cc102015-08-01 22:25:29 +02007#include <errno.h>
Dinh Nguyen429642c2015-06-02 22:52:48 -05008#include <div64.h>
Simon Glass8e16b1e2019-12-28 10:45:05 -07009#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060010#include <log.h>
Simon Goldschmidt24910c32019-04-16 22:04:39 +020011#include <ram.h>
12#include <reset.h>
Dinh Nguyen429642c2015-06-02 22:52:48 -050013#include <watchdog.h>
14#include <asm/arch/fpga_manager.h>
Simon Goldschmidt24910c32019-04-16 22:04:39 +020015#include <asm/arch/reset_manager.h>
Dinh Nguyen429642c2015-06-02 22:52:48 -050016#include <asm/arch/sdram.h>
Dinh Nguyen429642c2015-06-02 22:52:48 -050017#include <asm/arch/system_manager.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060018#include <asm/bitops.h>
Dinh Nguyen429642c2015-06-02 22:52:48 -050019#include <asm/io.h>
Simon Glass9bc15642020-02-03 07:36:16 -070020#include <dm/device_compat.h>
Dinh Nguyen429642c2015-06-02 22:52:48 -050021
Simon Goldschmidt24910c32019-04-16 22:04:39 +020022#include "sequencer.h"
23
24#ifdef CONFIG_SPL_BUILD
25
26struct altera_gen5_sdram_priv {
27 struct ram_info info;
28};
29
30struct altera_gen5_sdram_platdata {
31 struct socfpga_sdr *sdr;
32};
33
Marek Vasute08c5592015-07-26 10:37:54 +020034struct sdram_prot_rule {
Marek Vasut6772cd92015-08-01 23:12:11 +020035 u32 sdram_start; /* SDRAM start address */
36 u32 sdram_end; /* SDRAM end address */
Marek Vasute08c5592015-07-26 10:37:54 +020037 u32 rule; /* SDRAM protection rule number: 0-19 */
38 int valid; /* Rule valid or not? 1 - valid, 0 not*/
39
40 u32 security;
41 u32 portmask;
42 u32 result;
43 u32 lo_prot_id;
44 u32 hi_prot_id;
45};
46
Simon Goldschmidt24910c32019-04-16 22:04:39 +020047static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl);
Dinh Nguyen429642c2015-06-02 22:52:48 -050048
Marek Vasut724c50f2015-08-01 19:20:19 +020049/**
50 * get_errata_rows() - Up the number of DRAM rows to cover entire address space
Marek Vasut3a079112015-08-01 21:16:20 +020051 * @cfg: SDRAM controller configuration data
Marek Vasut724c50f2015-08-01 19:20:19 +020052 *
53 * SDRAM Failure happens when accessing non-existent memory. Artificially
54 * increase the number of rows so that the memory controller thinks it has
55 * 4GB of RAM. This function returns such amount of rows.
56 */
Marek Vasut32ada572015-08-01 21:35:18 +020057static int get_errata_rows(const struct socfpga_sdram_config *cfg)
Dinh Nguyen429642c2015-06-02 22:52:48 -050058{
Marek Vasut724c50f2015-08-01 19:20:19 +020059 /* Define constant for 4G memory - used for SDRAM errata workaround */
60#define MEMSIZE_4G (4ULL * 1024ULL * 1024ULL * 1024ULL)
61 const unsigned long long memsize = MEMSIZE_4G;
Marek Vasut3a079112015-08-01 21:16:20 +020062 const unsigned int cs =
63 ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
64 SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
65 const unsigned int rows =
66 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
67 SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
68 const unsigned int banks =
69 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
70 SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
71 const unsigned int cols =
72 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
73 SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
Marek Vasut724c50f2015-08-01 19:20:19 +020074 const unsigned int width = 8;
75
Dinh Nguyen429642c2015-06-02 22:52:48 -050076 unsigned long long newrows;
Marek Vasut724c50f2015-08-01 19:20:19 +020077 int bits, inewrowslog2;
Dinh Nguyen429642c2015-06-02 22:52:48 -050078
79 debug("workaround rows - memsize %lld\n", memsize);
80 debug("workaround rows - cs %d\n", cs);
81 debug("workaround rows - width %d\n", width);
82 debug("workaround rows - rows %d\n", rows);
83 debug("workaround rows - banks %d\n", banks);
84 debug("workaround rows - cols %d\n", cols);
85
Marek Vasut186880e2015-08-01 18:54:34 +020086 newrows = lldiv(memsize, cs * (width / 8));
Dinh Nguyen429642c2015-06-02 22:52:48 -050087 debug("rows workaround - term1 %lld\n", newrows);
88
Marek Vasut186880e2015-08-01 18:54:34 +020089 newrows = lldiv(newrows, (1 << banks) * (1 << cols));
Dinh Nguyen429642c2015-06-02 22:52:48 -050090 debug("rows workaround - term2 %lld\n", newrows);
91
Marek Vasut186880e2015-08-01 18:54:34 +020092 /*
93 * Compute the hamming weight - same as number of bits set.
Dinh Nguyen429642c2015-06-02 22:52:48 -050094 * Need to see if result is ordinal power of 2 before
95 * attempting log2 of result.
96 */
Marek Vasut2fda5062015-08-01 18:46:55 +020097 bits = generic_hweight32(newrows);
Dinh Nguyen429642c2015-06-02 22:52:48 -050098
99 debug("rows workaround - bits %d\n", bits);
100
101 if (bits != 1) {
102 printf("SDRAM workaround failed, bits set %d\n", bits);
103 return rows;
104 }
105
106 if (newrows > UINT_MAX) {
107 printf("SDRAM workaround rangecheck failed, %lld\n", newrows);
108 return rows;
109 }
110
Marek Vasut186880e2015-08-01 18:54:34 +0200111 inewrowslog2 = __ilog2(newrows);
Dinh Nguyen429642c2015-06-02 22:52:48 -0500112
Marek Vasut186880e2015-08-01 18:54:34 +0200113 debug("rows workaround - ilog2 %d, %lld\n", inewrowslog2, newrows);
Dinh Nguyen429642c2015-06-02 22:52:48 -0500114
115 if (inewrowslog2 == -1) {
Marek Vasut186880e2015-08-01 18:54:34 +0200116 printf("SDRAM workaround failed, newrows %lld\n", newrows);
Dinh Nguyen429642c2015-06-02 22:52:48 -0500117 return rows;
118 }
119
120 return inewrowslog2;
121}
122
123/* SDRAM protection rules vary from 0-19, a total of 20 rules. */
Simon Goldschmidt24910c32019-04-16 22:04:39 +0200124static void sdram_set_rule(struct socfpga_sdr_ctrl *sdr_ctrl,
125 struct sdram_prot_rule *prule)
Dinh Nguyen429642c2015-06-02 22:52:48 -0500126{
Marek Vasut6772cd92015-08-01 23:12:11 +0200127 u32 lo_addr_bits;
128 u32 hi_addr_bits;
Dinh Nguyen429642c2015-06-02 22:52:48 -0500129 int ruleno = prule->rule;
130
131 /* Select the rule */
132 writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
133
134 /* Obtain the address bits */
Marek Vasut7fce5bc2015-08-01 22:40:48 +0200135 lo_addr_bits = prule->sdram_start >> 20ULL;
Marek Vasut12361a22016-04-04 17:52:21 +0200136 hi_addr_bits = (prule->sdram_end - 1) >> 20ULL;
Dinh Nguyen429642c2015-06-02 22:52:48 -0500137
Marek Vasut6772cd92015-08-01 23:12:11 +0200138 debug("sdram set rule start %x, %d\n", lo_addr_bits,
Dinh Nguyen429642c2015-06-02 22:52:48 -0500139 prule->sdram_start);
Marek Vasut6772cd92015-08-01 23:12:11 +0200140 debug("sdram set rule end %x, %d\n", hi_addr_bits,
Dinh Nguyen429642c2015-06-02 22:52:48 -0500141 prule->sdram_end);
142
143 /* Set rule addresses */
144 writel(lo_addr_bits | (hi_addr_bits << 12), &sdr_ctrl->prot_rule_addr);
145
146 /* Set rule protection ids */
147 writel(prule->lo_prot_id | (prule->hi_prot_id << 12),
148 &sdr_ctrl->prot_rule_id);
149
150 /* Set the rule data */
151 writel(prule->security | (prule->valid << 2) |
152 (prule->portmask << 3) | (prule->result << 13),
153 &sdr_ctrl->prot_rule_data);
154
155 /* write the rule */
Marek Vasut7fce5bc2015-08-01 22:40:48 +0200156 writel(ruleno | (1 << 5), &sdr_ctrl->prot_rule_rdwr);
Dinh Nguyen429642c2015-06-02 22:52:48 -0500157
158 /* Set rule number to 0 by default */
159 writel(0, &sdr_ctrl->prot_rule_rdwr);
160}
161
Simon Goldschmidt24910c32019-04-16 22:04:39 +0200162static void sdram_get_rule(struct socfpga_sdr_ctrl *sdr_ctrl,
163 struct sdram_prot_rule *prule)
Dinh Nguyen429642c2015-06-02 22:52:48 -0500164{
Marek Vasut91144072015-08-01 23:21:23 +0200165 u32 addr;
166 u32 id;
167 u32 data;
Dinh Nguyen429642c2015-06-02 22:52:48 -0500168 int ruleno = prule->rule;
169
170 /* Read the rule */
171 writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
Marek Vasut91144072015-08-01 23:21:23 +0200172 writel(ruleno | (1 << 6), &sdr_ctrl->prot_rule_rdwr);
Dinh Nguyen429642c2015-06-02 22:52:48 -0500173
174 /* Get the addresses */
175 addr = readl(&sdr_ctrl->prot_rule_addr);
176 prule->sdram_start = (addr & 0xFFF) << 20;
177 prule->sdram_end = ((addr >> 12) & 0xFFF) << 20;
178
179 /* Get the configured protection IDs */
180 id = readl(&sdr_ctrl->prot_rule_id);
181 prule->lo_prot_id = id & 0xFFF;
182 prule->hi_prot_id = (id >> 12) & 0xFFF;
183
184 /* Get protection data */
185 data = readl(&sdr_ctrl->prot_rule_data);
186
187 prule->security = data & 0x3;
188 prule->valid = (data >> 2) & 0x1;
189 prule->portmask = (data >> 3) & 0x3FF;
190 prule->result = (data >> 13) & 0x1;
191}
192
Marek Vasut6772cd92015-08-01 23:12:11 +0200193static void
Simon Goldschmidt24910c32019-04-16 22:04:39 +0200194sdram_set_protection_config(struct socfpga_sdr_ctrl *sdr_ctrl,
195 const u32 sdram_start, const u32 sdram_end)
Dinh Nguyen429642c2015-06-02 22:52:48 -0500196{
197 struct sdram_prot_rule rule;
198 int rules;
199
200 /* Start with accepting all SDRAM transaction */
201 writel(0x0, &sdr_ctrl->protport_default);
202
203 /* Clear all protection rules for warm boot case */
Marek Vasut7fce5bc2015-08-01 22:40:48 +0200204 memset(&rule, 0, sizeof(rule));
Dinh Nguyen429642c2015-06-02 22:52:48 -0500205
206 for (rules = 0; rules < 20; rules++) {
207 rule.rule = rules;
Simon Goldschmidt24910c32019-04-16 22:04:39 +0200208 sdram_set_rule(sdr_ctrl, &rule);
Dinh Nguyen429642c2015-06-02 22:52:48 -0500209 }
210
211 /* new rule: accept SDRAM */
212 rule.sdram_start = sdram_start;
213 rule.sdram_end = sdram_end;
214 rule.lo_prot_id = 0x0;
215 rule.hi_prot_id = 0xFFF;
216 rule.portmask = 0x3FF;
217 rule.security = 0x3;
218 rule.result = 0;
219 rule.valid = 1;
220 rule.rule = 0;
221
222 /* set new rule */
Simon Goldschmidt24910c32019-04-16 22:04:39 +0200223 sdram_set_rule(sdr_ctrl, &rule);
Dinh Nguyen429642c2015-06-02 22:52:48 -0500224
225 /* default rule: reject everything */
226 writel(0x3ff, &sdr_ctrl->protport_default);
227}
228
Simon Goldschmidt24910c32019-04-16 22:04:39 +0200229static void sdram_dump_protection_config(struct socfpga_sdr_ctrl *sdr_ctrl)
Dinh Nguyen429642c2015-06-02 22:52:48 -0500230{
231 struct sdram_prot_rule rule;
232 int rules;
233
234 debug("SDRAM Prot rule, default %x\n",
235 readl(&sdr_ctrl->protport_default));
236
237 for (rules = 0; rules < 20; rules++) {
Marek Vasut42aa46d2015-12-29 09:38:52 +0100238 rule.rule = rules;
Simon Goldschmidt24910c32019-04-16 22:04:39 +0200239 sdram_get_rule(sdr_ctrl, &rule);
Dinh Nguyen429642c2015-06-02 22:52:48 -0500240 debug("Rule %d, rules ...\n", rules);
Marek Vasut6772cd92015-08-01 23:12:11 +0200241 debug(" sdram start %x\n", rule.sdram_start);
242 debug(" sdram end %x\n", rule.sdram_end);
Dinh Nguyen429642c2015-06-02 22:52:48 -0500243 debug(" low prot id %d, hi prot id %d\n",
244 rule.lo_prot_id,
245 rule.hi_prot_id);
246 debug(" portmask %x\n", rule.portmask);
247 debug(" security %d\n", rule.security);
248 debug(" result %d\n", rule.result);
249 debug(" valid %d\n", rule.valid);
250 }
251}
252
Marek Vasut116d88f2015-08-01 22:26:11 +0200253/**
254 * sdram_write_verify() - write to register and verify the write.
255 * @addr: Register address
256 * @val: Value to be written and verified
257 *
258 * This function writes to a register, reads back the value and compares
259 * the result with the written value to check if the data match.
260 */
261static unsigned sdram_write_verify(const u32 *addr, const u32 val)
Dinh Nguyen429642c2015-06-02 22:52:48 -0500262{
Marek Vasut116d88f2015-08-01 22:26:11 +0200263 u32 rval;
264
265 debug(" Write - Address 0x%p Data 0x%08x\n", addr, val);
266 writel(val, addr);
267
Dinh Nguyen429642c2015-06-02 22:52:48 -0500268 debug(" Read and verify...");
Marek Vasut116d88f2015-08-01 22:26:11 +0200269 rval = readl(addr);
270 if (rval != val) {
271 debug("FAIL - Address 0x%p Expected 0x%08x Data 0x%08x\n",
272 addr, val, rval);
273 return -EINVAL;
Dinh Nguyen429642c2015-06-02 22:52:48 -0500274 }
Marek Vasut116d88f2015-08-01 22:26:11 +0200275
Dinh Nguyen429642c2015-06-02 22:52:48 -0500276 debug("correct!\n");
Dinh Nguyen429642c2015-06-02 22:52:48 -0500277 return 0;
278}
279
Marek Vasutb0d848c2015-08-01 22:28:30 +0200280/**
281 * sdr_get_ctrlcfg() - Get the value of DRAM CTRLCFG register
282 * @cfg: SDRAM controller configuration data
283 *
284 * Return the value of DRAM CTRLCFG register.
285 */
Marek Vasut32ada572015-08-01 21:35:18 +0200286static u32 sdr_get_ctrlcfg(const struct socfpga_sdram_config *cfg)
Dinh Nguyen429642c2015-06-02 22:52:48 -0500287{
Marek Vasut3a079112015-08-01 21:16:20 +0200288 const u32 csbits =
289 ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
290 SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
291 u32 addrorder =
292 (cfg->ctrl_cfg & SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK) >>
293 SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
294
Marek Vasut4f3adbf2015-08-01 20:30:10 +0200295 u32 ctrl_cfg = cfg->ctrl_cfg;
Dinh Nguyen429642c2015-06-02 22:52:48 -0500296
Marek Vasut82a27642015-08-01 19:33:40 +0200297 /*
298 * SDRAM Failure When Accessing Non-Existent Memory
Dinh Nguyen429642c2015-06-02 22:52:48 -0500299 * Set the addrorder field of the SDRAM control register
300 * based on the CSBITs setting.
301 */
Marek Vasut3a079112015-08-01 21:16:20 +0200302 if (csbits == 1) {
303 if (addrorder != 0)
Marek Vasut82a27642015-08-01 19:33:40 +0200304 debug("INFO: Changing address order to 0 (chip, row, bank, column)\n");
Marek Vasut3a079112015-08-01 21:16:20 +0200305 addrorder = 0;
306 } else if (csbits == 2) {
307 if (addrorder != 2)
Marek Vasut82a27642015-08-01 19:33:40 +0200308 debug("INFO: Changing address order to 2 (row, chip, bank, column)\n");
Marek Vasut3a079112015-08-01 21:16:20 +0200309 addrorder = 2;
Dinh Nguyen429642c2015-06-02 22:52:48 -0500310 }
311
Marek Vasut3a079112015-08-01 21:16:20 +0200312 ctrl_cfg &= ~SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK;
Marek Vasut82a27642015-08-01 19:33:40 +0200313 ctrl_cfg |= addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
Dinh Nguyen429642c2015-06-02 22:52:48 -0500314
Marek Vasut1e271e42015-08-01 21:24:31 +0200315 return ctrl_cfg;
Dinh Nguyen429642c2015-06-02 22:52:48 -0500316}
317
Marek Vasutb0d848c2015-08-01 22:28:30 +0200318/**
319 * sdr_get_addr_rw() - Get the value of DRAM ADDRW register
320 * @cfg: SDRAM controller configuration data
321 *
322 * Return the value of DRAM ADDRW register.
323 */
Marek Vasut32ada572015-08-01 21:35:18 +0200324static u32 sdr_get_addr_rw(const struct socfpga_sdram_config *cfg)
Dinh Nguyen429642c2015-06-02 22:52:48 -0500325{
Dinh Nguyen429642c2015-06-02 22:52:48 -0500326 /*
327 * SDRAM Failure When Accessing Non-Existent Memory
Dinh Nguyen429642c2015-06-02 22:52:48 -0500328 * Set SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB to
329 * log2(number of chip select bits). Since there's only
330 * 1 or 2 chip selects, log2(1) => 0, and log2(2) => 1,
331 * which is the same as "chip selects" - 1.
332 */
Marek Vasut3a079112015-08-01 21:16:20 +0200333 const int rows = get_errata_rows(cfg);
334 u32 dram_addrw = cfg->dram_addrw & ~SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK;
Marek Vasut4f3adbf2015-08-01 20:30:10 +0200335
Marek Vasut1e271e42015-08-01 21:24:31 +0200336 return dram_addrw | (rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB);
Dinh Nguyen429642c2015-06-02 22:52:48 -0500337}
338
Marek Vasutb81f11c2015-08-01 21:26:55 +0200339/**
340 * sdr_load_regs() - Load SDRAM controller registers
341 * @cfg: SDRAM controller configuration data
342 *
343 * This function loads the register values into the SDRAM controller block.
344 */
Simon Goldschmidt24910c32019-04-16 22:04:39 +0200345static void sdr_load_regs(struct socfpga_sdr_ctrl *sdr_ctrl,
346 const struct socfpga_sdram_config *cfg)
Dinh Nguyen429642c2015-06-02 22:52:48 -0500347{
Marek Vasut1e271e42015-08-01 21:24:31 +0200348 const u32 ctrl_cfg = sdr_get_ctrlcfg(cfg);
349 const u32 dram_addrw = sdr_get_addr_rw(cfg);
350
Marek Vasut1e271e42015-08-01 21:24:31 +0200351 debug("\nConfiguring CTRLCFG\n");
352 writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);
Marek Vasut71c1a002015-08-01 21:21:21 +0200353
354 debug("Configuring DRAMTIMING1\n");
355 writel(cfg->dram_timing1, &sdr_ctrl->dram_timing1);
356
357 debug("Configuring DRAMTIMING2\n");
358 writel(cfg->dram_timing2, &sdr_ctrl->dram_timing2);
359
360 debug("Configuring DRAMTIMING3\n");
361 writel(cfg->dram_timing3, &sdr_ctrl->dram_timing3);
362
363 debug("Configuring DRAMTIMING4\n");
364 writel(cfg->dram_timing4, &sdr_ctrl->dram_timing4);
365
366 debug("Configuring LOWPWRTIMING\n");
367 writel(cfg->lowpwr_timing, &sdr_ctrl->lowpwr_timing);
368
Marek Vasut1e271e42015-08-01 21:24:31 +0200369 debug("Configuring DRAMADDRW\n");
370 writel(dram_addrw, &sdr_ctrl->dram_addrw);
Dinh Nguyen429642c2015-06-02 22:52:48 -0500371
372 debug("Configuring DRAMIFWIDTH\n");
Marek Vasut7697ff72015-08-01 20:58:44 +0200373 writel(cfg->dram_if_width, &sdr_ctrl->dram_if_width);
Dinh Nguyen429642c2015-06-02 22:52:48 -0500374
375 debug("Configuring DRAMDEVWIDTH\n");
Marek Vasut7697ff72015-08-01 20:58:44 +0200376 writel(cfg->dram_dev_width, &sdr_ctrl->dram_dev_width);
Dinh Nguyen429642c2015-06-02 22:52:48 -0500377
378 debug("Configuring LOWPWREQ\n");
Marek Vasut7697ff72015-08-01 20:58:44 +0200379 writel(cfg->lowpwr_eq, &sdr_ctrl->lowpwr_eq);
Dinh Nguyen429642c2015-06-02 22:52:48 -0500380
381 debug("Configuring DRAMINTR\n");
Marek Vasut7697ff72015-08-01 20:58:44 +0200382 writel(cfg->dram_intr, &sdr_ctrl->dram_intr);
Dinh Nguyen429642c2015-06-02 22:52:48 -0500383
Marek Vasut71c1a002015-08-01 21:21:21 +0200384 debug("Configuring STATICCFG\n");
385 writel(cfg->static_cfg, &sdr_ctrl->static_cfg);
Dinh Nguyen429642c2015-06-02 22:52:48 -0500386
387 debug("Configuring CTRLWIDTH\n");
Marek Vasut7697ff72015-08-01 20:58:44 +0200388 writel(cfg->ctrl_width, &sdr_ctrl->ctrl_width);
Dinh Nguyen429642c2015-06-02 22:52:48 -0500389
390 debug("Configuring PORTCFG\n");
Marek Vasut7697ff72015-08-01 20:58:44 +0200391 writel(cfg->port_cfg, &sdr_ctrl->port_cfg);
Dinh Nguyen429642c2015-06-02 22:52:48 -0500392
Marek Vasut71c1a002015-08-01 21:21:21 +0200393 debug("Configuring FIFOCFG\n");
394 writel(cfg->fifo_cfg, &sdr_ctrl->fifo_cfg);
Dinh Nguyen429642c2015-06-02 22:52:48 -0500395
396 debug("Configuring MPPRIORITY\n");
Marek Vasut7697ff72015-08-01 20:58:44 +0200397 writel(cfg->mp_priority, &sdr_ctrl->mp_priority);
Dinh Nguyen429642c2015-06-02 22:52:48 -0500398
Marek Vasut71c1a002015-08-01 21:21:21 +0200399 debug("Configuring MPWEIGHT_MPWEIGHT_0\n");
400 writel(cfg->mp_weight0, &sdr_ctrl->mp_weight0);
401 writel(cfg->mp_weight1, &sdr_ctrl->mp_weight1);
402 writel(cfg->mp_weight2, &sdr_ctrl->mp_weight2);
403 writel(cfg->mp_weight3, &sdr_ctrl->mp_weight3);
404
405 debug("Configuring MPPACING_MPPACING_0\n");
406 writel(cfg->mp_pacing0, &sdr_ctrl->mp_pacing0);
407 writel(cfg->mp_pacing1, &sdr_ctrl->mp_pacing1);
408 writel(cfg->mp_pacing2, &sdr_ctrl->mp_pacing2);
409 writel(cfg->mp_pacing3, &sdr_ctrl->mp_pacing3);
410
411 debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n");
412 writel(cfg->mp_threshold0, &sdr_ctrl->mp_threshold0);
413 writel(cfg->mp_threshold1, &sdr_ctrl->mp_threshold1);
414 writel(cfg->mp_threshold2, &sdr_ctrl->mp_threshold2);
Dinh Nguyen429642c2015-06-02 22:52:48 -0500415
416 debug("Configuring PHYCTRL_PHYCTRL_0\n");
Marek Vasut7697ff72015-08-01 20:58:44 +0200417 writel(cfg->phy_ctrl0, &sdr_ctrl->phy_ctrl0);
Dinh Nguyen429642c2015-06-02 22:52:48 -0500418
419 debug("Configuring CPORTWIDTH\n");
Marek Vasut7697ff72015-08-01 20:58:44 +0200420 writel(cfg->cport_width, &sdr_ctrl->cport_width);
Dinh Nguyen429642c2015-06-02 22:52:48 -0500421
422 debug("Configuring CPORTWMAP\n");
Marek Vasut7697ff72015-08-01 20:58:44 +0200423 writel(cfg->cport_wmap, &sdr_ctrl->cport_wmap);
Dinh Nguyen429642c2015-06-02 22:52:48 -0500424
425 debug("Configuring CPORTRMAP\n");
Marek Vasut7697ff72015-08-01 20:58:44 +0200426 writel(cfg->cport_rmap, &sdr_ctrl->cport_rmap);
Dinh Nguyen429642c2015-06-02 22:52:48 -0500427
428 debug("Configuring RFIFOCMAP\n");
Marek Vasut7697ff72015-08-01 20:58:44 +0200429 writel(cfg->rfifo_cmap, &sdr_ctrl->rfifo_cmap);
Dinh Nguyen429642c2015-06-02 22:52:48 -0500430
431 debug("Configuring WFIFOCMAP\n");
Marek Vasut7697ff72015-08-01 20:58:44 +0200432 writel(cfg->wfifo_cmap, &sdr_ctrl->wfifo_cmap);
Dinh Nguyen429642c2015-06-02 22:52:48 -0500433
434 debug("Configuring CPORTRDWR\n");
Marek Vasut7697ff72015-08-01 20:58:44 +0200435 writel(cfg->cport_rdwr, &sdr_ctrl->cport_rdwr);
Dinh Nguyen429642c2015-06-02 22:52:48 -0500436
437 debug("Configuring DRAMODT\n");
Marek Vasut7697ff72015-08-01 20:58:44 +0200438 writel(cfg->dram_odt, &sdr_ctrl->dram_odt);
Chin Liang See3ea59512016-09-21 10:25:56 +0800439
Marek Vasut6bccacf2019-10-18 00:22:31 +0200440 if (dram_is_ddr(3)) {
441 debug("Configuring EXTRATIME1\n");
442 writel(cfg->extratime1, &sdr_ctrl->extratime1);
443 }
Marek Vasutb81f11c2015-08-01 21:26:55 +0200444}
445
Marek Vasut5a4e8ed2015-08-01 22:03:48 +0200446/**
447 * sdram_mmr_init_full() - Function to initialize SDRAM MMR
448 * @sdr_phy_reg: Value of the PHY control register 0
449 *
450 * Initialize the SDRAM MMR.
451 */
Simon Goldschmidt24910c32019-04-16 22:04:39 +0200452int sdram_mmr_init_full(struct socfpga_sdr_ctrl *sdr_ctrl,
453 unsigned int sdr_phy_reg)
Marek Vasutb81f11c2015-08-01 21:26:55 +0200454{
Marek Vasut32ada572015-08-01 21:35:18 +0200455 const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
Marek Vasutb81f11c2015-08-01 21:26:55 +0200456 const unsigned int rows =
457 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
458 SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
Marek Vasut116d88f2015-08-01 22:26:11 +0200459 int ret;
Marek Vasutb81f11c2015-08-01 21:26:55 +0200460
Ley Foon Tan3d3a8602019-11-08 10:38:20 +0800461 writel(rows,
462 socfpga_get_sysmgr_addr() + SYSMGR_ISWGRP_HANDOFF_OFFSET(4));
Marek Vasutb81f11c2015-08-01 21:26:55 +0200463
Simon Goldschmidt24910c32019-04-16 22:04:39 +0200464 sdr_load_regs(sdr_ctrl, cfg);
Dinh Nguyen429642c2015-06-02 22:52:48 -0500465
466 /* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */
Ley Foon Tan3d3a8602019-11-08 10:38:20 +0800467 writel(cfg->fpgaport_rst,
468 socfpga_get_sysmgr_addr() + SYSMGR_ISWGRP_HANDOFF_OFFSET(3));
Dinh Nguyen429642c2015-06-02 22:52:48 -0500469
470 /* only enable if the FPGA is programmed */
471 if (fpgamgr_test_fpga_ready()) {
Marek Vasut116d88f2015-08-01 22:26:11 +0200472 ret = sdram_write_verify(&sdr_ctrl->fpgaport_rst,
473 cfg->fpgaport_rst);
474 if (ret)
475 return ret;
Dinh Nguyen429642c2015-06-02 22:52:48 -0500476 }
477
478 /* Restore the SDR PHY Register if valid */
479 if (sdr_phy_reg != 0xffffffff)
480 writel(sdr_phy_reg, &sdr_ctrl->phy_ctrl0);
481
Marek Vasut7697ff72015-08-01 20:58:44 +0200482 /* Final step - apply configuration changes */
483 debug("Configuring STATICCFG\n");
484 clrsetbits_le32(&sdr_ctrl->static_cfg,
485 SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK,
Dinh Nguyen429642c2015-06-02 22:52:48 -0500486 1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB);
Dinh Nguyen429642c2015-06-02 22:52:48 -0500487
Simon Goldschmidt24910c32019-04-16 22:04:39 +0200488 sdram_set_protection_config(sdr_ctrl, 0,
489 sdram_calculate_size(sdr_ctrl) - 1);
Dinh Nguyen429642c2015-06-02 22:52:48 -0500490
Simon Goldschmidt24910c32019-04-16 22:04:39 +0200491 sdram_dump_protection_config(sdr_ctrl);
Dinh Nguyen429642c2015-06-02 22:52:48 -0500492
Marek Vasut116d88f2015-08-01 22:26:11 +0200493 return 0;
Dinh Nguyen429642c2015-06-02 22:52:48 -0500494}
495
Marek Vasut1796a092015-08-01 21:47:16 +0200496/**
497 * sdram_calculate_size() - Calculate SDRAM size
Dinh Nguyen429642c2015-06-02 22:52:48 -0500498 *
Marek Vasut1796a092015-08-01 21:47:16 +0200499 * Calculate SDRAM device size based on SDRAM controller parameters.
500 * Size is specified in bytes.
Dinh Nguyen429642c2015-06-02 22:52:48 -0500501 */
Simon Goldschmidt24910c32019-04-16 22:04:39 +0200502static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl)
Dinh Nguyen429642c2015-06-02 22:52:48 -0500503{
504 unsigned long temp;
505 unsigned long row, bank, col, cs, width;
Marek Vasut6d6fbba2015-08-01 21:44:00 +0200506 const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
507 const unsigned int csbits =
508 ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
509 SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
510 const unsigned int rowbits =
511 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
512 SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
Dinh Nguyen429642c2015-06-02 22:52:48 -0500513
514 temp = readl(&sdr_ctrl->dram_addrw);
515 col = (temp & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
516 SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
517
Marek Vasut1796a092015-08-01 21:47:16 +0200518 /*
519 * SDRAM Failure When Accessing Non-Existent Memory
Dinh Nguyen429642c2015-06-02 22:52:48 -0500520 * Use ROWBITS from Quartus/QSys to calculate SDRAM size
521 * since the FB specifies we modify ROWBITs to work around SDRAM
522 * controller issue.
Dinh Nguyen429642c2015-06-02 22:52:48 -0500523 */
Ley Foon Tan3d3a8602019-11-08 10:38:20 +0800524 row = readl(socfpga_get_sysmgr_addr() +
525 SYSMGR_ISWGRP_HANDOFF_OFFSET(4));
Dinh Nguyen429642c2015-06-02 22:52:48 -0500526 if (row == 0)
Marek Vasut6d6fbba2015-08-01 21:44:00 +0200527 row = rowbits;
Marek Vasut1796a092015-08-01 21:47:16 +0200528 /*
529 * If the stored handoff value for rows is greater than
Dinh Nguyen429642c2015-06-02 22:52:48 -0500530 * the field width in the sdr.dramaddrw register then
531 * something is very wrong. Revert to using the the #define
532 * value handed off by the SOCEDS tool chain instead of
533 * using a broken value.
534 */
535 if (row > 31)
Marek Vasut6d6fbba2015-08-01 21:44:00 +0200536 row = rowbits;
Dinh Nguyen429642c2015-06-02 22:52:48 -0500537
538 bank = (temp & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
539 SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
540
Marek Vasut1796a092015-08-01 21:47:16 +0200541 /*
542 * SDRAM Failure When Accessing Non-Existent Memory
Dinh Nguyen429642c2015-06-02 22:52:48 -0500543 * Use CSBITs from Quartus/QSys to calculate SDRAM size
544 * since the FB specifies we modify CSBITs to work around SDRAM
545 * controller issue.
546 */
Marek Vasut6d6fbba2015-08-01 21:44:00 +0200547 cs = csbits;
Dinh Nguyen429642c2015-06-02 22:52:48 -0500548
549 width = readl(&sdr_ctrl->dram_if_width);
Marek Vasut1796a092015-08-01 21:47:16 +0200550
Dinh Nguyen429642c2015-06-02 22:52:48 -0500551 /* ECC would not be calculated as its not addressible */
552 if (width == SDRAM_WIDTH_32BIT_WITH_ECC)
553 width = 32;
554 if (width == SDRAM_WIDTH_16BIT_WITH_ECC)
555 width = 16;
556
557 /* calculate the SDRAM size base on this info */
558 temp = 1 << (row + bank + col);
559 temp = temp * cs * (width / 8);
560
Marek Vasut1796a092015-08-01 21:47:16 +0200561 debug("%s returns %ld\n", __func__, temp);
Dinh Nguyen429642c2015-06-02 22:52:48 -0500562
563 return temp;
564}
Simon Goldschmidt24910c32019-04-16 22:04:39 +0200565
566static int altera_gen5_sdram_ofdata_to_platdata(struct udevice *dev)
567{
Simon Glass71fa5b42020-12-03 16:55:18 -0700568 struct altera_gen5_sdram_platdata *plat = dev->plat;
Simon Goldschmidt24910c32019-04-16 22:04:39 +0200569
570 plat->sdr = (struct socfpga_sdr *)devfdt_get_addr_index(dev, 0);
571 if (!plat->sdr)
572 return -ENODEV;
573
574 return 0;
575}
576
577static int altera_gen5_sdram_probe(struct udevice *dev)
578{
579 int ret;
580 unsigned long sdram_size;
Simon Glass71fa5b42020-12-03 16:55:18 -0700581 struct altera_gen5_sdram_platdata *plat = dev->plat;
Simon Goldschmidt24910c32019-04-16 22:04:39 +0200582 struct altera_gen5_sdram_priv *priv = dev_get_priv(dev);
583 struct socfpga_sdr_ctrl *sdr_ctrl = &plat->sdr->sdr_ctrl;
584 struct reset_ctl_bulk resets;
585
586 ret = reset_get_bulk(dev, &resets);
587 if (ret) {
588 dev_err(dev, "Can't get reset: %d\n", ret);
589 return -ENODEV;
590 }
591 reset_deassert_bulk(&resets);
592
593 if (sdram_mmr_init_full(sdr_ctrl, 0xffffffff) != 0) {
594 puts("SDRAM init failed.\n");
595 goto failed;
596 }
597
598 debug("SDRAM: Calibrating PHY\n");
599 /* SDRAM calibration */
600 if (sdram_calibration_full(plat->sdr) == 0) {
601 puts("SDRAM calibration failed.\n");
602 goto failed;
603 }
604
605 sdram_size = sdram_calculate_size(sdr_ctrl);
606 debug("SDRAM: %ld MiB\n", sdram_size >> 20);
607
608 /* Sanity check ensure correct SDRAM size specified */
609 if (get_ram_size(0, sdram_size) != sdram_size) {
610 puts("SDRAM size check failed!\n");
611 goto failed;
612 }
613
614 priv->info.base = 0;
615 priv->info.size = sdram_size;
616
617 return 0;
618
619failed:
620 reset_release_bulk(&resets);
621 return -ENODEV;
622}
623
624static int altera_gen5_sdram_get_info(struct udevice *dev,
625 struct ram_info *info)
626{
627 struct altera_gen5_sdram_priv *priv = dev_get_priv(dev);
628
629 info->base = priv->info.base;
630 info->size = priv->info.size;
631
632 return 0;
633}
634
Simon Goldschmidte8744332019-10-23 22:19:37 +0200635static const struct ram_ops altera_gen5_sdram_ops = {
Simon Goldschmidt24910c32019-04-16 22:04:39 +0200636 .get_info = altera_gen5_sdram_get_info,
637};
638
639static const struct udevice_id altera_gen5_sdram_ids[] = {
640 { .compatible = "altr,sdr-ctl" },
641 { /* sentinel */ }
642};
643
644U_BOOT_DRIVER(altera_gen5_sdram) = {
645 .name = "altr_sdr_ctl",
646 .id = UCLASS_RAM,
647 .of_match = altera_gen5_sdram_ids,
648 .ops = &altera_gen5_sdram_ops,
649 .ofdata_to_platdata = altera_gen5_sdram_ofdata_to_platdata,
Simon Glass71fa5b42020-12-03 16:55:18 -0700650 .plat_auto = sizeof(struct altera_gen5_sdram_platdata),
Simon Goldschmidt24910c32019-04-16 22:04:39 +0200651 .probe = altera_gen5_sdram_probe,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700652 .priv_auto = sizeof(struct altera_gen5_sdram_priv),
Simon Goldschmidt24910c32019-04-16 22:04:39 +0200653};
654
655#endif /* CONFIG_SPL_BUILD */