stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2001-2004 |
| 3 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
| 4 | * |
Wolfgang Denk | bd8ec7e | 2013-10-07 13:07:26 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | /* |
| 9 | * board/config.h - configuration options, board specific |
| 10 | */ |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 11 | #ifndef __CONFIG_H |
| 12 | #define __CONFIG_H |
| 13 | |
| 14 | /* |
| 15 | * High Level Configuration Options |
| 16 | * (easy to change) |
| 17 | */ |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 18 | #define CONFIG_405EP 1 /* This is a PPC405 CPU */ |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 19 | #define CONFIG_VOM405 1 /* ...on a VOM405 board */ |
| 20 | |
Wolfgang Denk | 291ba1b | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 21 | #define CONFIG_SYS_TEXT_BASE 0xFFFC8000 |
Matthias Fuchs | 6e4b1c8 | 2015-01-12 22:47:35 +0100 | [diff] [blame] | 22 | #define CONFIG_DISPLAY_BOARDINFO |
Wolfgang Denk | 291ba1b | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 23 | |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 24 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ |
| 25 | #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ |
| 26 | |
| 27 | #define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ |
| 28 | |
| 29 | #define CONFIG_BAUDRATE 9600 |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 30 | |
| 31 | #undef CONFIG_BOOTARGS |
| 32 | #undef CONFIG_BOOTCOMMAND |
| 33 | |
| 34 | #define CONFIG_PREBOOT /* enable preboot variable */ |
| 35 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 36 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 37 | |
Stefan Roese | f230327 | 2005-11-15 10:35:59 +0100 | [diff] [blame] | 38 | #undef CONFIG_HAS_ETH1 |
| 39 | |
Ben Warren | 3a918a6 | 2008-10-27 23:50:15 -0700 | [diff] [blame] | 40 | #define CONFIG_PPC4xx_EMAC |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 41 | #define CONFIG_MII 1 /* MII PHY management */ |
| 42 | #define CONFIG_PHY_ADDR 0 /* PHY address */ |
| 43 | #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ |
Stefan Roese | f230327 | 2005-11-15 10:35:59 +0100 | [diff] [blame] | 44 | #define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 45 | |
Jon Loeliger | 530ca67 | 2007-07-09 21:38:02 -0500 | [diff] [blame] | 46 | /* |
| 47 | * BOOTP options |
| 48 | */ |
| 49 | #define CONFIG_BOOTP_SUBNETMASK |
| 50 | #define CONFIG_BOOTP_GATEWAY |
| 51 | #define CONFIG_BOOTP_HOSTNAME |
| 52 | #define CONFIG_BOOTP_BOOTPATH |
| 53 | #define CONFIG_BOOTP_DNS |
| 54 | #define CONFIG_BOOTP_DNS2 |
| 55 | #define CONFIG_BOOTP_SEND_HOSTNAME |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 56 | |
Jon Loeliger | 2161619 | 2007-07-08 15:31:57 -0500 | [diff] [blame] | 57 | /* |
| 58 | * Command line configuration. |
| 59 | */ |
Jon Loeliger | 2161619 | 2007-07-08 15:31:57 -0500 | [diff] [blame] | 60 | #define CONFIG_CMD_BSP |
Jon Loeliger | 2161619 | 2007-07-08 15:31:57 -0500 | [diff] [blame] | 61 | #define CONFIG_CMD_IRQ |
Jon Loeliger | 2161619 | 2007-07-08 15:31:57 -0500 | [diff] [blame] | 62 | #define CONFIG_CMD_EEPROM |
| 63 | |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 64 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 65 | |
| 66 | #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ |
| 67 | |
| 68 | #undef CONFIG_PRAM /* no "protected RAM" */ |
| 69 | |
| 70 | /* |
| 71 | * Miscellaneous configurable options |
| 72 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 73 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 74 | |
Jon Loeliger | 2161619 | 2007-07-08 15:31:57 -0500 | [diff] [blame] | 75 | #if defined(CONFIG_CMD_KGDB) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 76 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 77 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 78 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 79 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 80 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 81 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 82 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 83 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 84 | #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 85 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 86 | #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 87 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 88 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
| 89 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 90 | |
Stefan Roese | 3ddce57 | 2010-09-20 16:05:31 +0200 | [diff] [blame] | 91 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
Stefan Roese | 3ddce57 | 2010-09-20 16:05:31 +0200 | [diff] [blame] | 92 | #define CONFIG_SYS_NS16550_SERIAL |
| 93 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| 94 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() |
| 95 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 96 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 97 | #define CONFIG_SYS_BASE_BAUD 691200 |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 98 | |
| 99 | /* The following table includes the supported baudrates */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 100 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 101 | { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ |
| 102 | 57600, 115200, 230400, 460800, 921600 } |
| 103 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 104 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
| 105 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 106 | |
Matthias Fuchs | e7772cf | 2008-09-02 15:07:54 +0200 | [diff] [blame] | 107 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 108 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 109 | #define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 110 | |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 111 | /* |
| 112 | * For booting Linux, the board info and command line data |
| 113 | * have to be in the first 8 MB of memory, since this is |
| 114 | * the maximum mapped by the Linux kernel during initialization. |
| 115 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 116 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
Matthias Fuchs | e7772cf | 2008-09-02 15:07:54 +0200 | [diff] [blame] | 117 | /* |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 118 | * FLASH organization |
| 119 | */ |
| 120 | #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ |
| 121 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 122 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
| 123 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 124 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 125 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
| 126 | #define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 127 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 128 | #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ |
| 129 | #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ |
| 130 | #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 131 | /* |
| 132 | * The following defines are added for buggy IOP480 byte interface. |
| 133 | * All other boards should use the standard values (CPCI405 etc.) |
| 134 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 135 | #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ |
| 136 | #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ |
| 137 | #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 138 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 139 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 140 | |
Matthias Fuchs | e7772cf | 2008-09-02 15:07:54 +0200 | [diff] [blame] | 141 | /* |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 142 | * Start addresses for the final memory configuration |
| 143 | * (Set up by the startup code) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 144 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 145 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 146 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
Matthias Fuchs | 3256ccc | 2009-04-29 09:50:59 +0200 | [diff] [blame] | 147 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE |
Wolfgang Denk | 0708bc6 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 148 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
| 149 | #define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1) |
Matthias Fuchs | 3256ccc | 2009-04-29 09:50:59 +0200 | [diff] [blame] | 150 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 151 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 152 | #if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM) |
| 153 | # define CONFIG_SYS_RAMBOOT 1 |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 154 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 155 | # undef CONFIG_SYS_RAMBOOT |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 156 | #endif |
| 157 | |
Matthias Fuchs | e7772cf | 2008-09-02 15:07:54 +0200 | [diff] [blame] | 158 | /* |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 159 | * Environment Variable setup |
| 160 | */ |
Jean-Christophe PLAGNIOL-VILLARD | e46af64 | 2008-09-05 09:19:30 +0200 | [diff] [blame] | 161 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 162 | #define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ |
| 163 | #define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 164 | /* total size of a CAT24WC16 is 2048 bytes */ |
| 165 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 166 | #define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ |
| 167 | #define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */ |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 168 | |
Matthias Fuchs | e7772cf | 2008-09-02 15:07:54 +0200 | [diff] [blame] | 169 | /* |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 170 | * I2C EEPROM (CAT24WC16) for environment |
| 171 | */ |
Dirk Eibach | 42b204f | 2013-04-25 02:40:01 +0000 | [diff] [blame] | 172 | #define CONFIG_SYS_I2C |
| 173 | #define CONFIG_SYS_I2C_PPC4XX |
| 174 | #define CONFIG_SYS_I2C_PPC4XX_CH0 |
| 175 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 |
| 176 | #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 177 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 178 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ |
| 179 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 180 | /* mask of address bits that overflow into the "EEPROM chip address" */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 181 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
| 182 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 183 | /* 16 byte page write mode using*/ |
| 184 | /* last 4 bits of the address */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 185 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 186 | |
Matthias Fuchs | e7772cf | 2008-09-02 15:07:54 +0200 | [diff] [blame] | 187 | /* |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 188 | * External Bus Controller (EBC) Setup |
| 189 | */ |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 190 | #define CAN_BA 0xF0000000 /* CAN Base Address */ |
| 191 | |
| 192 | /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 193 | #define CONFIG_SYS_EBC_PB0AP 0x92015480 |
| 194 | #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 195 | |
| 196 | /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 197 | #define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
| 198 | #define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 199 | |
Matthias Fuchs | e7772cf | 2008-09-02 15:07:54 +0200 | [diff] [blame] | 200 | /* |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 201 | * FPGA stuff |
| 202 | */ |
Matthias Fuchs | 3256ccc | 2009-04-29 09:50:59 +0200 | [diff] [blame] | 203 | #define CONFIG_SYS_XSVF_DEFAULT_ADDR 0xfffc0000 |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 204 | |
| 205 | /* FPGA program pin configuration */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 206 | #define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */ |
| 207 | #define CONFIG_SYS_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */ |
| 208 | #define CONFIG_SYS_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */ |
| 209 | #define CONFIG_SYS_FPGA_INIT 0x00010000 /* unused (ppc input) */ |
| 210 | #define CONFIG_SYS_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */ |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 211 | |
Matthias Fuchs | e7772cf | 2008-09-02 15:07:54 +0200 | [diff] [blame] | 212 | /* |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 213 | * Definitions for initial stack pointer and data area (in data cache) |
| 214 | */ |
| 215 | /* use on chip memory ( OCM ) for temperary stack until sdram is tested */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 216 | #define CONFIG_SYS_TEMP_STACK_OCM 1 |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 217 | |
| 218 | /* On Chip Memory location */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 219 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 |
| 220 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 |
| 221 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 222 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 223 | |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 224 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 225 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 226 | |
Matthias Fuchs | e7772cf | 2008-09-02 15:07:54 +0200 | [diff] [blame] | 227 | /* |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 228 | * Definitions for GPIO setup (PPC405EP specific) |
| 229 | * |
| 230 | * GPIO0[0] - External Bus Controller BLAST output |
| 231 | * GPIO0[1-9] - Instruction trace outputs -> GPIO |
| 232 | * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs |
| 233 | * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO |
| 234 | * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs |
| 235 | * GPIO0[24-27] - UART0 control signal inputs/outputs |
| 236 | * GPIO0[28-29] - UART1 data signal input/output |
| 237 | * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs |
| 238 | */ |
| 239 | /* GPIO Input: OSR=00, ISR=00, TSR=00, TCR=0 */ |
| 240 | /* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */ |
| 241 | /* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */ |
| 242 | /* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */ |
Stefan Roese | 8cb251a | 2010-09-12 06:21:37 +0200 | [diff] [blame] | 243 | #define CONFIG_SYS_GPIO0_OSRL 0x40000500 /* 0 ... 15 */ |
| 244 | #define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* 16 ... 31 */ |
| 245 | #define CONFIG_SYS_GPIO0_ISR1L 0x00000000 /* 0 ... 15 */ |
| 246 | #define CONFIG_SYS_GPIO0_ISR1H 0x14000045 /* 16 ... 31 */ |
| 247 | #define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 0 ... 15 */ |
| 248 | #define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 16 ... 31 */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 249 | #define CONFIG_SYS_GPIO0_TCR 0xF7FE0014 /* 0 ... 31 */ |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 250 | |
| 251 | /* |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 252 | * Default speed selection (cpu_plb_opb_ebc) in mhz. |
| 253 | * This value will be set if iic boot eprom is disabled. |
| 254 | */ |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 255 | #define PLLMR0_DEFAULT PLLMR0_133_66_66_33 |
| 256 | #define PLLMR1_DEFAULT PLLMR1_133_66_66_33 |
stroese | a9484a9 | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 257 | |
| 258 | #endif /* __CONFIG_H */ |