Bin Meng | 2229c4c | 2015-05-07 21:34:08 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | /dts-v1/; |
| 8 | |
Bin Meng | ef37e7b | 2015-06-03 09:20:06 +0800 | [diff] [blame] | 9 | #include <dt-bindings/interrupt-router/intel-irq.h> |
| 10 | |
| 11 | /* ICH9 IRQ router has discrete PIRQ control registers */ |
| 12 | #undef PIRQE |
| 13 | #undef PIRQF |
| 14 | #undef PIRQG |
| 15 | #undef PIRQH |
| 16 | #define PIRQE 8 |
| 17 | #define PIRQF 9 |
| 18 | #define PIRQG 10 |
| 19 | #define PIRQH 11 |
| 20 | |
Bin Meng | 2229c4c | 2015-05-07 21:34:08 +0800 | [diff] [blame] | 21 | /include/ "skeleton.dtsi" |
| 22 | /include/ "serial.dtsi" |
Bin Meng | 7ca7374 | 2015-11-12 05:33:06 -0800 | [diff] [blame] | 23 | /include/ "keyboard.dtsi" |
Bin Meng | 770fd33 | 2015-07-15 16:23:39 +0800 | [diff] [blame] | 24 | /include/ "rtc.dtsi" |
Bin Meng | 38de020 | 2015-11-13 00:11:22 -0800 | [diff] [blame] | 25 | /include/ "tsc_timer.dtsi" |
Bin Meng | 2229c4c | 2015-05-07 21:34:08 +0800 | [diff] [blame] | 26 | |
| 27 | / { |
Bin Meng | 000883b | 2015-06-03 09:20:04 +0800 | [diff] [blame] | 28 | model = "QEMU x86 (Q35)"; |
Bin Meng | 2229c4c | 2015-05-07 21:34:08 +0800 | [diff] [blame] | 29 | compatible = "qemu,x86"; |
| 30 | |
| 31 | config { |
| 32 | silent_console = <0>; |
Bin Meng | 70be096 | 2015-06-03 09:20:05 +0800 | [diff] [blame] | 33 | u-boot,no-apm-finalize; |
Bin Meng | 2229c4c | 2015-05-07 21:34:08 +0800 | [diff] [blame] | 34 | }; |
| 35 | |
| 36 | chosen { |
| 37 | stdout-path = "/serial"; |
| 38 | }; |
| 39 | |
Bin Meng | 354dcdd | 2015-07-22 01:21:13 -0700 | [diff] [blame] | 40 | cpus { |
| 41 | #address-cells = <1>; |
| 42 | #size-cells = <0>; |
| 43 | |
| 44 | cpu@0 { |
| 45 | device_type = "cpu"; |
Miao Yan | 4336af6 | 2016-01-07 01:32:01 -0800 | [diff] [blame] | 46 | compatible = "cpu-qemu"; |
Bin Meng | 354dcdd | 2015-07-22 01:21:13 -0700 | [diff] [blame] | 47 | reg = <0>; |
| 48 | intel,apic-id = <0>; |
| 49 | }; |
| 50 | }; |
| 51 | |
Bin Meng | 38de020 | 2015-11-13 00:11:22 -0800 | [diff] [blame] | 52 | tsc-timer { |
| 53 | clock-frequency = <1000000000>; |
| 54 | }; |
| 55 | |
Bin Meng | 2229c4c | 2015-05-07 21:34:08 +0800 | [diff] [blame] | 56 | pci { |
| 57 | compatible = "pci-x86"; |
| 58 | #address-cells = <3>; |
| 59 | #size-cells = <2>; |
| 60 | u-boot,dm-pre-reloc; |
| 61 | ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000 |
| 62 | 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000 |
| 63 | 0x01000000 0x0 0x2000 0x2000 0 0xe000>; |
Bin Meng | ef37e7b | 2015-06-03 09:20:06 +0800 | [diff] [blame] | 64 | |
Simon Glass | 3276163 | 2016-01-18 20:19:21 -0700 | [diff] [blame] | 65 | pch@1f,0 { |
Bin Meng | ef37e7b | 2015-06-03 09:20:06 +0800 | [diff] [blame] | 66 | reg = <0x0000f800 0 0 0 0>; |
Simon Glass | 3276163 | 2016-01-18 20:19:21 -0700 | [diff] [blame] | 67 | compatible = "intel,pch9"; |
| 68 | |
| 69 | irq-router { |
| 70 | compatible = "intel,irq-router"; |
| 71 | intel,pirq-config = "pci"; |
Bin Meng | 0651f62 | 2016-05-07 07:46:15 -0700 | [diff] [blame] | 72 | intel,actl-8bit; |
| 73 | intel,actl-addr = <0x44>; |
Simon Glass | 3276163 | 2016-01-18 20:19:21 -0700 | [diff] [blame] | 74 | intel,pirq-link = <0x60 8>; |
| 75 | intel,pirq-mask = <0x0e40>; |
| 76 | intel,pirq-routing = < |
| 77 | /* e1000 NIC */ |
| 78 | PCI_BDF(0, 2, 0) INTA PIRQG |
| 79 | /* ICH9 UHCI */ |
| 80 | PCI_BDF(0, 29, 0) INTA PIRQA |
| 81 | PCI_BDF(0, 29, 1) INTB PIRQB |
| 82 | PCI_BDF(0, 29, 2) INTC PIRQC |
| 83 | /* ICH9 EHCI */ |
| 84 | PCI_BDF(0, 29, 7) INTD PIRQD |
| 85 | /* ICH9 SATA */ |
| 86 | PCI_BDF(0, 31, 2) INTA PIRQA |
| 87 | >; |
| 88 | }; |
Bin Meng | ef37e7b | 2015-06-03 09:20:06 +0800 | [diff] [blame] | 89 | }; |
Bin Meng | 2229c4c | 2015-05-07 21:34:08 +0800 | [diff] [blame] | 90 | }; |
| 91 | |
| 92 | }; |