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Bin Meng2229c4c2015-05-07 21:34:08 +08001/*
2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7/dts-v1/;
8
Bin Mengef37e7b2015-06-03 09:20:06 +08009#include <dt-bindings/interrupt-router/intel-irq.h>
10
11/* ICH9 IRQ router has discrete PIRQ control registers */
12#undef PIRQE
13#undef PIRQF
14#undef PIRQG
15#undef PIRQH
16#define PIRQE 8
17#define PIRQF 9
18#define PIRQG 10
19#define PIRQH 11
20
Bin Meng2229c4c2015-05-07 21:34:08 +080021/include/ "skeleton.dtsi"
22/include/ "serial.dtsi"
Bin Meng7ca73742015-11-12 05:33:06 -080023/include/ "keyboard.dtsi"
Bin Meng770fd332015-07-15 16:23:39 +080024/include/ "rtc.dtsi"
Bin Meng2229c4c2015-05-07 21:34:08 +080025
26/ {
Bin Meng000883b2015-06-03 09:20:04 +080027 model = "QEMU x86 (Q35)";
Bin Meng2229c4c2015-05-07 21:34:08 +080028 compatible = "qemu,x86";
29
30 config {
31 silent_console = <0>;
Bin Meng70be0962015-06-03 09:20:05 +080032 u-boot,no-apm-finalize;
Bin Meng2229c4c2015-05-07 21:34:08 +080033 };
34
35 chosen {
36 stdout-path = "/serial";
37 };
38
Bin Meng354dcdd2015-07-22 01:21:13 -070039 cpus {
40 #address-cells = <1>;
41 #size-cells = <0>;
42
43 cpu@0 {
44 device_type = "cpu";
45 compatible = "cpu-x86";
46 reg = <0>;
47 intel,apic-id = <0>;
48 };
Bin Meng6647f572015-07-27 19:16:08 +080049
50 cpu@1 {
51 device_type = "cpu";
52 compatible = "cpu-x86";
53 reg = <1>;
54 intel,apic-id = <1>;
55 };
Bin Meng354dcdd2015-07-22 01:21:13 -070056 };
57
Bin Meng2229c4c2015-05-07 21:34:08 +080058 pci {
59 compatible = "pci-x86";
60 #address-cells = <3>;
61 #size-cells = <2>;
62 u-boot,dm-pre-reloc;
63 ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
64 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
65 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
Bin Mengef37e7b2015-06-03 09:20:06 +080066
67 irq-router@1f,0 {
68 reg = <0x0000f800 0 0 0 0>;
69 compatible = "intel,irq-router";
70 intel,pirq-config = "pci";
71 intel,pirq-link = <0x60 8>;
72 intel,pirq-mask = <0x0e40>;
73 intel,pirq-routing = <
74 /* e1000 NIC */
75 PCI_BDF(0, 2, 0) INTA PIRQG
76 /* ICH9 UHCI */
77 PCI_BDF(0, 29, 0) INTA PIRQA
78 PCI_BDF(0, 29, 1) INTB PIRQB
79 PCI_BDF(0, 29, 2) INTC PIRQC
80 /* ICH9 EHCI */
81 PCI_BDF(0, 29, 7) INTD PIRQD
82 /* ICH9 SATA */
83 PCI_BDF(0, 31, 2) INTA PIRQA
84 >;
85 };
Bin Meng2229c4c2015-05-07 21:34:08 +080086 };
87
88};