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Chin Liang Seecca9f452013-12-30 18:26:14 -06001/*
2 * (C) Copyright 2013 Altera Corporation <www.altera.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <malloc.h>
Marek Vasut17497232015-07-25 10:48:14 +02009#include <fdtdec.h>
10#include <libfdt.h>
Chin Liang Seecca9f452013-12-30 18:26:14 -060011#include <dwmmc.h>
Pavel Machek51d21132014-09-08 14:08:45 +020012#include <errno.h>
Chin Liang Seecca9f452013-12-30 18:26:14 -060013#include <asm/arch/dwmmc.h>
14#include <asm/arch/clock_manager.h>
15#include <asm/arch/system_manager.h>
16
17static const struct socfpga_clock_manager *clock_manager_base =
18 (void *)SOCFPGA_CLKMGR_ADDRESS;
19static const struct socfpga_system_manager *system_manager_base =
20 (void *)SOCFPGA_SYSMGR_ADDRESS;
21
Chin Liang See48e7bf92015-11-26 09:43:43 +080022/* socfpga implmentation specific drver private data */
23struct dwmci_socfpga_priv_data {
Chin Liang Seecca9f452013-12-30 18:26:14 -060024 unsigned int drvsel;
25 unsigned int smplsel;
Chin Liang See48e7bf92015-11-26 09:43:43 +080026};
27
28static void socfpga_dwmci_clksel(struct dwmci_host *host)
29{
30 struct dwmci_socfpga_priv_data *priv = host->priv;
Chin Liang Seecca9f452013-12-30 18:26:14 -060031
32 /* Disable SDMMC clock. */
Pavel Machek91c2f8f2014-07-19 23:57:59 +020033 clrbits_le32(&clock_manager_base->per_pll.en,
Chin Liang Seecca9f452013-12-30 18:26:14 -060034 CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
35
Chin Liang See48e7bf92015-11-26 09:43:43 +080036 debug("%s: drvsel %d smplsel %d\n", __func__,
37 priv->drvsel, priv->smplsel);
38 writel(SYSMGR_SDMMC_CTRL_SET(priv->smplsel, priv->drvsel),
Chin Liang Seecca9f452013-12-30 18:26:14 -060039 &system_manager_base->sdmmcgrp_ctrl);
40
41 debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
42 readl(&system_manager_base->sdmmcgrp_ctrl));
43
44 /* Enable SDMMC clock */
Pavel Machek91c2f8f2014-07-19 23:57:59 +020045 setbits_le32(&clock_manager_base->per_pll.en,
Chin Liang Seecca9f452013-12-30 18:26:14 -060046 CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
47}
48
Marek Vasut17497232015-07-25 10:48:14 +020049static int socfpga_dwmci_of_probe(const void *blob, int node, const int idx)
Chin Liang Seecca9f452013-12-30 18:26:14 -060050{
Marek Vasut17497232015-07-25 10:48:14 +020051 /* FIXME: probe from DT eventually too/ */
52 const unsigned long clk = cm_get_mmc_controller_clk_hz();
53
Pavel Machek1d45a442014-07-21 13:30:19 +020054 struct dwmci_host *host;
Chin Liang See48e7bf92015-11-26 09:43:43 +080055 struct dwmci_socfpga_priv_data *priv;
Marek Vasut17497232015-07-25 10:48:14 +020056 fdt_addr_t reg_base;
57 int bus_width, fifo_depth;
Pavel Machek51d21132014-09-08 14:08:45 +020058
59 if (clk == 0) {
Marek Vasut17497232015-07-25 10:48:14 +020060 printf("DWMMC%d: MMC clock is zero!", idx);
Pavel Machek51d21132014-09-08 14:08:45 +020061 return -EINVAL;
62 }
Pavel Machek1d45a442014-07-21 13:30:19 +020063
Marek Vasut17497232015-07-25 10:48:14 +020064 /* Get the register address from the device node */
65 reg_base = fdtdec_get_addr(blob, node, "reg");
66 if (!reg_base) {
67 printf("DWMMC%d: Can't get base address\n", idx);
68 return -EINVAL;
Chin Liang Seecca9f452013-12-30 18:26:14 -060069 }
70
Marek Vasut17497232015-07-25 10:48:14 +020071 /* Get the bus width from the device node */
72 bus_width = fdtdec_get_int(blob, node, "bus-width", 0);
73 if (bus_width <= 0) {
74 printf("DWMMC%d: Can't get bus-width\n", idx);
75 return -EINVAL;
76 }
77
78 fifo_depth = fdtdec_get_int(blob, node, "fifo-depth", 0);
79 if (fifo_depth < 0) {
80 printf("DWMMC%d: Can't get FIFO depth\n", idx);
81 return -EINVAL;
82 }
83
84 /* Allocate the host */
85 host = calloc(1, sizeof(*host));
86 if (!host)
87 return -ENOMEM;
Chin Liang See48e7bf92015-11-26 09:43:43 +080088
89 /* Allocate the priv */
90 priv = calloc(1, sizeof(*priv));
91 if (!priv) {
92 free(host);
93 return -ENOMEM;
94 }
Marek Vasut17497232015-07-25 10:48:14 +020095
Pavel Machek1d45a442014-07-21 13:30:19 +020096 host->name = "SOCFPGA DWMMC";
Marek Vasut17497232015-07-25 10:48:14 +020097 host->ioaddr = (void *)reg_base;
Chin Liang Seecca9f452013-12-30 18:26:14 -060098 host->buswidth = bus_width;
99 host->clksel = socfpga_dwmci_clksel;
Marek Vasut17497232015-07-25 10:48:14 +0200100 host->dev_index = idx;
101 /* Fixed clock divide by 4 which due to the SDMMC wrapper */
Pavel Machek51d21132014-09-08 14:08:45 +0200102 host->bus_hz = clk;
Chin Liang Seecca9f452013-12-30 18:26:14 -0600103 host->fifoth_val = MSIZE(0x2) |
Marek Vasut17497232015-07-25 10:48:14 +0200104 RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
Chin Liang See48e7bf92015-11-26 09:43:43 +0800105 priv->drvsel = fdtdec_get_uint(blob, node, "drvsel", 3);
106 priv->smplsel = fdtdec_get_uint(blob, node, "smplsel", 0);
107 host->priv = priv;
Chin Liang Seecca9f452013-12-30 18:26:14 -0600108
109 return add_dwmci(host, host->bus_hz, 400000);
110}
111
Marek Vasut17497232015-07-25 10:48:14 +0200112static int socfpga_dwmci_process_node(const void *blob, int nodes[],
113 int count)
114{
115 int i, node, ret;
116
117 for (i = 0; i < count; i++) {
118 node = nodes[i];
119 if (node <= 0)
120 continue;
121
122 ret = socfpga_dwmci_of_probe(blob, node, i);
123 if (ret) {
124 printf("%s: failed to decode dev %d\n", __func__, i);
125 return ret;
126 }
127 }
128 return 0;
129}
130
131int socfpga_dwmmc_init(const void *blob)
132{
133 int nodes[2]; /* Max. two controllers. */
134 int ret, count;
135
136 count = fdtdec_find_aliases_for_id(blob, "mmc",
137 COMPAT_ALTERA_SOCFPGA_DWMMC,
138 nodes, ARRAY_SIZE(nodes));
139
140 ret = socfpga_dwmci_process_node(blob, nodes, count);
141
142 return ret;
143}