socfpga: fix clock manager register definition
Structure defining clock manager hardware was wrong, leading to
wrong registers being accessed and hang in MMC init.
This fixes structure to match hardware.
Signed-off-by: Pavel Machek <pavel@denx.de>
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index bc53a5d..417ca4c 100644
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -24,7 +24,7 @@
unsigned int smplsel;
/* Disable SDMMC clock. */
- clrbits_le32(&clock_manager_base->per_pll_en,
+ clrbits_le32(&clock_manager_base->per_pll.en,
CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
/* Configures drv_sel and smpl_sel */
@@ -39,7 +39,7 @@
readl(&system_manager_base->sdmmcgrp_ctrl));
/* Enable SDMMC clock */
- setbits_le32(&clock_manager_base->per_pll_en,
+ setbits_le32(&clock_manager_base->per_pll.en,
CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
}