blob: 7ececf37ccc02193ba2566f2cdba830958e56a22 [file] [log] [blame]
Alex Marginean0daa53a2019-06-03 19:12:28 +03001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2019
4 * Alex Marginean, NXP
5 */
6
Alex Marginean0daa53a2019-06-03 19:12:28 +03007#include <dm.h>
Simon Glass0f2af882020-05-10 11:40:05 -06008#include <log.h>
Simon Glass75c4d412020-07-19 10:15:37 -06009#include <miiphy.h>
Alex Marginean0daa53a2019-06-03 19:12:28 +030010#include <misc.h>
Simon Glass75c4d412020-07-19 10:15:37 -060011#include <dm/test.h>
12#include <test/test.h>
Alex Marginean0daa53a2019-06-03 19:12:28 +030013#include <test/ut.h>
Alex Marginean0daa53a2019-06-03 19:12:28 +030014
15/* macros copied over from mdio_sandbox.c */
16#define SANDBOX_PHY_ADDR 5
Alex Marginean3336ef62019-07-12 10:13:52 +030017#define SANDBOX_PHY_REG_CNT 2
18
19/* test using 1st register, 0 */
Alex Marginean0daa53a2019-06-03 19:12:28 +030020#define SANDBOX_PHY_REG 0
21
22#define TEST_REG_VALUE 0xabcd
23
24static int dm_test_mdio(struct unit_test_state *uts)
25{
26 struct uclass *uc;
27 struct udevice *dev;
28 struct mdio_ops *ops;
29 u16 reg;
30
31 ut_assertok(uclass_get(UCLASS_MDIO, &uc));
32
33 ut_assertok(uclass_get_device_by_name(UCLASS_MDIO, "mdio-test", &dev));
34
35 ops = mdio_get_ops(dev);
36 ut_assertnonnull(ops);
37 ut_assertnonnull(ops->read);
38 ut_assertnonnull(ops->write);
39
Marek Behúne4dedf22022-04-07 00:32:59 +020040 ut_assertok(dm_mdio_write(dev, SANDBOX_PHY_ADDR, MDIO_DEVAD_NONE,
41 SANDBOX_PHY_REG, TEST_REG_VALUE));
42 reg = dm_mdio_read(dev, SANDBOX_PHY_ADDR, MDIO_DEVAD_NONE,
43 SANDBOX_PHY_REG);
Alex Marginean0daa53a2019-06-03 19:12:28 +030044 ut_asserteq(reg, TEST_REG_VALUE);
45
Marek Behúne4dedf22022-04-07 00:32:59 +020046 ut_assert(dm_mdio_read(dev, SANDBOX_PHY_ADDR + 1, MDIO_DEVAD_NONE,
47 SANDBOX_PHY_REG) != 0);
Alex Marginean0daa53a2019-06-03 19:12:28 +030048
Marek Behúne4dedf22022-04-07 00:32:59 +020049 ut_assertok(dm_mdio_reset(dev));
50 reg = dm_mdio_read(dev, SANDBOX_PHY_ADDR, MDIO_DEVAD_NONE,
51 SANDBOX_PHY_REG);
Alex Marginean0daa53a2019-06-03 19:12:28 +030052 ut_asserteq(reg, 0);
53
54 return 0;
55}
56
Simon Glass974dccd2020-07-28 19:41:12 -060057DM_TEST(dm_test_mdio, UT_TESTF_SCAN_FDT);