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git01.mediatek.com / filogic / uboot / f94b26109b51f02fcd5930cfbbc24a865e6e4e81 / . / dts / upstream / Bindings / phy / qcom,sc8280xp-qmp-ufs-phy.yaml
blob: 91a6cc38ff7ff5d8df2fd33997b540e4338e9ab2 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-ufs-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm QMP PHY controller (UFS, SC8280XP)
8
9maintainers:
10 - Vinod Koul <vkoul@kernel.org>
11
12description:
13 The QMP PHY controller supports physical layer functionality for a number of
14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
15
16properties:
17 compatible:
18 enum:
19 - qcom,msm8996-qmp-ufs-phy
20 - qcom,msm8998-qmp-ufs-phy
21 - qcom,sa8775p-qmp-ufs-phy
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]22 - qcom,sc7180-qmp-ufs-phy
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]23 - qcom,sc7280-qmp-ufs-phy
24 - qcom,sc8180x-qmp-ufs-phy
25 - qcom,sc8280xp-qmp-ufs-phy
26 - qcom,sdm845-qmp-ufs-phy
27 - qcom,sm6115-qmp-ufs-phy
28 - qcom,sm6125-qmp-ufs-phy
29 - qcom,sm6350-qmp-ufs-phy
30 - qcom,sm7150-qmp-ufs-phy
31 - qcom,sm8150-qmp-ufs-phy
32 - qcom,sm8250-qmp-ufs-phy
33 - qcom,sm8350-qmp-ufs-phy
34 - qcom,sm8450-qmp-ufs-phy
35 - qcom,sm8550-qmp-ufs-phy
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]36 - qcom,sm8650-qmp-ufs-phy
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]37
38 reg:
39 maxItems: 1
40
41 clocks:
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]42 minItems: 2
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]43 maxItems: 3
44
45 clock-names:
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]46 minItems: 2
47 maxItems: 3
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]48
49 power-domains:
50 maxItems: 1
51
52 resets:
53 maxItems: 1
54
55 reset-names:
56 items:
57 - const: ufsphy
58
59 vdda-phy-supply: true
60
61 vdda-pll-supply: true
62
63 "#clock-cells":
64 const: 1
65
66 "#phy-cells":
67 const: 0
68
69required:
70 - compatible
71 - reg
72 - clocks
73 - clock-names
74 - power-domains
75 - resets
76 - reset-names
77 - vdda-phy-supply
78 - vdda-pll-supply
79 - "#phy-cells"
80
81allOf:
82 - if:
83 properties:
84 compatible:
85 contains:
86 enum:
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]87 - qcom,msm8998-qmp-ufs-phy
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]88 - qcom,sa8775p-qmp-ufs-phy
89 - qcom,sc7280-qmp-ufs-phy
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]90 - qcom,sc8180x-qmp-ufs-phy
91 - qcom,sc8280xp-qmp-ufs-phy
92 - qcom,sdm845-qmp-ufs-phy
93 - qcom,sm6115-qmp-ufs-phy
94 - qcom,sm6125-qmp-ufs-phy
95 - qcom,sm6350-qmp-ufs-phy
96 - qcom,sm7150-qmp-ufs-phy
97 - qcom,sm8150-qmp-ufs-phy
98 - qcom,sm8250-qmp-ufs-phy
99 - qcom,sm8350-qmp-ufs-phy
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]100 - qcom,sm8450-qmp-ufs-phy
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]101 - qcom,sm8550-qmp-ufs-phy
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]102 - qcom,sm8650-qmp-ufs-phy
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]103 then:
104 properties:
105 clocks:
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]106 minItems: 3
107 maxItems: 3
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]108 clock-names:
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]109 items:
110 - const: ref
111 - const: ref_aux
112 - const: qref
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]113
114 - if:
115 properties:
116 compatible:
117 contains:
118 enum:
119 - qcom,msm8996-qmp-ufs-phy
120 then:
121 properties:
122 clocks:
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]123 minItems: 2
124 maxItems: 2
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]125 clock-names:
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]126 items:
127 - const: ref
128 - const: qref
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]129
130additionalProperties: false
131
132examples:
133 - |
134 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]135 #include <dt-bindings/clock/qcom,rpmh.h>
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]136
137 ufs_mem_phy: phy@1d87000 {
138 compatible = "qcom,sc8280xp-qmp-ufs-phy";
139 reg = <0x01d87000 0x1000>;
140
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]141 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
142 <&gcc GCC_UFS_REF_CLKREF_CLK>;
143
144 clock-names = "ref", "ref_aux", "qref";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]145
146 power-domains = <&gcc UFS_PHY_GDSC>;
147
148 resets = <&ufs_mem_hc 0>;
149 reset-names = "ufsphy";
150
151 vdda-phy-supply = <&vreg_l6b>;
152 vdda-pll-supply = <&vreg_l3b>;
153
154 #phy-cells = <0>;
155 };