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git01.mediatek.com / filogic / uboot / 53633a893a06bd5a0c807287d9cc29337806eaf7 / . / Bindings / phy / qcom,sc8280xp-qmp-ufs-phy.yaml
blob: f3a3296c811cb3403201642703c77060b7ed1c36 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame^]1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-ufs-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm QMP PHY controller (UFS, SC8280XP)
8
9maintainers:
10 - Vinod Koul <vkoul@kernel.org>
11
12description:
13 The QMP PHY controller supports physical layer functionality for a number of
14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
15
16properties:
17 compatible:
18 enum:
19 - qcom,msm8996-qmp-ufs-phy
20 - qcom,msm8998-qmp-ufs-phy
21 - qcom,sa8775p-qmp-ufs-phy
22 - qcom,sc7280-qmp-ufs-phy
23 - qcom,sc8180x-qmp-ufs-phy
24 - qcom,sc8280xp-qmp-ufs-phy
25 - qcom,sdm845-qmp-ufs-phy
26 - qcom,sm6115-qmp-ufs-phy
27 - qcom,sm6125-qmp-ufs-phy
28 - qcom,sm6350-qmp-ufs-phy
29 - qcom,sm7150-qmp-ufs-phy
30 - qcom,sm8150-qmp-ufs-phy
31 - qcom,sm8250-qmp-ufs-phy
32 - qcom,sm8350-qmp-ufs-phy
33 - qcom,sm8450-qmp-ufs-phy
34 - qcom,sm8550-qmp-ufs-phy
35
36 reg:
37 maxItems: 1
38
39 clocks:
40 minItems: 1
41 maxItems: 3
42
43 clock-names:
44 minItems: 1
45 items:
46 - const: ref
47 - const: ref_aux
48 - const: qref
49
50 power-domains:
51 maxItems: 1
52
53 resets:
54 maxItems: 1
55
56 reset-names:
57 items:
58 - const: ufsphy
59
60 vdda-phy-supply: true
61
62 vdda-pll-supply: true
63
64 "#clock-cells":
65 const: 1
66
67 "#phy-cells":
68 const: 0
69
70required:
71 - compatible
72 - reg
73 - clocks
74 - clock-names
75 - power-domains
76 - resets
77 - reset-names
78 - vdda-phy-supply
79 - vdda-pll-supply
80 - "#phy-cells"
81
82allOf:
83 - if:
84 properties:
85 compatible:
86 contains:
87 enum:
88 - qcom,sa8775p-qmp-ufs-phy
89 - qcom,sc7280-qmp-ufs-phy
90 - qcom,sm8450-qmp-ufs-phy
91 then:
92 properties:
93 clocks:
94 minItems: 3
95 clock-names:
96 minItems: 3
97
98 - if:
99 properties:
100 compatible:
101 contains:
102 enum:
103 - qcom,msm8998-qmp-ufs-phy
104 - qcom,sc8180x-qmp-ufs-phy
105 - qcom,sc8280xp-qmp-ufs-phy
106 - qcom,sdm845-qmp-ufs-phy
107 - qcom,sm6115-qmp-ufs-phy
108 - qcom,sm6125-qmp-ufs-phy
109 - qcom,sm6350-qmp-ufs-phy
110 - qcom,sm7150-qmp-ufs-phy
111 - qcom,sm8150-qmp-ufs-phy
112 - qcom,sm8250-qmp-ufs-phy
113 - qcom,sm8350-qmp-ufs-phy
114 - qcom,sm8550-qmp-ufs-phy
115 then:
116 properties:
117 clocks:
118 maxItems: 2
119 clock-names:
120 maxItems: 2
121
122 - if:
123 properties:
124 compatible:
125 contains:
126 enum:
127 - qcom,msm8996-qmp-ufs-phy
128 then:
129 properties:
130 clocks:
131 maxItems: 1
132 clock-names:
133 maxItems: 1
134
135additionalProperties: false
136
137examples:
138 - |
139 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
140
141 ufs_mem_phy: phy@1d87000 {
142 compatible = "qcom,sc8280xp-qmp-ufs-phy";
143 reg = <0x01d87000 0x1000>;
144
145 clocks = <&gcc GCC_UFS_REF_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
146 clock-names = "ref", "ref_aux";
147
148 power-domains = <&gcc UFS_PHY_GDSC>;
149
150 resets = <&ufs_mem_hc 0>;
151 reset-names = "ufsphy";
152
153 vdda-phy-supply = <&vreg_l6b>;
154 vdda-pll-supply = <&vreg_l3b>;
155
156 #phy-cells = <0>;
157 };