blob: 4df0a69cfe10f90505689e537572b3c493ece11a [file] [log] [blame]
Hai Pham68f1ac02023-02-28 22:37:02 +01001// SPDX-License-Identifier: GPL-2.0
2/*
3 * r8a779g0 Clock Pulse Generator / Module Standby and Software Reset
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 *
7 * Based on r8a779f0-cpg-mssr.c
8 */
9
Hai Pham68f1ac02023-02-28 22:37:02 +010010#include <clk-uclass.h>
11#include <dm.h>
12
13#include <dt-bindings/clock/r8a779g0-cpg-mssr.h>
14
15#include "renesas-cpg-mssr.h"
16#include "rcar-gen3-cpg.h"
17
18enum clk_ids {
19 /* Core Clock Outputs exported to DT */
Marek Vasutc9c2d352024-06-19 00:54:18 +020020 LAST_DT_CORE_CLK = R8A779G0_CLK_CP,
Hai Pham68f1ac02023-02-28 22:37:02 +010021
22 /* External Input Clocks */
23 CLK_EXTAL,
24 CLK_EXTALR,
25
26 /* Internal Core Clocks */
27 CLK_MAIN,
28 CLK_PLL1,
29 CLK_PLL2,
30 CLK_PLL3,
31 CLK_PLL4,
32 CLK_PLL5,
33 CLK_PLL6,
34 CLK_PLL1_DIV2,
35 CLK_PLL2_DIV2,
36 CLK_PLL3_DIV2,
37 CLK_PLL4_DIV2,
38 CLK_PLL5_DIV2,
39 CLK_PLL5_DIV4,
40 CLK_PLL6_DIV2,
41 CLK_S0,
42 CLK_S0_VIO,
43 CLK_S0_VC,
44 CLK_S0_HSC,
45 CLK_SASYNCPER,
46 CLK_SV_VIP,
47 CLK_SV_IR,
48 CLK_SDSRC,
49 CLK_RPCSRC,
50 CLK_VIO,
51 CLK_VC,
52 CLK_OCO,
53
54 /* Module Clocks */
55 MOD_CLK_BASE
56};
57
Marek Vasut3c7646e2023-09-17 16:11:37 +020058static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
Hai Pham68f1ac02023-02-28 22:37:02 +010059 /* External Clock Inputs */
60 DEF_INPUT("extal", CLK_EXTAL),
61 DEF_INPUT("extalr", CLK_EXTALR),
62
63 /* Internal Core Clocks */
64 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL),
65 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN),
66 DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN4_PLL2, CLK_MAIN),
67 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN4_PLL3, CLK_MAIN),
68 DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN4_PLL4, CLK_MAIN),
69 DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN),
70 DEF_BASE(".pll6", CLK_PLL6, CLK_TYPE_GEN4_PLL6, CLK_MAIN),
71
72 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
73 DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 2, 1),
74 DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 2, 1),
75 DEF_FIXED(".pll4_div2", CLK_PLL4_DIV2, CLK_PLL4, 2, 1),
76 DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2, CLK_PLL5, 2, 1),
77 DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1),
78 DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2, CLK_PLL6, 2, 1),
79 DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
80 DEF_FIXED(".s0_vio", CLK_S0_VIO, CLK_PLL1_DIV2, 2, 1),
81 DEF_FIXED(".s0_vc", CLK_S0_VC, CLK_PLL1_DIV2, 2, 1),
82 DEF_FIXED(".s0_hsc", CLK_S0_HSC, CLK_PLL1_DIV2, 2, 1),
83 DEF_FIXED(".sasyncper", CLK_SASYNCPER, CLK_PLL5_DIV4, 3, 1),
84 DEF_FIXED(".sv_vip", CLK_SV_VIP, CLK_PLL1, 5, 1),
85 DEF_FIXED(".sv_ir", CLK_SV_IR, CLK_PLL1, 5, 1),
86 DEF_BASE(".sdsrc", CLK_SDSRC, CLK_TYPE_GEN4_SDSRC, CLK_PLL5),
87 DEF_RATE(".oco", CLK_OCO, 32768),
88
89 DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
90 DEF_FIXED(".vio", CLK_VIO, CLK_PLL5_DIV2, 3, 1),
91 DEF_FIXED(".vc", CLK_VC, CLK_PLL5_DIV2, 3, 1),
92
93 /* Core Clock Outputs */
94 DEF_GEN4_Z("z0", R8A779G0_CLK_Z0, CLK_TYPE_GEN4_Z, CLK_PLL2, 2, 0),
95 DEF_FIXED("s0d2", R8A779G0_CLK_S0D2, CLK_S0, 2, 1),
96 DEF_FIXED("s0d3", R8A779G0_CLK_S0D3, CLK_S0, 3, 1),
97 DEF_FIXED("s0d4", R8A779G0_CLK_S0D4, CLK_S0, 4, 1),
98 DEF_FIXED("cl16m", R8A779G0_CLK_CL16M, CLK_S0, 48, 1),
99 DEF_FIXED("s0d1_vio", R8A779G0_CLK_S0D1_VIO, CLK_S0_VIO, 1, 1),
100 DEF_FIXED("s0d2_vio", R8A779G0_CLK_S0D2_VIO, CLK_S0_VIO, 2, 1),
101 DEF_FIXED("s0d4_vio", R8A779G0_CLK_S0D4_VIO, CLK_S0_VIO, 4, 1),
102 DEF_FIXED("s0d8_vio", R8A779G0_CLK_S0D8_VIO, CLK_S0_VIO, 8, 1),
103 DEF_FIXED("s0d1_vc", R8A779G0_CLK_S0D1_VC, CLK_S0_VC, 1, 1),
104 DEF_FIXED("s0d2_vc", R8A779G0_CLK_S0D2_VC, CLK_S0_VC, 2, 1),
105 DEF_FIXED("s0d4_vc", R8A779G0_CLK_S0D4_VC, CLK_S0_VC, 4, 1),
106 DEF_FIXED("s0d2_mm", R8A779G0_CLK_S0D2_MM, CLK_S0, 2, 1),
107 DEF_FIXED("s0d4_mm", R8A779G0_CLK_S0D4_MM, CLK_S0, 4, 1),
108 DEF_FIXED("cl16m_mm", R8A779G0_CLK_CL16M_MM, CLK_S0, 48, 1),
109 DEF_FIXED("s0d2_u3dg", R8A779G0_CLK_S0D2_U3DG, CLK_S0, 2, 1),
110 DEF_FIXED("s0d4_u3dg", R8A779G0_CLK_S0D4_U3DG, CLK_S0, 4, 1),
111 DEF_FIXED("s0d2_rt", R8A779G0_CLK_S0D2_RT, CLK_S0, 2, 1),
112 DEF_FIXED("s0d3_rt", R8A779G0_CLK_S0D3_RT, CLK_S0, 3, 1),
113 DEF_FIXED("s0d4_rt", R8A779G0_CLK_S0D4_RT, CLK_S0, 4, 1),
114 DEF_FIXED("s0d6_rt", R8A779G0_CLK_S0D6_RT, CLK_S0, 6, 1),
115 DEF_FIXED("s0d24_rt", R8A779G0_CLK_S0D24_RT, CLK_S0, 24, 1),
116 DEF_FIXED("cl16m_rt", R8A779G0_CLK_CL16M_RT, CLK_S0, 48, 1),
117 DEF_FIXED("s0d2_per", R8A779G0_CLK_S0D2_PER, CLK_S0, 2, 1),
118 DEF_FIXED("s0d3_per", R8A779G0_CLK_S0D3_PER, CLK_S0, 3, 1),
119 DEF_FIXED("s0d4_per", R8A779G0_CLK_S0D4_PER, CLK_S0, 4, 1),
120 DEF_FIXED("s0d6_per", R8A779G0_CLK_S0D6_PER, CLK_S0, 6, 1),
121 DEF_FIXED("s0d12_per", R8A779G0_CLK_S0D12_PER, CLK_S0, 12, 1),
122 DEF_FIXED("s0d24_per", R8A779G0_CLK_S0D24_PER, CLK_S0, 24, 1),
123 DEF_FIXED("cl16m_per", R8A779G0_CLK_CL16M_PER, CLK_S0, 48, 1),
124 DEF_FIXED("s0d1_hsc", R8A779G0_CLK_S0D1_HSC, CLK_S0_HSC, 1, 1),
125 DEF_FIXED("s0d2_hsc", R8A779G0_CLK_S0D2_HSC, CLK_S0_HSC, 2, 1),
126 DEF_FIXED("s0d4_hsc", R8A779G0_CLK_S0D4_HSC, CLK_S0_HSC, 4, 1),
127 DEF_FIXED("cl16m_hsc", R8A779G0_CLK_CL16M_HSC, CLK_S0_HSC, 48, 1),
128 DEF_FIXED("s0d2_cc", R8A779G0_CLK_S0D2_CC, CLK_S0, 2, 1),
129 DEF_FIXED("sasyncrt", R8A779G0_CLK_SASYNCRT, CLK_PLL5_DIV4, 48, 1),
130 DEF_FIXED("sasyncperd1",R8A779G0_CLK_SASYNCPERD1, CLK_SASYNCPER,1, 1),
131 DEF_FIXED("sasyncperd2",R8A779G0_CLK_SASYNCPERD2, CLK_SASYNCPER,2, 1),
132 DEF_FIXED("sasyncperd4",R8A779G0_CLK_SASYNCPERD4, CLK_SASYNCPER,4, 1),
133 DEF_FIXED("svd1_ir", R8A779G0_CLK_SVD1_IR, CLK_SV_IR, 1, 1),
134 DEF_FIXED("svd2_ir", R8A779G0_CLK_SVD2_IR, CLK_SV_IR, 2, 1),
135 DEF_FIXED("svd1_vip", R8A779G0_CLK_SVD1_VIP, CLK_SV_VIP, 1, 1),
136 DEF_FIXED("svd2_vip", R8A779G0_CLK_SVD2_VIP, CLK_SV_VIP, 2, 1),
137 DEF_FIXED("cbfusa", R8A779G0_CLK_CBFUSA, CLK_EXTAL, 2, 1),
138 DEF_FIXED("cpex", R8A779G0_CLK_CPEX, CLK_EXTAL, 2, 1),
Marek Vasutc9c2d352024-06-19 00:54:18 +0200139 DEF_FIXED("cp", R8A779G0_CLK_CP, CLK_EXTAL, 2, 1),
Hai Pham68f1ac02023-02-28 22:37:02 +0100140 DEF_FIXED("viobus", R8A779G0_CLK_VIOBUS, CLK_VIO, 1, 1),
141 DEF_FIXED("viobusd2", R8A779G0_CLK_VIOBUSD2, CLK_VIO, 2, 1),
142 DEF_FIXED("vcbus", R8A779G0_CLK_VCBUS, CLK_VC, 1, 1),
143 DEF_FIXED("vcbusd2", R8A779G0_CLK_VCBUSD2, CLK_VC, 2, 1),
144 DEF_DIV6P1("canfd", R8A779G0_CLK_CANFD, CLK_PLL5_DIV4, 0x878),
Marek Vasut3c7646e2023-09-17 16:11:37 +0200145 DEF_DIV6P1("csi", R8A779G0_CLK_CSI, CLK_PLL5_DIV4, 0x880),
Hai Pham68f1ac02023-02-28 22:37:02 +0100146 DEF_FIXED("dsiref", R8A779G0_CLK_DSIREF, CLK_PLL5_DIV4, 48, 1),
147 DEF_DIV6P1("dsiext", R8A779G0_CLK_DSIEXT, CLK_PLL5_DIV4, 0x884),
148
149 DEF_GEN4_SDH("sd0h", R8A779G0_CLK_SD0H, CLK_SDSRC, 0x870),
150 DEF_GEN4_SD("sd0", R8A779G0_CLK_SD0, R8A779G0_CLK_SD0H, 0x870),
151 DEF_DIV6P1("mso", R8A779G0_CLK_MSO, CLK_PLL5_DIV4, 0x87c),
152
153 DEF_BASE("rpc", R8A779G0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
154 DEF_BASE("rpcd2", R8A779G0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, R8A779G0_CLK_RPC),
155
156 DEF_GEN4_OSC("osc", R8A779G0_CLK_OSC, CLK_EXTAL, 8),
157 DEF_GEN4_MDSEL("r", R8A779G0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
158};
159
Marek Vasut3c7646e2023-09-17 16:11:37 +0200160static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
Hai Pham68f1ac02023-02-28 22:37:02 +0100161 DEF_MOD("avb0", 211, R8A779G0_CLK_S0D4_HSC),
162 DEF_MOD("avb1", 212, R8A779G0_CLK_S0D4_HSC),
163 DEF_MOD("avb2", 213, R8A779G0_CLK_S0D4_HSC),
164 DEF_MOD("canfd0", 328, R8A779G0_CLK_SASYNCPERD2),
Marek Vasut3c7646e2023-09-17 16:11:37 +0200165 DEF_MOD("csi40", 331, R8A779G0_CLK_CSI),
166 DEF_MOD("csi41", 400, R8A779G0_CLK_CSI),
Hai Pham68f1ac02023-02-28 22:37:02 +0100167 DEF_MOD("dis0", 411, R8A779G0_CLK_VIOBUSD2),
168 DEF_MOD("dsitxlink0", 415, R8A779G0_CLK_VIOBUSD2),
169 DEF_MOD("dsitxlink1", 416, R8A779G0_CLK_VIOBUSD2),
170 DEF_MOD("fcpvd0", 508, R8A779G0_CLK_VIOBUSD2),
171 DEF_MOD("fcpvd1", 509, R8A779G0_CLK_VIOBUSD2),
172 DEF_MOD("hscif0", 514, R8A779G0_CLK_SASYNCPERD1),
173 DEF_MOD("hscif1", 515, R8A779G0_CLK_SASYNCPERD1),
174 DEF_MOD("hscif2", 516, R8A779G0_CLK_SASYNCPERD1),
175 DEF_MOD("hscif3", 517, R8A779G0_CLK_SASYNCPERD1),
176 DEF_MOD("i2c0", 518, R8A779G0_CLK_S0D6_PER),
177 DEF_MOD("i2c1", 519, R8A779G0_CLK_S0D6_PER),
178 DEF_MOD("i2c2", 520, R8A779G0_CLK_S0D6_PER),
179 DEF_MOD("i2c3", 521, R8A779G0_CLK_S0D6_PER),
180 DEF_MOD("i2c4", 522, R8A779G0_CLK_S0D6_PER),
181 DEF_MOD("i2c5", 523, R8A779G0_CLK_S0D6_PER),
182 DEF_MOD("irqc", 611, R8A779G0_CLK_CL16M),
Marek Vasut3c7646e2023-09-17 16:11:37 +0200183 DEF_MOD("ispcs0", 612, R8A779G0_CLK_S0D2_VIO),
184 DEF_MOD("ispcs1", 613, R8A779G0_CLK_S0D2_VIO),
Hai Pham68f1ac02023-02-28 22:37:02 +0100185 DEF_MOD("msi0", 618, R8A779G0_CLK_MSO),
186 DEF_MOD("msi1", 619, R8A779G0_CLK_MSO),
187 DEF_MOD("msi2", 620, R8A779G0_CLK_MSO),
188 DEF_MOD("msi3", 621, R8A779G0_CLK_MSO),
189 DEF_MOD("msi4", 622, R8A779G0_CLK_MSO),
190 DEF_MOD("msi5", 623, R8A779G0_CLK_MSO),
Marek Vasutc9c2d352024-06-19 00:54:18 +0200191 DEF_MOD("pciec0", 624, R8A779G0_CLK_S0D2_HSC),
192 DEF_MOD("pciec1", 625, R8A779G0_CLK_S0D2_HSC),
Hai Pham68f1ac02023-02-28 22:37:02 +0100193 DEF_MOD("pwm", 628, R8A779G0_CLK_SASYNCPERD4),
194 DEF_MOD("rpc-if", 629, R8A779G0_CLK_RPCD2),
195 DEF_MOD("scif0", 702, R8A779G0_CLK_SASYNCPERD4),
196 DEF_MOD("scif1", 703, R8A779G0_CLK_SASYNCPERD4),
197 DEF_MOD("scif3", 704, R8A779G0_CLK_SASYNCPERD4),
198 DEF_MOD("scif4", 705, R8A779G0_CLK_SASYNCPERD4),
199 DEF_MOD("sdhi", 706, R8A779G0_CLK_SD0),
200 DEF_MOD("sys-dmac0", 709, R8A779G0_CLK_S0D6_PER),
201 DEF_MOD("sys-dmac1", 710, R8A779G0_CLK_S0D6_PER),
202 DEF_MOD("tmu0", 713, R8A779G0_CLK_SASYNCRT),
203 DEF_MOD("tmu1", 714, R8A779G0_CLK_SASYNCPERD2),
204 DEF_MOD("tmu2", 715, R8A779G0_CLK_SASYNCPERD2),
205 DEF_MOD("tmu3", 716, R8A779G0_CLK_SASYNCPERD2),
206 DEF_MOD("tmu4", 717, R8A779G0_CLK_SASYNCPERD2),
207 DEF_MOD("tpu0", 718, R8A779G0_CLK_SASYNCPERD4),
Marek Vasut3c7646e2023-09-17 16:11:37 +0200208 DEF_MOD("vin00", 730, R8A779G0_CLK_S0D4_VIO),
209 DEF_MOD("vin01", 731, R8A779G0_CLK_S0D4_VIO),
210 DEF_MOD("vin02", 800, R8A779G0_CLK_S0D4_VIO),
211 DEF_MOD("vin03", 801, R8A779G0_CLK_S0D4_VIO),
212 DEF_MOD("vin04", 802, R8A779G0_CLK_S0D4_VIO),
213 DEF_MOD("vin05", 803, R8A779G0_CLK_S0D4_VIO),
214 DEF_MOD("vin06", 804, R8A779G0_CLK_S0D4_VIO),
215 DEF_MOD("vin07", 805, R8A779G0_CLK_S0D4_VIO),
216 DEF_MOD("vin10", 806, R8A779G0_CLK_S0D4_VIO),
217 DEF_MOD("vin11", 807, R8A779G0_CLK_S0D4_VIO),
218 DEF_MOD("vin12", 808, R8A779G0_CLK_S0D4_VIO),
219 DEF_MOD("vin13", 809, R8A779G0_CLK_S0D4_VIO),
220 DEF_MOD("vin14", 810, R8A779G0_CLK_S0D4_VIO),
221 DEF_MOD("vin15", 811, R8A779G0_CLK_S0D4_VIO),
222 DEF_MOD("vin16", 812, R8A779G0_CLK_S0D4_VIO),
223 DEF_MOD("vin17", 813, R8A779G0_CLK_S0D4_VIO),
Hai Pham68f1ac02023-02-28 22:37:02 +0100224 DEF_MOD("vspd0", 830, R8A779G0_CLK_VIOBUSD2),
225 DEF_MOD("vspd1", 831, R8A779G0_CLK_VIOBUSD2),
226 DEF_MOD("wdt1:wdt0", 907, R8A779G0_CLK_R),
227 DEF_MOD("cmt0", 910, R8A779G0_CLK_R),
228 DEF_MOD("cmt1", 911, R8A779G0_CLK_R),
229 DEF_MOD("cmt2", 912, R8A779G0_CLK_R),
230 DEF_MOD("cmt3", 913, R8A779G0_CLK_R),
Marek Vasutc9c2d352024-06-19 00:54:18 +0200231 DEF_MOD("pfc0", 915, R8A779G0_CLK_CP),
232 DEF_MOD("pfc1", 916, R8A779G0_CLK_CP),
233 DEF_MOD("pfc2", 917, R8A779G0_CLK_CP),
234 DEF_MOD("pfc3", 918, R8A779G0_CLK_CP),
Marek Vasut3c7646e2023-09-17 16:11:37 +0200235 DEF_MOD("tsc", 919, R8A779G0_CLK_CL16M),
Marek Vasutc9c2d352024-06-19 00:54:18 +0200236 DEF_MOD("tsn", 2723, R8A779G0_CLK_S0D4_HSC),
Marek Vasut3c7646e2023-09-17 16:11:37 +0200237 DEF_MOD("ssiu", 2926, R8A779G0_CLK_S0D6_PER),
238 DEF_MOD("ssi", 2927, R8A779G0_CLK_S0D6_PER),
Hai Pham68f1ac02023-02-28 22:37:02 +0100239};
240
241/*
242 * CPG Clock Data
243 */
244/*
245 * MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
246 * 14 13 (MHz)
247 * ------------------------------------------------------------------------
248 * 0 0 16.66 / 1 x192 x204 x192 x144 x192 x168 /16
249 * 0 1 20 / 1 x160 x170 x160 x120 x160 x140 /19
250 * 1 0 Prohibited setting
251 * 1 1 33.33 / 2 x192 x204 x192 x144 x192 x168 /32
252 */
253#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
254 (((md) & BIT(13)) >> 13))
255
256static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {
257 /* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */
258 { 1, 192, 1, 204, 1, 192, 1, 144, 1, 192, 1, 168, 1, 16, },
259 { 1, 160, 1, 170, 1, 160, 1, 120, 1, 160, 1, 140, 1, 19, },
260 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
261 { 2, 192, 1, 204, 1, 192, 1, 144, 1, 192, 1, 168, 1, 32, },
262};
263
264/*
265 * Note that the only clock left running before booting Linux are now
266 * MFIS, INTC-AP, INTC-EX, SCIF0, HSCIF0 on V4H
267 */
268#define MSTPCR5_HSCIF0 BIT(14) /* No information: MFIS, INTC-AP */
269#define MSTPCR6_INTCEX BIT(11) /* No information: MFIS, INTC-AP */
270#define MSTPCR7_SCIF0 BIT(2) /* No information: MFIS, INTC-AP */
271static const struct mstp_stop_table r8a779g0_mstp_table[] = {
272 { 0x0FC302A1, 0x0, 0x0, 0x0 },
273 { 0x00D50038, 0x0, 0x0, 0x0 },
274 { 0x00003800, 0x0, 0x0, 0x0 },
275 { 0xF0000000, 0x0, 0x0, 0x0 },
276 { 0x0001CE01, 0x0, 0x0, 0x0 },
277 { 0xEEFFE380, MSTPCR5_HSCIF0, 0x0, 0x0 },
278 { 0xF3FD3901, MSTPCR6_INTCEX, 0x0, 0x0 },
279 { 0xE007E6FF, MSTPCR7_SCIF0, 0x0, 0x0 },
280 { 0xC0003FFF, 0x0, 0x0, 0x0 },
281 { 0x001FBCF8, 0x0, 0x0, 0x0 },
282 { 0x30000000, 0x0, 0x0, 0x0 },
283 { 0x000000C3, 0x0, 0x0, 0x0 },
284 { 0xDE800000, 0x0, 0x0, 0x0 },
285 { 0x00000017, 0x0, 0x0, 0x0 },
286 { 0x00000000, 0x0, 0x0, 0x0 },
287 { 0x00000000, 0x0, 0x0, 0x0 },
288 { 0x00000000, 0x0, 0x0, 0x0 },
289 { 0x00000000, 0x0, 0x0, 0x0 },
290 { 0x00000000, 0x0, 0x0, 0x0 },
291 { 0x00000000, 0x0, 0x0, 0x0 },
292 { 0x00000000, 0x0, 0x0, 0x0 },
293 { 0x00000000, 0x0, 0x0, 0x0 },
294 { 0x00000000, 0x0, 0x0, 0x0 },
295 { 0x00000000, 0x0, 0x0, 0x0 },
296 { 0x00000000, 0x0, 0x0, 0x0 },
297 { 0x00000000, 0x0, 0x0, 0x0 },
298 { 0x00000000, 0x0, 0x0, 0x0 },
299 { 0x000033C0, 0x0, 0x0, 0x0 },
300 { 0x402A001E, 0x0, 0x0, 0x0 },
301 { 0x0C010080, 0x0, 0x0, 0x0 },
302};
303
304static const void *r8a779g0_get_pll_config(const u32 cpg_mode)
305{
306 return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
307}
308
309static const struct cpg_mssr_info r8a779g0_cpg_mssr_info = {
310 .core_clk = r8a779g0_core_clks,
311 .core_clk_size = ARRAY_SIZE(r8a779g0_core_clks),
312 .mod_clk = r8a779g0_mod_clks,
313 .mod_clk_size = ARRAY_SIZE(r8a779g0_mod_clks),
314 .mstp_table = r8a779g0_mstp_table,
315 .mstp_table_size = ARRAY_SIZE(r8a779g0_mstp_table),
316 .reset_node = "renesas,r8a779g0-rst",
317 .reset_modemr_offset = CPG_RST_MODEMR0,
318 .extalr_node = "extalr",
319 .mod_clk_base = MOD_CLK_BASE,
320 .clk_extal_id = CLK_EXTAL,
321 .clk_extalr_id = CLK_EXTALR,
322 .get_pll_config = r8a779g0_get_pll_config,
323 .reg_layout = CLK_REG_LAYOUT_RCAR_GEN4,
324};
325
326static const struct udevice_id r8a779g0_cpg_ids[] = {
327 {
328 .compatible = "renesas,r8a779g0-cpg-mssr",
329 .data = (ulong)&r8a779g0_cpg_mssr_info
330 },
331 { }
332};
333
334U_BOOT_DRIVER(cpg_r8a779g0) = {
335 .name = "cpg_r8a779g0",
336 .id = UCLASS_NOP,
337 .of_match = r8a779g0_cpg_ids,
338 .bind = gen3_cpg_bind,
339};