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git01.mediatek.com / filogic / uboot / f8bdf6e0e3693c81f801f62e60f618a5b1b51ae3 / . / board / google / chromebook_link / link.c
blob: d12d74202c51a6ed1f6dc2d0eade9be6e4c865b7 [file] [log] [blame]
Simon Glass0b36ecd2014-11-12 22:42:07 -0700[diff] [blame]1/*
2 * Copyright (C) 2014 Google, Inc
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
Simon Glass7f251c42014-11-14 20:56:45 -0700[diff] [blame]8#include <cros_ec.h>
Simon Glass3da658a2015-03-05 12:25:32 -0700[diff] [blame]9#include <dm.h>
Simon Glass9a447682014-11-12 22:42:25 -0700[diff] [blame]10#include <asm/gpio.h>
Bin Menga55173f2014-12-12 21:05:23 +0800[diff] [blame]11#include <asm/io.h>
12#include <asm/pci.h>
13#include <asm/arch/pch.h>
Simon Glass0b36ecd2014-11-12 22:42:07 -0700[diff] [blame]14
15int arch_early_init_r(void)
16{
17 return 0;
18}
19
Simon Glass9a447682014-11-12 22:42:25 -0700[diff] [blame]20static const struct pch_gpio_set1 pch_gpio_set1_mode = {
21 .gpio0 = GPIO_MODE_GPIO, /* NMI_DBG# */
22 .gpio3 = GPIO_MODE_GPIO, /* ALS_INT# */
23 .gpio5 = GPIO_MODE_GPIO, /* SIM_DET */
24 .gpio7 = GPIO_MODE_GPIO, /* EC_SCI# */
25 .gpio8 = GPIO_MODE_GPIO, /* EC_SMI# */
26 .gpio9 = GPIO_MODE_GPIO, /* RECOVERY# */
27 .gpio10 = GPIO_MODE_GPIO, /* SPD vector D3 */
28 .gpio11 = GPIO_MODE_GPIO, /* smbalert#, let's keep it initialized */
29 .gpio12 = GPIO_MODE_GPIO, /* TP_INT# */
30 .gpio14 = GPIO_MODE_GPIO, /* Touch_INT_L */
31 .gpio15 = GPIO_MODE_GPIO, /* EC_LID_OUT# (EC_WAKE#) */
32 .gpio21 = GPIO_MODE_GPIO, /* EC_IN_RW */
33 .gpio24 = GPIO_MODE_GPIO, /* DDR3L_EN */
34 .gpio28 = GPIO_MODE_GPIO, /* SLP_ME_CSW_DEV# */
35};
36
37static const struct pch_gpio_set1 pch_gpio_set1_direction = {
38 .gpio0 = GPIO_DIR_INPUT,
39 .gpio3 = GPIO_DIR_INPUT,
40 .gpio5 = GPIO_DIR_INPUT,
41 .gpio7 = GPIO_DIR_INPUT,
42 .gpio8 = GPIO_DIR_INPUT,
43 .gpio9 = GPIO_DIR_INPUT,
44 .gpio10 = GPIO_DIR_INPUT,
45 .gpio11 = GPIO_DIR_INPUT,
46 .gpio12 = GPIO_DIR_INPUT,
47 .gpio14 = GPIO_DIR_INPUT,
48 .gpio15 = GPIO_DIR_INPUT,
49 .gpio21 = GPIO_DIR_INPUT,
50 .gpio24 = GPIO_DIR_OUTPUT,
51 .gpio28 = GPIO_DIR_INPUT,
52};
53
54static const struct pch_gpio_set1 pch_gpio_set1_level = {
55 .gpio1 = GPIO_LEVEL_HIGH,
56 .gpio6 = GPIO_LEVEL_HIGH,
57 .gpio24 = GPIO_LEVEL_LOW,
58};
59
60static const struct pch_gpio_set1 pch_gpio_set1_invert = {
61 .gpio7 = GPIO_INVERT,
62 .gpio8 = GPIO_INVERT,
63 .gpio12 = GPIO_INVERT,
64 .gpio14 = GPIO_INVERT,
65 .gpio15 = GPIO_INVERT,
66};
67
68static const struct pch_gpio_set2 pch_gpio_set2_mode = {
69 .gpio36 = GPIO_MODE_GPIO, /* W_DISABLE_L */
70 .gpio41 = GPIO_MODE_GPIO, /* SPD vector D0 */
71 .gpio42 = GPIO_MODE_GPIO, /* SPD vector D1 */
72 .gpio43 = GPIO_MODE_GPIO, /* SPD vector D2 */
73 .gpio57 = GPIO_MODE_GPIO, /* PCH_SPI_WP_D */
74 .gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */
75};
76
77static const struct pch_gpio_set2 pch_gpio_set2_direction = {
78 .gpio36 = GPIO_DIR_OUTPUT,
79 .gpio41 = GPIO_DIR_INPUT,
80 .gpio42 = GPIO_DIR_INPUT,
81 .gpio43 = GPIO_DIR_INPUT,
82 .gpio57 = GPIO_DIR_INPUT,
83 .gpio60 = GPIO_DIR_OUTPUT,
84};
85
86static const struct pch_gpio_set2 pch_gpio_set2_level = {
87 .gpio36 = GPIO_LEVEL_HIGH,
88 .gpio60 = GPIO_LEVEL_HIGH,
89};
90
91static const struct pch_gpio_set3 pch_gpio_set3_mode = {
92};
93
94static const struct pch_gpio_set3 pch_gpio_set3_direction = {
95};
96
97static const struct pch_gpio_set3 pch_gpio_set3_level = {
98};
99
100static const struct pch_gpio_map link_gpio_map = {
101 .set1 = {
102 .mode = &pch_gpio_set1_mode,
103 .direction = &pch_gpio_set1_direction,
104 .level = &pch_gpio_set1_level,
105 .invert = &pch_gpio_set1_invert,
106 },
107 .set2 = {
108 .mode = &pch_gpio_set2_mode,
109 .direction = &pch_gpio_set2_direction,
110 .level = &pch_gpio_set2_level,
111 },
112 .set3 = {
113 .mode = &pch_gpio_set3_mode,
114 .direction = &pch_gpio_set3_direction,
115 .level = &pch_gpio_set3_level,
116 },
117};
118
119int board_early_init_f(void)
120{
121 ich_gpio_set_gpio_map(&link_gpio_map);
122
123 return 0;
124}
Bin Menga55173f2014-12-12 21:05:23 +0800[diff] [blame]125
Bin Meng9b649692014-12-17 15:50:38 +0800[diff] [blame]126void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
Bin Menga55173f2014-12-12 21:05:23 +0800[diff] [blame]127{
128 /* GPIO Set 1 */
129 if (gpio->set1.level)
130 outl(*((u32 *)gpio->set1.level), gpiobase + GP_LVL);
131 if (gpio->set1.mode)
132 outl(*((u32 *)gpio->set1.mode), gpiobase + GPIO_USE_SEL);
133 if (gpio->set1.direction)
134 outl(*((u32 *)gpio->set1.direction), gpiobase + GP_IO_SEL);
135 if (gpio->set1.reset)
136 outl(*((u32 *)gpio->set1.reset), gpiobase + GP_RST_SEL1);
137 if (gpio->set1.invert)
138 outl(*((u32 *)gpio->set1.invert), gpiobase + GPI_INV);
139 if (gpio->set1.blink)
140 outl(*((u32 *)gpio->set1.blink), gpiobase + GPO_BLINK);
141
142 /* GPIO Set 2 */
143 if (gpio->set2.level)
144 outl(*((u32 *)gpio->set2.level), gpiobase + GP_LVL2);
145 if (gpio->set2.mode)
146 outl(*((u32 *)gpio->set2.mode), gpiobase + GPIO_USE_SEL2);
147 if (gpio->set2.direction)
148 outl(*((u32 *)gpio->set2.direction), gpiobase + GP_IO_SEL2);
149 if (gpio->set2.reset)
150 outl(*((u32 *)gpio->set2.reset), gpiobase + GP_RST_SEL2);
151
152 /* GPIO Set 3 */
153 if (gpio->set3.level)
154 outl(*((u32 *)gpio->set3.level), gpiobase + GP_LVL3);
155 if (gpio->set3.mode)
156 outl(*((u32 *)gpio->set3.mode), gpiobase + GPIO_USE_SEL3);
157 if (gpio->set3.direction)
158 outl(*((u32 *)gpio->set3.direction), gpiobase + GP_IO_SEL3);
159 if (gpio->set3.reset)
160 outl(*((u32 *)gpio->set3.reset), gpiobase + GP_RST_SEL3);
161}