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git01.mediatek.com / filogic / uboot / 3da658a598316c8f362a90b8086cce302013aac7 / . / board / google / chromebook_link / link.c
blob: 8c04cb82802fc9b47bd84b56751e714904d6c00b [file] [log] [blame]
Simon Glass0b36ecd2014-11-12 22:42:07 -0700[diff] [blame]1/*
2 * Copyright (C) 2014 Google, Inc
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
Simon Glass7f251c42014-11-14 20:56:45 -0700[diff] [blame]8#include <cros_ec.h>
Simon Glass3da658a2015-03-05 12:25:32 -0700[diff] [blame^]9#include <dm.h>
Simon Glass9a447682014-11-12 22:42:25 -0700[diff] [blame]10#include <asm/gpio.h>
Bin Menga55173f2014-12-12 21:05:23 +0800[diff] [blame]11#include <asm/io.h>
12#include <asm/pci.h>
13#include <asm/arch/pch.h>
Simon Glass0b36ecd2014-11-12 22:42:07 -0700[diff] [blame]14
15int arch_early_init_r(void)
16{
Simon Glass3da658a2015-03-05 12:25:32 -0700[diff] [blame^]17 struct udevice *dev;
18 int ret;
19
20 /* Make sure the platform controller hub is up and running */
21 ret = uclass_get_device(UCLASS_PCH, 0, &dev);
22 if (ret)
23 return ret;
24
Simon Glass7f251c42014-11-14 20:56:45 -0700[diff] [blame]25 if (cros_ec_board_init())
26 return -1;
27
Simon Glass0b36ecd2014-11-12 22:42:07 -0700[diff] [blame]28 return 0;
29}
30
Simon Glass9a447682014-11-12 22:42:25 -0700[diff] [blame]31static const struct pch_gpio_set1 pch_gpio_set1_mode = {
32 .gpio0 = GPIO_MODE_GPIO, /* NMI_DBG# */
33 .gpio3 = GPIO_MODE_GPIO, /* ALS_INT# */
34 .gpio5 = GPIO_MODE_GPIO, /* SIM_DET */
35 .gpio7 = GPIO_MODE_GPIO, /* EC_SCI# */
36 .gpio8 = GPIO_MODE_GPIO, /* EC_SMI# */
37 .gpio9 = GPIO_MODE_GPIO, /* RECOVERY# */
38 .gpio10 = GPIO_MODE_GPIO, /* SPD vector D3 */
39 .gpio11 = GPIO_MODE_GPIO, /* smbalert#, let's keep it initialized */
40 .gpio12 = GPIO_MODE_GPIO, /* TP_INT# */
41 .gpio14 = GPIO_MODE_GPIO, /* Touch_INT_L */
42 .gpio15 = GPIO_MODE_GPIO, /* EC_LID_OUT# (EC_WAKE#) */
43 .gpio21 = GPIO_MODE_GPIO, /* EC_IN_RW */
44 .gpio24 = GPIO_MODE_GPIO, /* DDR3L_EN */
45 .gpio28 = GPIO_MODE_GPIO, /* SLP_ME_CSW_DEV# */
46};
47
48static const struct pch_gpio_set1 pch_gpio_set1_direction = {
49 .gpio0 = GPIO_DIR_INPUT,
50 .gpio3 = GPIO_DIR_INPUT,
51 .gpio5 = GPIO_DIR_INPUT,
52 .gpio7 = GPIO_DIR_INPUT,
53 .gpio8 = GPIO_DIR_INPUT,
54 .gpio9 = GPIO_DIR_INPUT,
55 .gpio10 = GPIO_DIR_INPUT,
56 .gpio11 = GPIO_DIR_INPUT,
57 .gpio12 = GPIO_DIR_INPUT,
58 .gpio14 = GPIO_DIR_INPUT,
59 .gpio15 = GPIO_DIR_INPUT,
60 .gpio21 = GPIO_DIR_INPUT,
61 .gpio24 = GPIO_DIR_OUTPUT,
62 .gpio28 = GPIO_DIR_INPUT,
63};
64
65static const struct pch_gpio_set1 pch_gpio_set1_level = {
66 .gpio1 = GPIO_LEVEL_HIGH,
67 .gpio6 = GPIO_LEVEL_HIGH,
68 .gpio24 = GPIO_LEVEL_LOW,
69};
70
71static const struct pch_gpio_set1 pch_gpio_set1_invert = {
72 .gpio7 = GPIO_INVERT,
73 .gpio8 = GPIO_INVERT,
74 .gpio12 = GPIO_INVERT,
75 .gpio14 = GPIO_INVERT,
76 .gpio15 = GPIO_INVERT,
77};
78
79static const struct pch_gpio_set2 pch_gpio_set2_mode = {
80 .gpio36 = GPIO_MODE_GPIO, /* W_DISABLE_L */
81 .gpio41 = GPIO_MODE_GPIO, /* SPD vector D0 */
82 .gpio42 = GPIO_MODE_GPIO, /* SPD vector D1 */
83 .gpio43 = GPIO_MODE_GPIO, /* SPD vector D2 */
84 .gpio57 = GPIO_MODE_GPIO, /* PCH_SPI_WP_D */
85 .gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */
86};
87
88static const struct pch_gpio_set2 pch_gpio_set2_direction = {
89 .gpio36 = GPIO_DIR_OUTPUT,
90 .gpio41 = GPIO_DIR_INPUT,
91 .gpio42 = GPIO_DIR_INPUT,
92 .gpio43 = GPIO_DIR_INPUT,
93 .gpio57 = GPIO_DIR_INPUT,
94 .gpio60 = GPIO_DIR_OUTPUT,
95};
96
97static const struct pch_gpio_set2 pch_gpio_set2_level = {
98 .gpio36 = GPIO_LEVEL_HIGH,
99 .gpio60 = GPIO_LEVEL_HIGH,
100};
101
102static const struct pch_gpio_set3 pch_gpio_set3_mode = {
103};
104
105static const struct pch_gpio_set3 pch_gpio_set3_direction = {
106};
107
108static const struct pch_gpio_set3 pch_gpio_set3_level = {
109};
110
111static const struct pch_gpio_map link_gpio_map = {
112 .set1 = {
113 .mode = &pch_gpio_set1_mode,
114 .direction = &pch_gpio_set1_direction,
115 .level = &pch_gpio_set1_level,
116 .invert = &pch_gpio_set1_invert,
117 },
118 .set2 = {
119 .mode = &pch_gpio_set2_mode,
120 .direction = &pch_gpio_set2_direction,
121 .level = &pch_gpio_set2_level,
122 },
123 .set3 = {
124 .mode = &pch_gpio_set3_mode,
125 .direction = &pch_gpio_set3_direction,
126 .level = &pch_gpio_set3_level,
127 },
128};
129
130int board_early_init_f(void)
131{
132 ich_gpio_set_gpio_map(&link_gpio_map);
133
134 return 0;
135}
Bin Menga55173f2014-12-12 21:05:23 +0800[diff] [blame]136
Bin Meng9b649692014-12-17 15:50:38 +0800[diff] [blame]137void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
Bin Menga55173f2014-12-12 21:05:23 +0800[diff] [blame]138{
139 /* GPIO Set 1 */
140 if (gpio->set1.level)
141 outl(*((u32 *)gpio->set1.level), gpiobase + GP_LVL);
142 if (gpio->set1.mode)
143 outl(*((u32 *)gpio->set1.mode), gpiobase + GPIO_USE_SEL);
144 if (gpio->set1.direction)
145 outl(*((u32 *)gpio->set1.direction), gpiobase + GP_IO_SEL);
146 if (gpio->set1.reset)
147 outl(*((u32 *)gpio->set1.reset), gpiobase + GP_RST_SEL1);
148 if (gpio->set1.invert)
149 outl(*((u32 *)gpio->set1.invert), gpiobase + GPI_INV);
150 if (gpio->set1.blink)
151 outl(*((u32 *)gpio->set1.blink), gpiobase + GPO_BLINK);
152
153 /* GPIO Set 2 */
154 if (gpio->set2.level)
155 outl(*((u32 *)gpio->set2.level), gpiobase + GP_LVL2);
156 if (gpio->set2.mode)
157 outl(*((u32 *)gpio->set2.mode), gpiobase + GPIO_USE_SEL2);
158 if (gpio->set2.direction)
159 outl(*((u32 *)gpio->set2.direction), gpiobase + GP_IO_SEL2);
160 if (gpio->set2.reset)
161 outl(*((u32 *)gpio->set2.reset), gpiobase + GP_RST_SEL2);
162
163 /* GPIO Set 3 */
164 if (gpio->set3.level)
165 outl(*((u32 *)gpio->set3.level), gpiobase + GP_LVL3);
166 if (gpio->set3.mode)
167 outl(*((u32 *)gpio->set3.mode), gpiobase + GPIO_USE_SEL3);
168 if (gpio->set3.direction)
169 outl(*((u32 *)gpio->set3.direction), gpiobase + GP_IO_SEL3);
170 if (gpio->set3.reset)
171 outl(*((u32 *)gpio->set3.reset), gpiobase + GP_RST_SEL3);
172}