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wdenk9b7f3842003-10-09 20:09:04 +00001/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk9b7f3842003-10-09 20:09:04 +00006 */
7
8/*
9 * This file contains the configuration parameters for the dbau1x00 board.
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
wdenk9b7f3842003-10-09 20:09:04 +000015#define CONFIG_DBAU1X00 1
Shinya Kuribayashied49a6a2008-06-07 20:51:56 +090016#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
wdenk9b7f3842003-10-09 20:09:04 +000017
Daniel Schwierzeck2bc7eeb2014-11-15 23:30:01 +010018#define CONFIG_DISPLAY_BOARDINFO
19
wdenk4ea537d2003-12-07 18:32:37 +000020#ifdef CONFIG_DBAU1000
wdenk9b7f3842003-10-09 20:09:04 +000021/* Also known as Merlot */
Shinya Kuribayashied49a6a2008-06-07 20:51:56 +090022#define CONFIG_SOC_AU1000 1
wdenk4ea537d2003-12-07 18:32:37 +000023#else
24#ifdef CONFIG_DBAU1100
Shinya Kuribayashied49a6a2008-06-07 20:51:56 +090025#define CONFIG_SOC_AU1100 1
wdenk4ea537d2003-12-07 18:32:37 +000026#else
27#ifdef CONFIG_DBAU1500
Shinya Kuribayashied49a6a2008-06-07 20:51:56 +090028#define CONFIG_SOC_AU1500 1
wdenk1ebf41e2004-01-02 14:00:00 +000029#else
wdenk96c7a8c2005-01-09 22:28:56 +000030#ifdef CONFIG_DBAU1550
31/* Cabernet */
Shinya Kuribayashied49a6a2008-06-07 20:51:56 +090032#define CONFIG_SOC_AU1550 1
wdenk96c7a8c2005-01-09 22:28:56 +000033#else
wdenk4ea537d2003-12-07 18:32:37 +000034#error "No valid board set"
35#endif
36#endif
37#endif
wdenk96c7a8c2005-01-09 22:28:56 +000038#endif
wdenk9b7f3842003-10-09 20:09:04 +000039
wdenk9b7f3842003-10-09 20:09:04 +000040#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
41
42#define CONFIG_BAUDRATE 115200
43
44/* valid baudrates */
wdenk9b7f3842003-10-09 20:09:04 +000045
46#define CONFIG_TIMESTAMP /* Print image info with timestamp */
47#undef CONFIG_BOOTARGS
48
49#define CONFIG_EXTRA_ENV_SETTINGS \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010050 "addmisc=setenv bootargs ${bootargs} " \
51 "console=ttyS0,${baudrate} " \
wdenk9b7f3842003-10-09 20:09:04 +000052 "panic=1\0" \
53 "bootfile=/tftpboot/vmlinux.srec\0" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010054 "load=tftp 80500000 ${u-boot}\0" \
wdenk9b7f3842003-10-09 20:09:04 +000055 ""
wdenk96c7a8c2005-01-09 22:28:56 +000056
57#ifdef CONFIG_DBAU1550
58/* Boot from flash by default, revert to bootp */
59#define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm"
wdenk96c7a8c2005-01-09 22:28:56 +000060#else /* CONFIG_DBAU1550 */
Heiko Schocher65d4f8b2006-04-11 14:53:29 +020061#define CONFIG_BOOTCOMMAND "bootp;bootm"
wdenk96c7a8c2005-01-09 22:28:56 +000062#endif /* CONFIG_DBAU1550 */
63
Jon Loeligerb15a23b2007-07-04 22:32:03 -050064
65/*
Jon Loeligere54e77a2007-07-10 09:29:01 -050066 * BOOTP options
67 */
68#define CONFIG_BOOTP_BOOTFILESIZE
69#define CONFIG_BOOTP_BOOTPATH
70#define CONFIG_BOOTP_GATEWAY
71#define CONFIG_BOOTP_HOSTNAME
72
73
74/*
Jon Loeligerb15a23b2007-07-04 22:32:03 -050075 * Command line configuration.
76 */
77#include <config_cmd_default.h>
78
79#undef CONFIG_CMD_BDI
80#undef CONFIG_CMD_BEDBUG
81#undef CONFIG_CMD_ELF
Mike Frysinger78dcaf42009-01-28 19:08:14 -050082#undef CONFIG_CMD_SAVEENV
Jon Loeligerb15a23b2007-07-04 22:32:03 -050083#undef CONFIG_CMD_FAT
84#undef CONFIG_CMD_FPGA
85#undef CONFIG_CMD_MII
86#undef CONFIG_CMD_RUN
87
88
89#ifdef CONFIG_DBAU1550
90
91#define CONFIG_CMD_FLASH
92#define CONFIG_CMD_LOADB
Jon Loeligerb15a23b2007-07-04 22:32:03 -050093
94#undef CONFIG_CMD_I2C
95#undef CONFIG_CMD_IDE
96#undef CONFIG_CMD_NFS
97#undef CONFIG_CMD_PCMCIA
98
99#else
100
101#define CONFIG_CMD_IDE
102#define CONFIG_CMD_DHCP
103
104#undef CONFIG_CMD_FLASH
105#undef CONFIG_CMD_LOADB
106#undef CONFIG_CMD_LOADS
107
108#endif
109
wdenk9b7f3842003-10-09 20:09:04 +0000110
111/*
112 * Miscellaneous configurable options
113 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200114#define CONFIG_SYS_LONGHELP /* undef to save memory */
wdenk96c7a8c2005-01-09 22:28:56 +0000115
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200116#define CONFIG_SYS_PROMPT "DbAu1xx0 # " /* Monitor Command Prompt */
wdenk96c7a8c2005-01-09 22:28:56 +0000117
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200118#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
119#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
120#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
wdenk9b7f3842003-10-09 20:09:04 +0000121
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200122#define CONFIG_SYS_MALLOC_LEN 128*1024
wdenk9b7f3842003-10-09 20:09:04 +0000123
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200124#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
wdenk9b7f3842003-10-09 20:09:04 +0000125
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200126#define CONFIG_SYS_MHZ 396
wdenk96c7a8c2005-01-09 22:28:56 +0000127
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200128#if (CONFIG_SYS_MHZ % 12) != 0
wdenk96c7a8c2005-01-09 22:28:56 +0000129#error "Invalid CPU frequency - must be multiple of 12!"
130#endif
131
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200132#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
Shinya Kuribayashi5d374e02008-06-05 22:29:00 +0900133
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200134#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
wdenk9b7f3842003-10-09 20:09:04 +0000135
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200136#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */
wdenk9b7f3842003-10-09 20:09:04 +0000137
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200138#define CONFIG_SYS_MEMTEST_START 0x80100000
139#define CONFIG_SYS_MEMTEST_END 0x80800000
wdenk9b7f3842003-10-09 20:09:04 +0000140
141/*-----------------------------------------------------------------------
142 * FLASH and environment organization
143 */
wdenk96c7a8c2005-01-09 22:28:56 +0000144#ifdef CONFIG_DBAU1550
145
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200146#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
147#define CONFIG_SYS_MAX_FLASH_SECT (512) /* max number of sectors on one chip */
wdenk96c7a8c2005-01-09 22:28:56 +0000148
149#define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */
150#define PHYS_FLASH_2 0xbc000000 /* Flash Bank #2 */
151
wdenk96c7a8c2005-01-09 22:28:56 +0000152#else /* CONFIG_DBAU1550 */
153
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200154#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
155#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
wdenk9b7f3842003-10-09 20:09:04 +0000156
157#define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */
158#define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */
159
wdenk96c7a8c2005-01-09 22:28:56 +0000160#endif /* CONFIG_DBAU1550 */
161
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200162#define CONFIG_SYS_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2}
Heiko Schocher65d4f8b2006-04-11 14:53:29 +0200163
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200164#define CONFIG_SYS_FLASH_CFI 1
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200165#define CONFIG_FLASH_CFI_DRIVER 1
wdenk96c7a8c2005-01-09 22:28:56 +0000166
wdenk9b7f3842003-10-09 20:09:04 +0000167/* The following #defines are needed to get flash environment right */
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200168#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200169#define CONFIG_SYS_MONITOR_LEN (192 << 10)
wdenk9b7f3842003-10-09 20:09:04 +0000170
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200171#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
wdenk9b7f3842003-10-09 20:09:04 +0000172
173/* We boot from this flash, selected with dip switch */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200174#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2
wdenk9b7f3842003-10-09 20:09:04 +0000175
176/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200177#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
178#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
wdenk9b7f3842003-10-09 20:09:04 +0000179
Jean-Christophe PLAGNIOL-VILLARD68a87562008-09-10 22:48:00 +0200180#define CONFIG_ENV_IS_NOWHERE 1
wdenk9b7f3842003-10-09 20:09:04 +0000181
182/* Address and size of Primary Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200183#define CONFIG_ENV_ADDR 0xB0030000
184#define CONFIG_ENV_SIZE 0x10000
wdenk9b7f3842003-10-09 20:09:04 +0000185
186#define CONFIG_FLASH_16BIT
187
188#define CONFIG_NR_DRAM_BANKS 2
189
wdenk9b7f3842003-10-09 20:09:04 +0000190
wdenk96c7a8c2005-01-09 22:28:56 +0000191#ifdef CONFIG_DBAU1550
192#define MEM_SIZE 192
193#else
194#define MEM_SIZE 64
195#endif
196
wdenk9b7f3842003-10-09 20:09:04 +0000197#define CONFIG_MEMSIZE_IN_BYTES
198
wdenk96c7a8c2005-01-09 22:28:56 +0000199#ifndef CONFIG_DBAU1550
wdenk9b7f3842003-10-09 20:09:04 +0000200/*---ATA PCMCIA ------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200201#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
202#define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000
wdenk9b7f3842003-10-09 20:09:04 +0000203#define CONFIG_PCMCIA_SLOT_A
204
205#define CONFIG_ATAPI 1
206#define CONFIG_MAC_PARTITION 1
207
208/* We run CF in "true ide" mode or a harddrive via pcmcia */
209#define CONFIG_IDE_PCMCIA 1
210
211/* We only support one slot for now */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200212#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
213#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenk9b7f3842003-10-09 20:09:04 +0000214
215#undef CONFIG_IDE_LED /* LED for ide not supported */
216#undef CONFIG_IDE_RESET /* reset for ide not supported */
217
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200218#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenk9b7f3842003-10-09 20:09:04 +0000219
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200220#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenk9b7f3842003-10-09 20:09:04 +0000221
wdenk1ebf41e2004-01-02 14:00:00 +0000222/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200223#define CONFIG_SYS_ATA_DATA_OFFSET 8
wdenk9b7f3842003-10-09 20:09:04 +0000224
225/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200226#define CONFIG_SYS_ATA_REG_OFFSET 0
wdenk9b7f3842003-10-09 20:09:04 +0000227
228/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200229#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenk96c7a8c2005-01-09 22:28:56 +0000230#endif /* CONFIG_DBAU1550 */
wdenk9b7f3842003-10-09 20:09:04 +0000231
232/*-----------------------------------------------------------------------
233 * Cache Configuration
234 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200235#define CONFIG_SYS_DCACHE_SIZE 16384
236#define CONFIG_SYS_ICACHE_SIZE 16384
237#define CONFIG_SYS_CACHELINE_SIZE 32
wdenk9b7f3842003-10-09 20:09:04 +0000238
wdenk9b7f3842003-10-09 20:09:04 +0000239#endif /* __CONFIG_H */