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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Kumar Galae38209e2011-02-09 02:00:08 +00002/*
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
Kumar Galae38209e2011-02-09 02:00:08 +00004 */
5
6/*
7 * P5020 DS board configuration file
Scott Wooda1ef48c2012-08-14 10:14:51 +00008 * Also supports P5010 DS
Kumar Galae38209e2011-02-09 02:00:08 +00009 */
Kumar Galad0af3b92011-08-31 09:50:13 -050010#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
11
Kumar Galad0af3b92011-08-31 09:50:13 -050012#define CONFIG_NAND_FSL_ELBC
Zang Roy-R619112ce421a2012-11-26 00:05:38 +000013#define CONFIG_FSL_SATA_V2
Kumar Galad0af3b92011-08-31 09:50:13 -050014#define CONFIG_PCIE3
Kumar Galae38209e2011-02-09 02:00:08 +000015#define CONFIG_PCIE4
Kumar Gala9d8e8132011-09-10 10:44:13 -050016#define CONFIG_SYS_FSL_RAID_ENGINE
Kumar Gala4eb3c372011-10-14 13:28:52 -050017#define CONFIG_SYS_DPAA_RMAN
Kumar Galae38209e2011-02-09 02:00:08 +000018
Timur Tabi830b76f2012-10-05 09:48:53 +000019#define CONFIG_SYS_SRIO
20#define CONFIG_SRIO1 /* SRIO port 1 */
21#define CONFIG_SRIO2 /* SRIO port 2 */
Liu Gang27afb9c2013-05-07 16:30:46 +080022#define CONFIG_SRIO_PCIE_BOOT_MASTER
Kumar Galae38209e2011-02-09 02:00:08 +000023#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
24
25#include "corenet_ds.h"