Sricharan | 62a8650 | 2011-11-15 09:50:00 -0500 | [diff] [blame] | 1 | /* |
| 2 | * OMAP44xx EMIF header |
| 3 | * |
| 4 | * Copyright (C) 2009-2010 Texas Instruments, Inc. |
| 5 | * |
| 6 | * Aneesh V <aneesh@ti.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | */ |
| 12 | |
| 13 | #ifndef _EMIF_H_ |
| 14 | #define _EMIF_H_ |
| 15 | #include <asm/types.h> |
| 16 | #include <common.h> |
| 17 | |
| 18 | /* Base address */ |
| 19 | #define EMIF1_BASE 0x4c000000 |
| 20 | #define EMIF2_BASE 0x4d000000 |
| 21 | |
Tom Rini | 3fd4456 | 2012-07-03 08:51:34 -0700 | [diff] [blame] | 22 | /* Registers shifts, masks and values */ |
Sricharan | 62a8650 | 2011-11-15 09:50:00 -0500 | [diff] [blame] | 23 | |
| 24 | /* EMIF_MOD_ID_REV */ |
| 25 | #define EMIF_REG_SCHEME_SHIFT 30 |
| 26 | #define EMIF_REG_SCHEME_MASK (0x3 << 30) |
| 27 | #define EMIF_REG_MODULE_ID_SHIFT 16 |
| 28 | #define EMIF_REG_MODULE_ID_MASK (0xfff << 16) |
| 29 | #define EMIF_REG_RTL_VERSION_SHIFT 11 |
| 30 | #define EMIF_REG_RTL_VERSION_MASK (0x1f << 11) |
| 31 | #define EMIF_REG_MAJOR_REVISION_SHIFT 8 |
| 32 | #define EMIF_REG_MAJOR_REVISION_MASK (0x7 << 8) |
| 33 | #define EMIF_REG_MINOR_REVISION_SHIFT 0 |
| 34 | #define EMIF_REG_MINOR_REVISION_MASK (0x3f << 0) |
| 35 | |
| 36 | /* STATUS */ |
| 37 | #define EMIF_REG_BE_SHIFT 31 |
| 38 | #define EMIF_REG_BE_MASK (1 << 31) |
| 39 | #define EMIF_REG_DUAL_CLK_MODE_SHIFT 30 |
| 40 | #define EMIF_REG_DUAL_CLK_MODE_MASK (1 << 30) |
| 41 | #define EMIF_REG_FAST_INIT_SHIFT 29 |
| 42 | #define EMIF_REG_FAST_INIT_MASK (1 << 29) |
| 43 | #define EMIF_REG_PHY_DLL_READY_SHIFT 2 |
| 44 | #define EMIF_REG_PHY_DLL_READY_MASK (1 << 2) |
| 45 | |
| 46 | /* SDRAM_CONFIG */ |
| 47 | #define EMIF_REG_SDRAM_TYPE_SHIFT 29 |
| 48 | #define EMIF_REG_SDRAM_TYPE_MASK (0x7 << 29) |
Tom Rini | 3fd4456 | 2012-07-03 08:51:34 -0700 | [diff] [blame] | 49 | #define EMIF_REG_SDRAM_TYPE_DDR1 0 |
| 50 | #define EMIF_REG_SDRAM_TYPE_LPDDR1 1 |
| 51 | #define EMIF_REG_SDRAM_TYPE_DDR2 2 |
| 52 | #define EMIF_REG_SDRAM_TYPE_DDR3 3 |
| 53 | #define EMIF_REG_SDRAM_TYPE_LPDDR2_S4 4 |
| 54 | #define EMIF_REG_SDRAM_TYPE_LPDDR2_S2 5 |
Sricharan | 62a8650 | 2011-11-15 09:50:00 -0500 | [diff] [blame] | 55 | #define EMIF_REG_IBANK_POS_SHIFT 27 |
| 56 | #define EMIF_REG_IBANK_POS_MASK (0x3 << 27) |
| 57 | #define EMIF_REG_DDR_TERM_SHIFT 24 |
| 58 | #define EMIF_REG_DDR_TERM_MASK (0x7 << 24) |
| 59 | #define EMIF_REG_DDR2_DDQS_SHIFT 23 |
| 60 | #define EMIF_REG_DDR2_DDQS_MASK (1 << 23) |
| 61 | #define EMIF_REG_DYN_ODT_SHIFT 21 |
| 62 | #define EMIF_REG_DYN_ODT_MASK (0x3 << 21) |
| 63 | #define EMIF_REG_DDR_DISABLE_DLL_SHIFT 20 |
| 64 | #define EMIF_REG_DDR_DISABLE_DLL_MASK (1 << 20) |
| 65 | #define EMIF_REG_SDRAM_DRIVE_SHIFT 18 |
| 66 | #define EMIF_REG_SDRAM_DRIVE_MASK (0x3 << 18) |
| 67 | #define EMIF_REG_CWL_SHIFT 16 |
| 68 | #define EMIF_REG_CWL_MASK (0x3 << 16) |
| 69 | #define EMIF_REG_NARROW_MODE_SHIFT 14 |
| 70 | #define EMIF_REG_NARROW_MODE_MASK (0x3 << 14) |
| 71 | #define EMIF_REG_CL_SHIFT 10 |
| 72 | #define EMIF_REG_CL_MASK (0xf << 10) |
| 73 | #define EMIF_REG_ROWSIZE_SHIFT 7 |
| 74 | #define EMIF_REG_ROWSIZE_MASK (0x7 << 7) |
| 75 | #define EMIF_REG_IBANK_SHIFT 4 |
| 76 | #define EMIF_REG_IBANK_MASK (0x7 << 4) |
| 77 | #define EMIF_REG_EBANK_SHIFT 3 |
| 78 | #define EMIF_REG_EBANK_MASK (1 << 3) |
| 79 | #define EMIF_REG_PAGESIZE_SHIFT 0 |
| 80 | #define EMIF_REG_PAGESIZE_MASK (0x7 << 0) |
| 81 | |
| 82 | /* SDRAM_CONFIG_2 */ |
| 83 | #define EMIF_REG_CS1NVMEN_SHIFT 30 |
| 84 | #define EMIF_REG_CS1NVMEN_MASK (1 << 30) |
| 85 | #define EMIF_REG_EBANK_POS_SHIFT 27 |
| 86 | #define EMIF_REG_EBANK_POS_MASK (1 << 27) |
| 87 | #define EMIF_REG_RDBNUM_SHIFT 4 |
| 88 | #define EMIF_REG_RDBNUM_MASK (0x3 << 4) |
| 89 | #define EMIF_REG_RDBSIZE_SHIFT 0 |
| 90 | #define EMIF_REG_RDBSIZE_MASK (0x7 << 0) |
| 91 | |
| 92 | /* SDRAM_REF_CTRL */ |
| 93 | #define EMIF_REG_INITREF_DIS_SHIFT 31 |
| 94 | #define EMIF_REG_INITREF_DIS_MASK (1 << 31) |
| 95 | #define EMIF_REG_SRT_SHIFT 29 |
| 96 | #define EMIF_REG_SRT_MASK (1 << 29) |
| 97 | #define EMIF_REG_ASR_SHIFT 28 |
| 98 | #define EMIF_REG_ASR_MASK (1 << 28) |
| 99 | #define EMIF_REG_PASR_SHIFT 24 |
| 100 | #define EMIF_REG_PASR_MASK (0x7 << 24) |
| 101 | #define EMIF_REG_REFRESH_RATE_SHIFT 0 |
| 102 | #define EMIF_REG_REFRESH_RATE_MASK (0xffff << 0) |
| 103 | |
| 104 | /* SDRAM_REF_CTRL_SHDW */ |
| 105 | #define EMIF_REG_REFRESH_RATE_SHDW_SHIFT 0 |
| 106 | #define EMIF_REG_REFRESH_RATE_SHDW_MASK (0xffff << 0) |
| 107 | |
| 108 | /* SDRAM_TIM_1 */ |
| 109 | #define EMIF_REG_T_RP_SHIFT 25 |
| 110 | #define EMIF_REG_T_RP_MASK (0xf << 25) |
| 111 | #define EMIF_REG_T_RCD_SHIFT 21 |
| 112 | #define EMIF_REG_T_RCD_MASK (0xf << 21) |
| 113 | #define EMIF_REG_T_WR_SHIFT 17 |
| 114 | #define EMIF_REG_T_WR_MASK (0xf << 17) |
| 115 | #define EMIF_REG_T_RAS_SHIFT 12 |
| 116 | #define EMIF_REG_T_RAS_MASK (0x1f << 12) |
| 117 | #define EMIF_REG_T_RC_SHIFT 6 |
| 118 | #define EMIF_REG_T_RC_MASK (0x3f << 6) |
| 119 | #define EMIF_REG_T_RRD_SHIFT 3 |
| 120 | #define EMIF_REG_T_RRD_MASK (0x7 << 3) |
| 121 | #define EMIF_REG_T_WTR_SHIFT 0 |
| 122 | #define EMIF_REG_T_WTR_MASK (0x7 << 0) |
| 123 | |
| 124 | /* SDRAM_TIM_1_SHDW */ |
| 125 | #define EMIF_REG_T_RP_SHDW_SHIFT 25 |
| 126 | #define EMIF_REG_T_RP_SHDW_MASK (0xf << 25) |
| 127 | #define EMIF_REG_T_RCD_SHDW_SHIFT 21 |
| 128 | #define EMIF_REG_T_RCD_SHDW_MASK (0xf << 21) |
| 129 | #define EMIF_REG_T_WR_SHDW_SHIFT 17 |
| 130 | #define EMIF_REG_T_WR_SHDW_MASK (0xf << 17) |
| 131 | #define EMIF_REG_T_RAS_SHDW_SHIFT 12 |
| 132 | #define EMIF_REG_T_RAS_SHDW_MASK (0x1f << 12) |
| 133 | #define EMIF_REG_T_RC_SHDW_SHIFT 6 |
| 134 | #define EMIF_REG_T_RC_SHDW_MASK (0x3f << 6) |
| 135 | #define EMIF_REG_T_RRD_SHDW_SHIFT 3 |
| 136 | #define EMIF_REG_T_RRD_SHDW_MASK (0x7 << 3) |
| 137 | #define EMIF_REG_T_WTR_SHDW_SHIFT 0 |
| 138 | #define EMIF_REG_T_WTR_SHDW_MASK (0x7 << 0) |
| 139 | |
| 140 | /* SDRAM_TIM_2 */ |
| 141 | #define EMIF_REG_T_XP_SHIFT 28 |
| 142 | #define EMIF_REG_T_XP_MASK (0x7 << 28) |
| 143 | #define EMIF_REG_T_ODT_SHIFT 25 |
| 144 | #define EMIF_REG_T_ODT_MASK (0x7 << 25) |
| 145 | #define EMIF_REG_T_XSNR_SHIFT 16 |
| 146 | #define EMIF_REG_T_XSNR_MASK (0x1ff << 16) |
| 147 | #define EMIF_REG_T_XSRD_SHIFT 6 |
| 148 | #define EMIF_REG_T_XSRD_MASK (0x3ff << 6) |
| 149 | #define EMIF_REG_T_RTP_SHIFT 3 |
| 150 | #define EMIF_REG_T_RTP_MASK (0x7 << 3) |
| 151 | #define EMIF_REG_T_CKE_SHIFT 0 |
| 152 | #define EMIF_REG_T_CKE_MASK (0x7 << 0) |
| 153 | |
| 154 | /* SDRAM_TIM_2_SHDW */ |
| 155 | #define EMIF_REG_T_XP_SHDW_SHIFT 28 |
| 156 | #define EMIF_REG_T_XP_SHDW_MASK (0x7 << 28) |
| 157 | #define EMIF_REG_T_ODT_SHDW_SHIFT 25 |
| 158 | #define EMIF_REG_T_ODT_SHDW_MASK (0x7 << 25) |
| 159 | #define EMIF_REG_T_XSNR_SHDW_SHIFT 16 |
| 160 | #define EMIF_REG_T_XSNR_SHDW_MASK (0x1ff << 16) |
| 161 | #define EMIF_REG_T_XSRD_SHDW_SHIFT 6 |
| 162 | #define EMIF_REG_T_XSRD_SHDW_MASK (0x3ff << 6) |
| 163 | #define EMIF_REG_T_RTP_SHDW_SHIFT 3 |
| 164 | #define EMIF_REG_T_RTP_SHDW_MASK (0x7 << 3) |
| 165 | #define EMIF_REG_T_CKE_SHDW_SHIFT 0 |
| 166 | #define EMIF_REG_T_CKE_SHDW_MASK (0x7 << 0) |
| 167 | |
| 168 | /* SDRAM_TIM_3 */ |
| 169 | #define EMIF_REG_T_CKESR_SHIFT 21 |
| 170 | #define EMIF_REG_T_CKESR_MASK (0x7 << 21) |
| 171 | #define EMIF_REG_ZQ_ZQCS_SHIFT 15 |
| 172 | #define EMIF_REG_ZQ_ZQCS_MASK (0x3f << 15) |
| 173 | #define EMIF_REG_T_TDQSCKMAX_SHIFT 13 |
| 174 | #define EMIF_REG_T_TDQSCKMAX_MASK (0x3 << 13) |
| 175 | #define EMIF_REG_T_RFC_SHIFT 4 |
| 176 | #define EMIF_REG_T_RFC_MASK (0x1ff << 4) |
| 177 | #define EMIF_REG_T_RAS_MAX_SHIFT 0 |
| 178 | #define EMIF_REG_T_RAS_MAX_MASK (0xf << 0) |
| 179 | |
| 180 | /* SDRAM_TIM_3_SHDW */ |
| 181 | #define EMIF_REG_T_CKESR_SHDW_SHIFT 21 |
| 182 | #define EMIF_REG_T_CKESR_SHDW_MASK (0x7 << 21) |
| 183 | #define EMIF_REG_ZQ_ZQCS_SHDW_SHIFT 15 |
| 184 | #define EMIF_REG_ZQ_ZQCS_SHDW_MASK (0x3f << 15) |
| 185 | #define EMIF_REG_T_TDQSCKMAX_SHDW_SHIFT 13 |
| 186 | #define EMIF_REG_T_TDQSCKMAX_SHDW_MASK (0x3 << 13) |
| 187 | #define EMIF_REG_T_RFC_SHDW_SHIFT 4 |
| 188 | #define EMIF_REG_T_RFC_SHDW_MASK (0x1ff << 4) |
| 189 | #define EMIF_REG_T_RAS_MAX_SHDW_SHIFT 0 |
| 190 | #define EMIF_REG_T_RAS_MAX_SHDW_MASK (0xf << 0) |
| 191 | |
| 192 | /* LPDDR2_NVM_TIM */ |
| 193 | #define EMIF_REG_NVM_T_XP_SHIFT 28 |
| 194 | #define EMIF_REG_NVM_T_XP_MASK (0x7 << 28) |
| 195 | #define EMIF_REG_NVM_T_WTR_SHIFT 24 |
| 196 | #define EMIF_REG_NVM_T_WTR_MASK (0x7 << 24) |
| 197 | #define EMIF_REG_NVM_T_RP_SHIFT 20 |
| 198 | #define EMIF_REG_NVM_T_RP_MASK (0xf << 20) |
| 199 | #define EMIF_REG_NVM_T_WRA_SHIFT 16 |
| 200 | #define EMIF_REG_NVM_T_WRA_MASK (0xf << 16) |
| 201 | #define EMIF_REG_NVM_T_RRD_SHIFT 8 |
| 202 | #define EMIF_REG_NVM_T_RRD_MASK (0xff << 8) |
| 203 | #define EMIF_REG_NVM_T_RCDMIN_SHIFT 0 |
| 204 | #define EMIF_REG_NVM_T_RCDMIN_MASK (0xff << 0) |
| 205 | |
| 206 | /* LPDDR2_NVM_TIM_SHDW */ |
| 207 | #define EMIF_REG_NVM_T_XP_SHDW_SHIFT 28 |
| 208 | #define EMIF_REG_NVM_T_XP_SHDW_MASK (0x7 << 28) |
| 209 | #define EMIF_REG_NVM_T_WTR_SHDW_SHIFT 24 |
| 210 | #define EMIF_REG_NVM_T_WTR_SHDW_MASK (0x7 << 24) |
| 211 | #define EMIF_REG_NVM_T_RP_SHDW_SHIFT 20 |
| 212 | #define EMIF_REG_NVM_T_RP_SHDW_MASK (0xf << 20) |
| 213 | #define EMIF_REG_NVM_T_WRA_SHDW_SHIFT 16 |
| 214 | #define EMIF_REG_NVM_T_WRA_SHDW_MASK (0xf << 16) |
| 215 | #define EMIF_REG_NVM_T_RRD_SHDW_SHIFT 8 |
| 216 | #define EMIF_REG_NVM_T_RRD_SHDW_MASK (0xff << 8) |
| 217 | #define EMIF_REG_NVM_T_RCDMIN_SHDW_SHIFT 0 |
| 218 | #define EMIF_REG_NVM_T_RCDMIN_SHDW_MASK (0xff << 0) |
| 219 | |
| 220 | /* PWR_MGMT_CTRL */ |
| 221 | #define EMIF_REG_IDLEMODE_SHIFT 30 |
| 222 | #define EMIF_REG_IDLEMODE_MASK (0x3 << 30) |
| 223 | #define EMIF_REG_PD_TIM_SHIFT 12 |
| 224 | #define EMIF_REG_PD_TIM_MASK (0xf << 12) |
| 225 | #define EMIF_REG_DPD_EN_SHIFT 11 |
| 226 | #define EMIF_REG_DPD_EN_MASK (1 << 11) |
| 227 | #define EMIF_REG_LP_MODE_SHIFT 8 |
| 228 | #define EMIF_REG_LP_MODE_MASK (0x7 << 8) |
| 229 | #define EMIF_REG_SR_TIM_SHIFT 4 |
| 230 | #define EMIF_REG_SR_TIM_MASK (0xf << 4) |
| 231 | #define EMIF_REG_CS_TIM_SHIFT 0 |
| 232 | #define EMIF_REG_CS_TIM_MASK (0xf << 0) |
| 233 | |
| 234 | /* PWR_MGMT_CTRL_SHDW */ |
SRICHARAN R | 7d8e96a | 2012-03-12 02:25:46 +0000 | [diff] [blame] | 235 | #define EMIF_REG_PD_TIM_SHDW_SHIFT 12 |
| 236 | #define EMIF_REG_PD_TIM_SHDW_MASK (0xf << 12) |
Sricharan | 62a8650 | 2011-11-15 09:50:00 -0500 | [diff] [blame] | 237 | #define EMIF_REG_SR_TIM_SHDW_SHIFT 4 |
| 238 | #define EMIF_REG_SR_TIM_SHDW_MASK (0xf << 4) |
| 239 | #define EMIF_REG_CS_TIM_SHDW_SHIFT 0 |
| 240 | #define EMIF_REG_CS_TIM_SHDW_MASK (0xf << 0) |
| 241 | |
| 242 | /* LPDDR2_MODE_REG_DATA */ |
| 243 | #define EMIF_REG_VALUE_0_SHIFT 0 |
| 244 | #define EMIF_REG_VALUE_0_MASK (0x7f << 0) |
| 245 | |
| 246 | /* LPDDR2_MODE_REG_CFG */ |
| 247 | #define EMIF_REG_CS_SHIFT 31 |
| 248 | #define EMIF_REG_CS_MASK (1 << 31) |
| 249 | #define EMIF_REG_REFRESH_EN_SHIFT 30 |
| 250 | #define EMIF_REG_REFRESH_EN_MASK (1 << 30) |
| 251 | #define EMIF_REG_ADDRESS_SHIFT 0 |
| 252 | #define EMIF_REG_ADDRESS_MASK (0xff << 0) |
| 253 | |
| 254 | /* OCP_CONFIG */ |
| 255 | #define EMIF_REG_SYS_THRESH_MAX_SHIFT 24 |
| 256 | #define EMIF_REG_SYS_THRESH_MAX_MASK (0xf << 24) |
| 257 | #define EMIF_REG_MPU_THRESH_MAX_SHIFT 20 |
| 258 | #define EMIF_REG_MPU_THRESH_MAX_MASK (0xf << 20) |
| 259 | #define EMIF_REG_LL_THRESH_MAX_SHIFT 16 |
| 260 | #define EMIF_REG_LL_THRESH_MAX_MASK (0xf << 16) |
| 261 | #define EMIF_REG_PR_OLD_COUNT_SHIFT 0 |
| 262 | #define EMIF_REG_PR_OLD_COUNT_MASK (0xff << 0) |
| 263 | |
| 264 | /* OCP_CFG_VAL_1 */ |
| 265 | #define EMIF_REG_SYS_BUS_WIDTH_SHIFT 30 |
| 266 | #define EMIF_REG_SYS_BUS_WIDTH_MASK (0x3 << 30) |
| 267 | #define EMIF_REG_LL_BUS_WIDTH_SHIFT 28 |
| 268 | #define EMIF_REG_LL_BUS_WIDTH_MASK (0x3 << 28) |
| 269 | #define EMIF_REG_WR_FIFO_DEPTH_SHIFT 8 |
| 270 | #define EMIF_REG_WR_FIFO_DEPTH_MASK (0xff << 8) |
| 271 | #define EMIF_REG_CMD_FIFO_DEPTH_SHIFT 0 |
| 272 | #define EMIF_REG_CMD_FIFO_DEPTH_MASK (0xff << 0) |
| 273 | |
| 274 | /* OCP_CFG_VAL_2 */ |
| 275 | #define EMIF_REG_RREG_FIFO_DEPTH_SHIFT 16 |
| 276 | #define EMIF_REG_RREG_FIFO_DEPTH_MASK (0xff << 16) |
| 277 | #define EMIF_REG_RSD_FIFO_DEPTH_SHIFT 8 |
| 278 | #define EMIF_REG_RSD_FIFO_DEPTH_MASK (0xff << 8) |
| 279 | #define EMIF_REG_RCMD_FIFO_DEPTH_SHIFT 0 |
| 280 | #define EMIF_REG_RCMD_FIFO_DEPTH_MASK (0xff << 0) |
| 281 | |
| 282 | /* IODFT_TLGC */ |
| 283 | #define EMIF_REG_TLEC_SHIFT 16 |
| 284 | #define EMIF_REG_TLEC_MASK (0xffff << 16) |
| 285 | #define EMIF_REG_MT_SHIFT 14 |
| 286 | #define EMIF_REG_MT_MASK (1 << 14) |
| 287 | #define EMIF_REG_ACT_CAP_EN_SHIFT 13 |
| 288 | #define EMIF_REG_ACT_CAP_EN_MASK (1 << 13) |
| 289 | #define EMIF_REG_OPG_LD_SHIFT 12 |
| 290 | #define EMIF_REG_OPG_LD_MASK (1 << 12) |
| 291 | #define EMIF_REG_RESET_PHY_SHIFT 10 |
| 292 | #define EMIF_REG_RESET_PHY_MASK (1 << 10) |
| 293 | #define EMIF_REG_MMS_SHIFT 8 |
| 294 | #define EMIF_REG_MMS_MASK (1 << 8) |
| 295 | #define EMIF_REG_MC_SHIFT 4 |
| 296 | #define EMIF_REG_MC_MASK (0x3 << 4) |
| 297 | #define EMIF_REG_PC_SHIFT 1 |
| 298 | #define EMIF_REG_PC_MASK (0x7 << 1) |
| 299 | #define EMIF_REG_TM_SHIFT 0 |
| 300 | #define EMIF_REG_TM_MASK (1 << 0) |
| 301 | |
| 302 | /* IODFT_CTRL_MISR_RSLT */ |
| 303 | #define EMIF_REG_DQM_TLMR_SHIFT 16 |
| 304 | #define EMIF_REG_DQM_TLMR_MASK (0x3ff << 16) |
| 305 | #define EMIF_REG_CTL_TLMR_SHIFT 0 |
| 306 | #define EMIF_REG_CTL_TLMR_MASK (0x7ff << 0) |
| 307 | |
| 308 | /* IODFT_ADDR_MISR_RSLT */ |
| 309 | #define EMIF_REG_ADDR_TLMR_SHIFT 0 |
| 310 | #define EMIF_REG_ADDR_TLMR_MASK (0x1fffff << 0) |
| 311 | |
| 312 | /* IODFT_DATA_MISR_RSLT_1 */ |
| 313 | #define EMIF_REG_DATA_TLMR_31_0_SHIFT 0 |
| 314 | #define EMIF_REG_DATA_TLMR_31_0_MASK (0xffffffff << 0) |
| 315 | |
| 316 | /* IODFT_DATA_MISR_RSLT_2 */ |
| 317 | #define EMIF_REG_DATA_TLMR_63_32_SHIFT 0 |
| 318 | #define EMIF_REG_DATA_TLMR_63_32_MASK (0xffffffff << 0) |
| 319 | |
| 320 | /* IODFT_DATA_MISR_RSLT_3 */ |
| 321 | #define EMIF_REG_DATA_TLMR_66_64_SHIFT 0 |
| 322 | #define EMIF_REG_DATA_TLMR_66_64_MASK (0x7 << 0) |
| 323 | |
| 324 | /* PERF_CNT_1 */ |
| 325 | #define EMIF_REG_COUNTER1_SHIFT 0 |
| 326 | #define EMIF_REG_COUNTER1_MASK (0xffffffff << 0) |
| 327 | |
| 328 | /* PERF_CNT_2 */ |
| 329 | #define EMIF_REG_COUNTER2_SHIFT 0 |
| 330 | #define EMIF_REG_COUNTER2_MASK (0xffffffff << 0) |
| 331 | |
| 332 | /* PERF_CNT_CFG */ |
| 333 | #define EMIF_REG_CNTR2_MCONNID_EN_SHIFT 31 |
| 334 | #define EMIF_REG_CNTR2_MCONNID_EN_MASK (1 << 31) |
| 335 | #define EMIF_REG_CNTR2_REGION_EN_SHIFT 30 |
| 336 | #define EMIF_REG_CNTR2_REGION_EN_MASK (1 << 30) |
| 337 | #define EMIF_REG_CNTR2_CFG_SHIFT 16 |
| 338 | #define EMIF_REG_CNTR2_CFG_MASK (0xf << 16) |
| 339 | #define EMIF_REG_CNTR1_MCONNID_EN_SHIFT 15 |
| 340 | #define EMIF_REG_CNTR1_MCONNID_EN_MASK (1 << 15) |
| 341 | #define EMIF_REG_CNTR1_REGION_EN_SHIFT 14 |
| 342 | #define EMIF_REG_CNTR1_REGION_EN_MASK (1 << 14) |
| 343 | #define EMIF_REG_CNTR1_CFG_SHIFT 0 |
| 344 | #define EMIF_REG_CNTR1_CFG_MASK (0xf << 0) |
| 345 | |
| 346 | /* PERF_CNT_SEL */ |
| 347 | #define EMIF_REG_MCONNID2_SHIFT 24 |
| 348 | #define EMIF_REG_MCONNID2_MASK (0xff << 24) |
| 349 | #define EMIF_REG_REGION_SEL2_SHIFT 16 |
| 350 | #define EMIF_REG_REGION_SEL2_MASK (0x3 << 16) |
| 351 | #define EMIF_REG_MCONNID1_SHIFT 8 |
| 352 | #define EMIF_REG_MCONNID1_MASK (0xff << 8) |
| 353 | #define EMIF_REG_REGION_SEL1_SHIFT 0 |
| 354 | #define EMIF_REG_REGION_SEL1_MASK (0x3 << 0) |
| 355 | |
| 356 | /* PERF_CNT_TIM */ |
| 357 | #define EMIF_REG_TOTAL_TIME_SHIFT 0 |
| 358 | #define EMIF_REG_TOTAL_TIME_MASK (0xffffffff << 0) |
| 359 | |
| 360 | /* READ_IDLE_CTRL */ |
| 361 | #define EMIF_REG_READ_IDLE_LEN_SHIFT 16 |
| 362 | #define EMIF_REG_READ_IDLE_LEN_MASK (0xf << 16) |
| 363 | #define EMIF_REG_READ_IDLE_INTERVAL_SHIFT 0 |
| 364 | #define EMIF_REG_READ_IDLE_INTERVAL_MASK (0x1ff << 0) |
| 365 | |
| 366 | /* READ_IDLE_CTRL_SHDW */ |
| 367 | #define EMIF_REG_READ_IDLE_LEN_SHDW_SHIFT 16 |
| 368 | #define EMIF_REG_READ_IDLE_LEN_SHDW_MASK (0xf << 16) |
| 369 | #define EMIF_REG_READ_IDLE_INTERVAL_SHDW_SHIFT 0 |
| 370 | #define EMIF_REG_READ_IDLE_INTERVAL_SHDW_MASK (0x1ff << 0) |
| 371 | |
| 372 | /* IRQ_EOI */ |
| 373 | #define EMIF_REG_EOI_SHIFT 0 |
| 374 | #define EMIF_REG_EOI_MASK (1 << 0) |
| 375 | |
| 376 | /* IRQSTATUS_RAW_SYS */ |
| 377 | #define EMIF_REG_DNV_SYS_SHIFT 2 |
| 378 | #define EMIF_REG_DNV_SYS_MASK (1 << 2) |
| 379 | #define EMIF_REG_TA_SYS_SHIFT 1 |
| 380 | #define EMIF_REG_TA_SYS_MASK (1 << 1) |
| 381 | #define EMIF_REG_ERR_SYS_SHIFT 0 |
| 382 | #define EMIF_REG_ERR_SYS_MASK (1 << 0) |
| 383 | |
| 384 | /* IRQSTATUS_RAW_LL */ |
| 385 | #define EMIF_REG_DNV_LL_SHIFT 2 |
| 386 | #define EMIF_REG_DNV_LL_MASK (1 << 2) |
| 387 | #define EMIF_REG_TA_LL_SHIFT 1 |
| 388 | #define EMIF_REG_TA_LL_MASK (1 << 1) |
| 389 | #define EMIF_REG_ERR_LL_SHIFT 0 |
| 390 | #define EMIF_REG_ERR_LL_MASK (1 << 0) |
| 391 | |
| 392 | /* IRQSTATUS_SYS */ |
| 393 | |
| 394 | /* IRQSTATUS_LL */ |
| 395 | |
| 396 | /* IRQENABLE_SET_SYS */ |
| 397 | #define EMIF_REG_EN_DNV_SYS_SHIFT 2 |
| 398 | #define EMIF_REG_EN_DNV_SYS_MASK (1 << 2) |
| 399 | #define EMIF_REG_EN_TA_SYS_SHIFT 1 |
| 400 | #define EMIF_REG_EN_TA_SYS_MASK (1 << 1) |
| 401 | #define EMIF_REG_EN_ERR_SYS_SHIFT 0 |
| 402 | #define EMIF_REG_EN_ERR_SYS_MASK (1 << 0) |
| 403 | |
| 404 | /* IRQENABLE_SET_LL */ |
| 405 | #define EMIF_REG_EN_DNV_LL_SHIFT 2 |
| 406 | #define EMIF_REG_EN_DNV_LL_MASK (1 << 2) |
| 407 | #define EMIF_REG_EN_TA_LL_SHIFT 1 |
| 408 | #define EMIF_REG_EN_TA_LL_MASK (1 << 1) |
| 409 | #define EMIF_REG_EN_ERR_LL_SHIFT 0 |
| 410 | #define EMIF_REG_EN_ERR_LL_MASK (1 << 0) |
| 411 | |
| 412 | /* IRQENABLE_CLR_SYS */ |
| 413 | |
| 414 | /* IRQENABLE_CLR_LL */ |
| 415 | |
| 416 | /* ZQ_CONFIG */ |
| 417 | #define EMIF_REG_ZQ_CS1EN_SHIFT 31 |
| 418 | #define EMIF_REG_ZQ_CS1EN_MASK (1 << 31) |
| 419 | #define EMIF_REG_ZQ_CS0EN_SHIFT 30 |
| 420 | #define EMIF_REG_ZQ_CS0EN_MASK (1 << 30) |
| 421 | #define EMIF_REG_ZQ_DUALCALEN_SHIFT 29 |
| 422 | #define EMIF_REG_ZQ_DUALCALEN_MASK (1 << 29) |
| 423 | #define EMIF_REG_ZQ_SFEXITEN_SHIFT 28 |
| 424 | #define EMIF_REG_ZQ_SFEXITEN_MASK (1 << 28) |
| 425 | #define EMIF_REG_ZQ_ZQINIT_MULT_SHIFT 18 |
| 426 | #define EMIF_REG_ZQ_ZQINIT_MULT_MASK (0x3 << 18) |
| 427 | #define EMIF_REG_ZQ_ZQCL_MULT_SHIFT 16 |
| 428 | #define EMIF_REG_ZQ_ZQCL_MULT_MASK (0x3 << 16) |
| 429 | #define EMIF_REG_ZQ_REFINTERVAL_SHIFT 0 |
| 430 | #define EMIF_REG_ZQ_REFINTERVAL_MASK (0xffff << 0) |
| 431 | |
| 432 | /* TEMP_ALERT_CONFIG */ |
| 433 | #define EMIF_REG_TA_CS1EN_SHIFT 31 |
| 434 | #define EMIF_REG_TA_CS1EN_MASK (1 << 31) |
| 435 | #define EMIF_REG_TA_CS0EN_SHIFT 30 |
| 436 | #define EMIF_REG_TA_CS0EN_MASK (1 << 30) |
| 437 | #define EMIF_REG_TA_SFEXITEN_SHIFT 28 |
| 438 | #define EMIF_REG_TA_SFEXITEN_MASK (1 << 28) |
| 439 | #define EMIF_REG_TA_DEVWDT_SHIFT 26 |
| 440 | #define EMIF_REG_TA_DEVWDT_MASK (0x3 << 26) |
| 441 | #define EMIF_REG_TA_DEVCNT_SHIFT 24 |
| 442 | #define EMIF_REG_TA_DEVCNT_MASK (0x3 << 24) |
| 443 | #define EMIF_REG_TA_REFINTERVAL_SHIFT 0 |
| 444 | #define EMIF_REG_TA_REFINTERVAL_MASK (0x3fffff << 0) |
| 445 | |
| 446 | /* OCP_ERR_LOG */ |
| 447 | #define EMIF_REG_MADDRSPACE_SHIFT 14 |
| 448 | #define EMIF_REG_MADDRSPACE_MASK (0x3 << 14) |
| 449 | #define EMIF_REG_MBURSTSEQ_SHIFT 11 |
| 450 | #define EMIF_REG_MBURSTSEQ_MASK (0x7 << 11) |
| 451 | #define EMIF_REG_MCMD_SHIFT 8 |
| 452 | #define EMIF_REG_MCMD_MASK (0x7 << 8) |
| 453 | #define EMIF_REG_MCONNID_SHIFT 0 |
| 454 | #define EMIF_REG_MCONNID_MASK (0xff << 0) |
| 455 | |
| 456 | /* DDR_PHY_CTRL_1 */ |
| 457 | #define EMIF_REG_DDR_PHY_CTRL_1_SHIFT 4 |
| 458 | #define EMIF_REG_DDR_PHY_CTRL_1_MASK (0xfffffff << 4) |
| 459 | #define EMIF_REG_READ_LATENCY_SHIFT 0 |
| 460 | #define EMIF_REG_READ_LATENCY_MASK (0xf << 0) |
| 461 | #define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT 4 |
| 462 | #define EMIF_REG_DLL_SLAVE_DLY_CTRL_MASK (0xFF << 4) |
| 463 | #define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT 12 |
| 464 | #define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_MASK (0xFFFFF << 12) |
| 465 | |
| 466 | /* DDR_PHY_CTRL_1_SHDW */ |
| 467 | #define EMIF_REG_DDR_PHY_CTRL_1_SHDW_SHIFT 4 |
| 468 | #define EMIF_REG_DDR_PHY_CTRL_1_SHDW_MASK (0xfffffff << 4) |
| 469 | #define EMIF_REG_READ_LATENCY_SHDW_SHIFT 0 |
| 470 | #define EMIF_REG_READ_LATENCY_SHDW_MASK (0xf << 0) |
| 471 | #define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHDW_SHIFT 4 |
| 472 | #define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHDW_MASK (0xFF << 4) |
| 473 | #define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_SHIFT 12 |
| 474 | #define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_MASK (0xFFFFF << 12) |
| 475 | |
| 476 | /* DDR_PHY_CTRL_2 */ |
| 477 | #define EMIF_REG_DDR_PHY_CTRL_2_SHIFT 0 |
| 478 | #define EMIF_REG_DDR_PHY_CTRL_2_MASK (0xffffffff << 0) |
| 479 | |
Lokesh Vutla | 0f42de6 | 2012-05-22 00:03:25 +0000 | [diff] [blame] | 480 | /*EMIF_READ_WRITE_LEVELING_CONTROL*/ |
| 481 | #define EMIF_REG_RDWRLVLFULL_START_SHIFT 31 |
| 482 | #define EMIF_REG_RDWRLVLFULL_START_MASK (1 << 31) |
| 483 | #define EMIF_REG_RDWRLVLINC_PRE_SHIFT 24 |
| 484 | #define EMIF_REG_RDWRLVLINC_PRE_MASK (0x7F << 24) |
| 485 | #define EMIF_REG_RDLVLINC_INT_SHIFT 16 |
| 486 | #define EMIF_REG_RDLVLINC_INT_MASK (0xFF << 16) |
| 487 | #define EMIF_REG_RDLVLGATEINC_INT_SHIFT 8 |
| 488 | #define EMIF_REG_RDLVLGATEINC_INT_MASK (0xFF << 8) |
| 489 | #define EMIF_REG_WRLVLINC_INT_SHIFT 0 |
| 490 | #define EMIF_REG_WRLVLINC_INT_MASK (0xFF << 0) |
| 491 | |
| 492 | /*EMIF_READ_WRITE_LEVELING_RAMP_CONTROL*/ |
| 493 | #define EMIF_REG_RDWRLVL_EN_SHIFT 31 |
| 494 | #define EMIF_REG_RDWRLVL_EN_MASK (1 << 31) |
| 495 | #define EMIF_REG_RDWRLVLINC_RMP_PRE_SHIFT 24 |
| 496 | #define EMIF_REG_RDWRLVLINC_RMP_PRE_MASK (0x7F << 24) |
| 497 | #define EMIF_REG_RDLVLINC_RMP_INT_SHIFT 16 |
| 498 | #define EMIF_REG_RDLVLINC_RMP_INT_MASK (0xFF << 16) |
| 499 | #define EMIF_REG_RDLVLGATEINC_RMP_INT_SHIFT 8 |
| 500 | #define EMIF_REG_RDLVLGATEINC_RMP_INT_MASK (0xFF << 8) |
| 501 | #define EMIF_REG_WRLVLINC_RMP_INT_SHIFT 0 |
| 502 | #define EMIF_REG_WRLVLINC_RMP_INT_MASK (0xFF << 0) |
| 503 | |
| 504 | /*EMIF_READ_WRITE_LEVELING_RAMP_WINDOW*/ |
| 505 | #define EMIF_REG_RDWRLVLINC_RMP_WIN_SHIFT 0 |
| 506 | #define EMIF_REG_RDWRLVLINC_RMP_WIN_MASK (0x1FFF << 0) |
| 507 | |
| 508 | /*Leveling Fields */ |
| 509 | #define DDR3_WR_LVL_INT 0x73 |
| 510 | #define DDR3_RD_LVL_INT 0x33 |
| 511 | #define DDR3_RD_LVL_GATE_INT 0x59 |
| 512 | #define RD_RW_LVL_INC_PRE 0x0 |
| 513 | #define DDR3_FULL_LVL (1 << EMIF_REG_RDWRLVL_EN_SHIFT) |
| 514 | |
| 515 | #define DDR3_INC_LVL ((DDR3_WR_LVL_INT << EMIF_REG_WRLVLINC_INT_SHIFT) \ |
| 516 | | (DDR3_RD_LVL_GATE_INT << EMIF_REG_RDLVLGATEINC_INT_SHIFT) \ |
| 517 | | (DDR3_RD_LVL_INT << EMIF_REG_RDLVLINC_RMP_INT_SHIFT) \ |
| 518 | | (RD_RW_LVL_INC_PRE << EMIF_REG_RDWRLVLINC_RMP_PRE_SHIFT)) |
| 519 | |
| 520 | #define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES 0x0000C1A7 |
| 521 | #define SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES 0x000001A7 |
| 522 | |
Sricharan | 62a8650 | 2011-11-15 09:50:00 -0500 | [diff] [blame] | 523 | /* DMM */ |
| 524 | #define DMM_BASE 0x4E000040 |
| 525 | |
| 526 | /* Memory Adapter */ |
| 527 | #define MA_BASE 0x482AF040 |
| 528 | |
| 529 | /* DMM_LISA_MAP */ |
| 530 | #define EMIF_SYS_ADDR_SHIFT 24 |
| 531 | #define EMIF_SYS_ADDR_MASK (0xff << 24) |
| 532 | #define EMIF_SYS_SIZE_SHIFT 20 |
| 533 | #define EMIF_SYS_SIZE_MASK (0x7 << 20) |
| 534 | #define EMIF_SDRC_INTL_SHIFT 18 |
| 535 | #define EMIF_SDRC_INTL_MASK (0x3 << 18) |
| 536 | #define EMIF_SDRC_ADDRSPC_SHIFT 16 |
| 537 | #define EMIF_SDRC_ADDRSPC_MASK (0x3 << 16) |
| 538 | #define EMIF_SDRC_MAP_SHIFT 8 |
| 539 | #define EMIF_SDRC_MAP_MASK (0x3 << 8) |
| 540 | #define EMIF_SDRC_ADDR_SHIFT 0 |
| 541 | #define EMIF_SDRC_ADDR_MASK (0xff << 0) |
| 542 | |
| 543 | /* DMM_LISA_MAP fields */ |
| 544 | #define DMM_SDRC_MAP_UNMAPPED 0 |
| 545 | #define DMM_SDRC_MAP_EMIF1_ONLY 1 |
| 546 | #define DMM_SDRC_MAP_EMIF2_ONLY 2 |
| 547 | #define DMM_SDRC_MAP_EMIF1_AND_EMIF2 3 |
| 548 | |
| 549 | #define DMM_SDRC_INTL_NONE 0 |
| 550 | #define DMM_SDRC_INTL_128B 1 |
| 551 | #define DMM_SDRC_INTL_256B 2 |
| 552 | #define DMM_SDRC_INTL_512 3 |
| 553 | |
| 554 | #define DMM_SDRC_ADDR_SPC_SDRAM 0 |
| 555 | #define DMM_SDRC_ADDR_SPC_NVM 1 |
| 556 | #define DMM_SDRC_ADDR_SPC_INVALID 2 |
| 557 | |
| 558 | #define DMM_LISA_MAP_INTERLEAVED_BASE_VAL (\ |
| 559 | (DMM_SDRC_MAP_EMIF1_AND_EMIF2 << EMIF_SDRC_MAP_SHIFT) |\ |
| 560 | (DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT) |\ |
| 561 | (DMM_SDRC_INTL_128B << EMIF_SDRC_INTL_SHIFT) |\ |
| 562 | (CONFIG_SYS_SDRAM_BASE << EMIF_SYS_ADDR_SHIFT)) |
| 563 | |
| 564 | #define DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL (\ |
| 565 | (DMM_SDRC_MAP_EMIF1_ONLY << EMIF_SDRC_MAP_SHIFT)|\ |
| 566 | (DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT)|\ |
| 567 | (DMM_SDRC_INTL_NONE << EMIF_SDRC_INTL_SHIFT)) |
| 568 | |
| 569 | #define DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL (\ |
| 570 | (DMM_SDRC_MAP_EMIF2_ONLY << EMIF_SDRC_MAP_SHIFT)|\ |
| 571 | (DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT)|\ |
| 572 | (DMM_SDRC_INTL_NONE << EMIF_SDRC_INTL_SHIFT)) |
| 573 | |
| 574 | /* Trap for invalid TILER PAT entries */ |
| 575 | #define DMM_LISA_MAP_0_INVAL_ADDR_TRAP (\ |
| 576 | (0 << EMIF_SDRC_ADDR_SHIFT) |\ |
| 577 | (DMM_SDRC_MAP_EMIF1_ONLY << EMIF_SDRC_MAP_SHIFT)|\ |
| 578 | (DMM_SDRC_ADDR_SPC_INVALID << EMIF_SDRC_ADDRSPC_SHIFT)|\ |
| 579 | (DMM_SDRC_INTL_NONE << EMIF_SDRC_INTL_SHIFT)|\ |
| 580 | (0xFF << EMIF_SYS_ADDR_SHIFT)) |
| 581 | |
SRICHARAN R | 3d53496 | 2012-03-12 02:25:37 +0000 | [diff] [blame] | 582 | #define EMIF_EXT_PHY_CTRL_TIMING_REG 0x5 |
| 583 | #define EMIF_EXT_PHY_CTRL_CONST_REG 0x13 |
Sricharan | 62a8650 | 2011-11-15 09:50:00 -0500 | [diff] [blame] | 584 | |
| 585 | /* Reg mapping structure */ |
| 586 | struct emif_reg_struct { |
| 587 | u32 emif_mod_id_rev; |
| 588 | u32 emif_status; |
| 589 | u32 emif_sdram_config; |
| 590 | u32 emif_lpddr2_nvm_config; |
| 591 | u32 emif_sdram_ref_ctrl; |
| 592 | u32 emif_sdram_ref_ctrl_shdw; |
| 593 | u32 emif_sdram_tim_1; |
| 594 | u32 emif_sdram_tim_1_shdw; |
| 595 | u32 emif_sdram_tim_2; |
| 596 | u32 emif_sdram_tim_2_shdw; |
| 597 | u32 emif_sdram_tim_3; |
| 598 | u32 emif_sdram_tim_3_shdw; |
| 599 | u32 emif_lpddr2_nvm_tim; |
| 600 | u32 emif_lpddr2_nvm_tim_shdw; |
| 601 | u32 emif_pwr_mgmt_ctrl; |
| 602 | u32 emif_pwr_mgmt_ctrl_shdw; |
| 603 | u32 emif_lpddr2_mode_reg_data; |
| 604 | u32 padding1[1]; |
| 605 | u32 emif_lpddr2_mode_reg_data_es2; |
| 606 | u32 padding11[1]; |
| 607 | u32 emif_lpddr2_mode_reg_cfg; |
| 608 | u32 emif_l3_config; |
| 609 | u32 emif_l3_cfg_val_1; |
| 610 | u32 emif_l3_cfg_val_2; |
| 611 | u32 emif_iodft_tlgc; |
| 612 | u32 padding2[7]; |
| 613 | u32 emif_perf_cnt_1; |
| 614 | u32 emif_perf_cnt_2; |
| 615 | u32 emif_perf_cnt_cfg; |
| 616 | u32 emif_perf_cnt_sel; |
| 617 | u32 emif_perf_cnt_tim; |
| 618 | u32 padding3; |
| 619 | u32 emif_read_idlectrl; |
| 620 | u32 emif_read_idlectrl_shdw; |
| 621 | u32 padding4; |
| 622 | u32 emif_irqstatus_raw_sys; |
| 623 | u32 emif_irqstatus_raw_ll; |
| 624 | u32 emif_irqstatus_sys; |
| 625 | u32 emif_irqstatus_ll; |
| 626 | u32 emif_irqenable_set_sys; |
| 627 | u32 emif_irqenable_set_ll; |
| 628 | u32 emif_irqenable_clr_sys; |
| 629 | u32 emif_irqenable_clr_ll; |
| 630 | u32 padding5; |
| 631 | u32 emif_zq_config; |
| 632 | u32 emif_temp_alert_config; |
| 633 | u32 emif_l3_err_log; |
SRICHARAN R | 3d53496 | 2012-03-12 02:25:37 +0000 | [diff] [blame] | 634 | u32 emif_rd_wr_lvl_rmp_win; |
| 635 | u32 emif_rd_wr_lvl_rmp_ctl; |
| 636 | u32 emif_rd_wr_lvl_ctl; |
| 637 | u32 padding6[1]; |
Sricharan | 62a8650 | 2011-11-15 09:50:00 -0500 | [diff] [blame] | 638 | u32 emif_ddr_phy_ctrl_1; |
| 639 | u32 emif_ddr_phy_ctrl_1_shdw; |
| 640 | u32 emif_ddr_phy_ctrl_2; |
SRICHARAN R | 3d53496 | 2012-03-12 02:25:37 +0000 | [diff] [blame] | 641 | u32 padding7[12]; |
| 642 | u32 emif_rd_wr_exec_thresh; |
| 643 | u32 padding8[55]; |
| 644 | u32 emif_ddr_ext_phy_ctrl_1; |
| 645 | u32 emif_ddr_ext_phy_ctrl_1_shdw; |
| 646 | u32 emif_ddr_ext_phy_ctrl_2; |
| 647 | u32 emif_ddr_ext_phy_ctrl_2_shdw; |
| 648 | u32 emif_ddr_ext_phy_ctrl_3; |
| 649 | u32 emif_ddr_ext_phy_ctrl_3_shdw; |
| 650 | u32 emif_ddr_ext_phy_ctrl_4; |
| 651 | u32 emif_ddr_ext_phy_ctrl_4_shdw; |
| 652 | u32 emif_ddr_ext_phy_ctrl_5; |
| 653 | u32 emif_ddr_ext_phy_ctrl_5_shdw; |
| 654 | u32 emif_ddr_ext_phy_ctrl_6; |
| 655 | u32 emif_ddr_ext_phy_ctrl_6_shdw; |
| 656 | u32 emif_ddr_ext_phy_ctrl_7; |
| 657 | u32 emif_ddr_ext_phy_ctrl_7_shdw; |
| 658 | u32 emif_ddr_ext_phy_ctrl_8; |
| 659 | u32 emif_ddr_ext_phy_ctrl_8_shdw; |
| 660 | u32 emif_ddr_ext_phy_ctrl_9; |
| 661 | u32 emif_ddr_ext_phy_ctrl_9_shdw; |
| 662 | u32 emif_ddr_ext_phy_ctrl_10; |
| 663 | u32 emif_ddr_ext_phy_ctrl_10_shdw; |
| 664 | u32 emif_ddr_ext_phy_ctrl_11; |
| 665 | u32 emif_ddr_ext_phy_ctrl_11_shdw; |
| 666 | u32 emif_ddr_ext_phy_ctrl_12; |
| 667 | u32 emif_ddr_ext_phy_ctrl_12_shdw; |
| 668 | u32 emif_ddr_ext_phy_ctrl_13; |
| 669 | u32 emif_ddr_ext_phy_ctrl_13_shdw; |
| 670 | u32 emif_ddr_ext_phy_ctrl_14; |
| 671 | u32 emif_ddr_ext_phy_ctrl_14_shdw; |
| 672 | u32 emif_ddr_ext_phy_ctrl_15; |
| 673 | u32 emif_ddr_ext_phy_ctrl_15_shdw; |
| 674 | u32 emif_ddr_ext_phy_ctrl_16; |
| 675 | u32 emif_ddr_ext_phy_ctrl_16_shdw; |
| 676 | u32 emif_ddr_ext_phy_ctrl_17; |
| 677 | u32 emif_ddr_ext_phy_ctrl_17_shdw; |
| 678 | u32 emif_ddr_ext_phy_ctrl_18; |
| 679 | u32 emif_ddr_ext_phy_ctrl_18_shdw; |
| 680 | u32 emif_ddr_ext_phy_ctrl_19; |
| 681 | u32 emif_ddr_ext_phy_ctrl_19_shdw; |
| 682 | u32 emif_ddr_ext_phy_ctrl_20; |
| 683 | u32 emif_ddr_ext_phy_ctrl_20_shdw; |
| 684 | u32 emif_ddr_ext_phy_ctrl_21; |
| 685 | u32 emif_ddr_ext_phy_ctrl_21_shdw; |
| 686 | u32 emif_ddr_ext_phy_ctrl_22; |
| 687 | u32 emif_ddr_ext_phy_ctrl_22_shdw; |
| 688 | u32 emif_ddr_ext_phy_ctrl_23; |
| 689 | u32 emif_ddr_ext_phy_ctrl_23_shdw; |
| 690 | u32 emif_ddr_ext_phy_ctrl_24; |
| 691 | u32 emif_ddr_ext_phy_ctrl_24_shdw; |
Sricharan | 62a8650 | 2011-11-15 09:50:00 -0500 | [diff] [blame] | 692 | }; |
| 693 | |
| 694 | struct dmm_lisa_map_regs { |
| 695 | u32 dmm_lisa_map_0; |
| 696 | u32 dmm_lisa_map_1; |
| 697 | u32 dmm_lisa_map_2; |
| 698 | u32 dmm_lisa_map_3; |
| 699 | }; |
| 700 | |
SRICHARAN R | 3d53496 | 2012-03-12 02:25:37 +0000 | [diff] [blame] | 701 | extern const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG]; |
Lokesh Vutla | c5b931a | 2012-05-22 00:03:24 +0000 | [diff] [blame] | 702 | extern const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG]; |
SRICHARAN R | 3d53496 | 2012-03-12 02:25:37 +0000 | [diff] [blame] | 703 | |
Sricharan | 62a8650 | 2011-11-15 09:50:00 -0500 | [diff] [blame] | 704 | #define CS0 0 |
| 705 | #define CS1 1 |
| 706 | /* The maximum frequency at which the LPDDR2 interface can operate in Hz*/ |
| 707 | #define MAX_LPDDR2_FREQ 400000000 /* 400 MHz */ |
| 708 | |
| 709 | /* |
| 710 | * The period of DDR clk is represented as numerator and denominator for |
| 711 | * better accuracy in integer based calculations. However, if the numerator |
| 712 | * and denominator are very huge there may be chances of overflow in |
| 713 | * calculations. So, as a trade-off keep denominator(and consequently |
| 714 | * numerator) within a limit sacrificing some accuracy - but not much |
| 715 | * If denominator and numerator are already small (such as at 400 MHz) |
| 716 | * no adjustment is needed |
| 717 | */ |
| 718 | #define EMIF_PERIOD_DEN_LIMIT 1000 |
| 719 | /* |
| 720 | * Maximum number of different frequencies supported by EMIF driver |
| 721 | * Determines the number of entries in the pointer array for register |
| 722 | * cache |
| 723 | */ |
| 724 | #define EMIF_MAX_NUM_FREQUENCIES 6 |
| 725 | /* |
| 726 | * Indices into the Addressing Table array. |
| 727 | * One entry each for all the different types of devices with different |
| 728 | * addressing schemes |
| 729 | */ |
| 730 | #define ADDR_TABLE_INDEX64M 0 |
| 731 | #define ADDR_TABLE_INDEX128M 1 |
| 732 | #define ADDR_TABLE_INDEX256M 2 |
| 733 | #define ADDR_TABLE_INDEX512M 3 |
| 734 | #define ADDR_TABLE_INDEX1GS4 4 |
| 735 | #define ADDR_TABLE_INDEX2GS4 5 |
| 736 | #define ADDR_TABLE_INDEX4G 6 |
| 737 | #define ADDR_TABLE_INDEX8G 7 |
| 738 | #define ADDR_TABLE_INDEX1GS2 8 |
| 739 | #define ADDR_TABLE_INDEX2GS2 9 |
| 740 | #define ADDR_TABLE_INDEXMAX 10 |
| 741 | |
| 742 | /* Number of Row bits */ |
| 743 | #define ROW_9 0 |
| 744 | #define ROW_10 1 |
| 745 | #define ROW_11 2 |
| 746 | #define ROW_12 3 |
| 747 | #define ROW_13 4 |
| 748 | #define ROW_14 5 |
| 749 | #define ROW_15 6 |
| 750 | #define ROW_16 7 |
| 751 | |
| 752 | /* Number of Column bits */ |
| 753 | #define COL_8 0 |
| 754 | #define COL_9 1 |
| 755 | #define COL_10 2 |
| 756 | #define COL_11 3 |
| 757 | #define COL_7 4 /*Not supported by OMAP included for completeness */ |
| 758 | |
| 759 | /* Number of Banks*/ |
| 760 | #define BANKS1 0 |
| 761 | #define BANKS2 1 |
| 762 | #define BANKS4 2 |
| 763 | #define BANKS8 3 |
| 764 | |
| 765 | /* Refresh rate in micro seconds x 10 */ |
| 766 | #define T_REFI_15_6 156 |
| 767 | #define T_REFI_7_8 78 |
| 768 | #define T_REFI_3_9 39 |
| 769 | |
| 770 | #define EBANK_CS1_DIS 0 |
| 771 | #define EBANK_CS1_EN 1 |
| 772 | |
| 773 | /* Read Latency used by the device at reset */ |
| 774 | #define RL_BOOT 3 |
| 775 | /* Read Latency for the highest frequency you want to use */ |
| 776 | #ifdef CONFIG_OMAP54XX |
| 777 | #define RL_FINAL 8 |
| 778 | #else |
| 779 | #define RL_FINAL 6 |
| 780 | #endif |
| 781 | |
| 782 | |
| 783 | /* Interleaving policies at EMIF level- between banks and Chip Selects */ |
| 784 | #define EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING 0 |
| 785 | #define EMIF_INTERLEAVING_POLICY_NO_BANK_INTERLEAVING 3 |
| 786 | |
| 787 | /* |
| 788 | * Interleaving policy to be used |
| 789 | * Currently set to MAX interleaving for better performance |
| 790 | */ |
| 791 | #define EMIF_INTERLEAVING_POLICY EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING |
| 792 | |
| 793 | /* State of the core voltage: |
| 794 | * This is important for some parameters such as read idle control and |
| 795 | * ZQ calibration timings. Timings are much stricter when voltage ramp |
| 796 | * is happening compared to when the voltage is stable. |
| 797 | * We need to calculate two sets of values for these parameters and use |
| 798 | * them accordingly |
| 799 | */ |
| 800 | #define LPDDR2_VOLTAGE_STABLE 0 |
| 801 | #define LPDDR2_VOLTAGE_RAMPING 1 |
| 802 | |
| 803 | /* Length of the forced read idle period in terms of cycles */ |
| 804 | #define EMIF_REG_READ_IDLE_LEN_VAL 5 |
| 805 | |
| 806 | /* Interval between forced 'read idles' */ |
| 807 | /* To be used when voltage is changed for DPS/DVFS - 1us */ |
| 808 | #define READ_IDLE_INTERVAL_DVFS (1*1000) |
| 809 | /* |
| 810 | * To be used when voltage is not scaled except by Smart Reflex |
| 811 | * 50us - or maximum value will do |
| 812 | */ |
| 813 | #define READ_IDLE_INTERVAL_NORMAL (50*1000) |
| 814 | |
| 815 | |
| 816 | /* |
| 817 | * Unless voltage is changing due to DVFS one ZQCS command every 50ms should |
| 818 | * be enough. This shoule be enough also in the case when voltage is changing |
| 819 | * due to smart-reflex. |
| 820 | */ |
| 821 | #define EMIF_ZQCS_INTERVAL_NORMAL_IN_US (50*1000) |
| 822 | /* |
| 823 | * If voltage is changing due to DVFS ZQCS should be performed more |
| 824 | * often(every 50us) |
| 825 | */ |
| 826 | #define EMIF_ZQCS_INTERVAL_DVFS_IN_US 50 |
| 827 | |
| 828 | /* The interval between ZQCL commands as a multiple of ZQCS interval */ |
| 829 | #define REG_ZQ_ZQCL_MULT 4 |
| 830 | /* The interval between ZQINIT commands as a multiple of ZQCL interval */ |
| 831 | #define REG_ZQ_ZQINIT_MULT 3 |
| 832 | /* Enable ZQ Calibration on exiting Self-refresh */ |
| 833 | #define REG_ZQ_SFEXITEN_ENABLE 1 |
| 834 | /* |
| 835 | * ZQ Calibration simultaneously on both chip-selects: |
| 836 | * Needs one calibration resistor per CS |
| 837 | * None of the boards that we know of have this capability |
| 838 | * So disabled by default |
| 839 | */ |
| 840 | #define REG_ZQ_DUALCALEN_DISABLE 0 |
| 841 | /* |
| 842 | * Enable ZQ Calibration by default on CS0. If we are asked to program |
| 843 | * the EMIF there will be something connected to CS0 for sure |
| 844 | */ |
| 845 | #define REG_ZQ_CS0EN_ENABLE 1 |
| 846 | |
| 847 | /* EMIF_PWR_MGMT_CTRL register */ |
| 848 | /* Low power modes */ |
| 849 | #define LP_MODE_DISABLE 0 |
| 850 | #define LP_MODE_CLOCK_STOP 1 |
| 851 | #define LP_MODE_SELF_REFRESH 2 |
| 852 | #define LP_MODE_PWR_DN 3 |
| 853 | |
| 854 | /* REG_DPD_EN */ |
| 855 | #define DPD_DISABLE 0 |
| 856 | #define DPD_ENABLE 1 |
| 857 | |
| 858 | /* Maximum delay before Low Power Modes */ |
SRICHARAN R | 3d53496 | 2012-03-12 02:25:37 +0000 | [diff] [blame] | 859 | #ifndef CONFIG_OMAP54XX |
Sricharan | 62a8650 | 2011-11-15 09:50:00 -0500 | [diff] [blame] | 860 | #define REG_CS_TIM 0xF |
SRICHARAN R | 3d53496 | 2012-03-12 02:25:37 +0000 | [diff] [blame] | 861 | #else |
| 862 | #define REG_CS_TIM 0x0 |
| 863 | #endif |
Sricharan | 62a8650 | 2011-11-15 09:50:00 -0500 | [diff] [blame] | 864 | #define REG_SR_TIM 0xF |
| 865 | #define REG_PD_TIM 0xF |
| 866 | |
| 867 | /* EMIF_PWR_MGMT_CTRL register */ |
| 868 | #define EMIF_PWR_MGMT_CTRL (\ |
| 869 | ((REG_CS_TIM << EMIF_REG_CS_TIM_SHIFT) & EMIF_REG_CS_TIM_MASK)|\ |
| 870 | ((REG_SR_TIM << EMIF_REG_SR_TIM_SHIFT) & EMIF_REG_SR_TIM_MASK)|\ |
| 871 | ((REG_PD_TIM << EMIF_REG_PD_TIM_SHIFT) & EMIF_REG_PD_TIM_MASK)|\ |
| 872 | ((REG_PD_TIM << EMIF_REG_PD_TIM_SHIFT) & EMIF_REG_PD_TIM_MASK)|\ |
| 873 | ((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)\ |
| 874 | & EMIF_REG_LP_MODE_MASK) |\ |
| 875 | ((DPD_DISABLE << EMIF_REG_DPD_EN_SHIFT)\ |
| 876 | & EMIF_REG_DPD_EN_MASK))\ |
| 877 | |
| 878 | #define EMIF_PWR_MGMT_CTRL_SHDW (\ |
| 879 | ((REG_CS_TIM << EMIF_REG_CS_TIM_SHDW_SHIFT)\ |
| 880 | & EMIF_REG_CS_TIM_SHDW_MASK) |\ |
| 881 | ((REG_SR_TIM << EMIF_REG_SR_TIM_SHDW_SHIFT)\ |
| 882 | & EMIF_REG_SR_TIM_SHDW_MASK) |\ |
| 883 | ((REG_PD_TIM << EMIF_REG_PD_TIM_SHDW_SHIFT)\ |
| 884 | & EMIF_REG_PD_TIM_SHDW_MASK) |\ |
| 885 | ((REG_PD_TIM << EMIF_REG_PD_TIM_SHDW_SHIFT)\ |
| 886 | & EMIF_REG_PD_TIM_SHDW_MASK)) |
| 887 | |
| 888 | /* EMIF_L3_CONFIG register value */ |
| 889 | #define EMIF_L3_CONFIG_VAL_SYS_10_LL_0 0x0A0000FF |
| 890 | #define EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0 0x0A300000 |
SRICHARAN R | 3d53496 | 2012-03-12 02:25:37 +0000 | [diff] [blame] | 891 | #define EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0 0x0A500000 |
Sricharan | 62a8650 | 2011-11-15 09:50:00 -0500 | [diff] [blame] | 892 | |
| 893 | /* |
| 894 | * Value of bits 12:31 of DDR_PHY_CTRL_1 register: |
| 895 | * All these fields have magic values dependent on frequency and |
| 896 | * determined by PHY and DLL integration with EMIF. Setting the magic |
| 897 | * values suggested by hw team. |
| 898 | */ |
| 899 | #define EMIF_DDR_PHY_CTRL_1_BASE_VAL 0x049FF |
| 900 | #define EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ 0x41 |
| 901 | #define EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ 0x80 |
| 902 | #define EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS 0xFF |
| 903 | |
| 904 | /* |
| 905 | * MR1 value: |
| 906 | * Burst length : 8 |
| 907 | * Burst type : sequential |
| 908 | * Wrap : enabled |
| 909 | * nWR : 3(default). EMIF does not do pre-charge. |
| 910 | * : So nWR is don't care |
| 911 | */ |
| 912 | #define MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3 0x23 |
SRICHARAN R | 3d53496 | 2012-03-12 02:25:37 +0000 | [diff] [blame] | 913 | #define MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8 0xc3 |
Sricharan | 62a8650 | 2011-11-15 09:50:00 -0500 | [diff] [blame] | 914 | |
| 915 | /* MR2 */ |
| 916 | #define MR2_RL3_WL1 1 |
| 917 | #define MR2_RL4_WL2 2 |
| 918 | #define MR2_RL5_WL2 3 |
| 919 | #define MR2_RL6_WL3 4 |
| 920 | |
| 921 | /* MR10: ZQ calibration codes */ |
| 922 | #define MR10_ZQ_ZQCS 0x56 |
| 923 | #define MR10_ZQ_ZQCL 0xAB |
| 924 | #define MR10_ZQ_ZQINIT 0xFF |
| 925 | #define MR10_ZQ_ZQRESET 0xC3 |
| 926 | |
| 927 | /* TEMP_ALERT_CONFIG */ |
| 928 | #define TEMP_ALERT_POLL_INTERVAL_MS 360 /* for temp gradient - 5 C/s */ |
| 929 | #define TEMP_ALERT_CONFIG_DEVCT_1 0 |
| 930 | #define TEMP_ALERT_CONFIG_DEVWDT_32 2 |
| 931 | |
| 932 | /* MR16 value: refresh full array(no partial array self refresh) */ |
| 933 | #define MR16_REF_FULL_ARRAY 0 |
| 934 | |
| 935 | /* |
| 936 | * Maximum number of entries we keep in our array of timing tables |
| 937 | * We need not keep all the speed bins supported by the device |
| 938 | * We need to keep timing tables for only the speed bins that we |
| 939 | * are interested in |
| 940 | */ |
| 941 | #define MAX_NUM_SPEEDBINS 4 |
| 942 | |
| 943 | /* LPDDR2 Densities */ |
| 944 | #define LPDDR2_DENSITY_64Mb 0 |
| 945 | #define LPDDR2_DENSITY_128Mb 1 |
| 946 | #define LPDDR2_DENSITY_256Mb 2 |
| 947 | #define LPDDR2_DENSITY_512Mb 3 |
| 948 | #define LPDDR2_DENSITY_1Gb 4 |
| 949 | #define LPDDR2_DENSITY_2Gb 5 |
| 950 | #define LPDDR2_DENSITY_4Gb 6 |
| 951 | #define LPDDR2_DENSITY_8Gb 7 |
| 952 | #define LPDDR2_DENSITY_16Gb 8 |
| 953 | #define LPDDR2_DENSITY_32Gb 9 |
| 954 | |
| 955 | /* LPDDR2 type */ |
| 956 | #define LPDDR2_TYPE_S4 0 |
| 957 | #define LPDDR2_TYPE_S2 1 |
| 958 | #define LPDDR2_TYPE_NVM 2 |
| 959 | |
| 960 | /* LPDDR2 IO width */ |
| 961 | #define LPDDR2_IO_WIDTH_32 0 |
| 962 | #define LPDDR2_IO_WIDTH_16 1 |
| 963 | #define LPDDR2_IO_WIDTH_8 2 |
| 964 | |
| 965 | /* Mode register numbers */ |
| 966 | #define LPDDR2_MR0 0 |
| 967 | #define LPDDR2_MR1 1 |
| 968 | #define LPDDR2_MR2 2 |
| 969 | #define LPDDR2_MR3 3 |
| 970 | #define LPDDR2_MR4 4 |
| 971 | #define LPDDR2_MR5 5 |
| 972 | #define LPDDR2_MR6 6 |
| 973 | #define LPDDR2_MR7 7 |
| 974 | #define LPDDR2_MR8 8 |
| 975 | #define LPDDR2_MR9 9 |
| 976 | #define LPDDR2_MR10 10 |
| 977 | #define LPDDR2_MR11 11 |
| 978 | #define LPDDR2_MR16 16 |
| 979 | #define LPDDR2_MR17 17 |
| 980 | #define LPDDR2_MR18 18 |
| 981 | |
| 982 | /* MR0 */ |
| 983 | #define LPDDR2_MR0_DAI_SHIFT 0 |
| 984 | #define LPDDR2_MR0_DAI_MASK 1 |
| 985 | #define LPDDR2_MR0_DI_SHIFT 1 |
| 986 | #define LPDDR2_MR0_DI_MASK (1 << 1) |
| 987 | #define LPDDR2_MR0_DNVI_SHIFT 2 |
| 988 | #define LPDDR2_MR0_DNVI_MASK (1 << 2) |
| 989 | |
| 990 | /* MR4 */ |
| 991 | #define MR4_SDRAM_REF_RATE_SHIFT 0 |
| 992 | #define MR4_SDRAM_REF_RATE_MASK 7 |
| 993 | #define MR4_TUF_SHIFT 7 |
| 994 | #define MR4_TUF_MASK (1 << 7) |
| 995 | |
| 996 | /* MR4 SDRAM Refresh Rate field values */ |
| 997 | #define SDRAM_TEMP_LESS_LOW_SHUTDOWN 0x0 |
| 998 | #define SDRAM_TEMP_LESS_4X_REFRESH_AND_TIMINGS 0x1 |
| 999 | #define SDRAM_TEMP_LESS_2X_REFRESH_AND_TIMINGS 0x2 |
| 1000 | #define SDRAM_TEMP_NOMINAL 0x3 |
| 1001 | #define SDRAM_TEMP_RESERVED_4 0x4 |
| 1002 | #define SDRAM_TEMP_HIGH_DERATE_REFRESH 0x5 |
| 1003 | #define SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS 0x6 |
| 1004 | #define SDRAM_TEMP_VERY_HIGH_SHUTDOWN 0x7 |
| 1005 | |
| 1006 | #define LPDDR2_MANUFACTURER_SAMSUNG 1 |
| 1007 | #define LPDDR2_MANUFACTURER_QIMONDA 2 |
| 1008 | #define LPDDR2_MANUFACTURER_ELPIDA 3 |
| 1009 | #define LPDDR2_MANUFACTURER_ETRON 4 |
| 1010 | #define LPDDR2_MANUFACTURER_NANYA 5 |
| 1011 | #define LPDDR2_MANUFACTURER_HYNIX 6 |
| 1012 | #define LPDDR2_MANUFACTURER_MOSEL 7 |
| 1013 | #define LPDDR2_MANUFACTURER_WINBOND 8 |
| 1014 | #define LPDDR2_MANUFACTURER_ESMT 9 |
| 1015 | #define LPDDR2_MANUFACTURER_SPANSION 11 |
| 1016 | #define LPDDR2_MANUFACTURER_SST 12 |
| 1017 | #define LPDDR2_MANUFACTURER_ZMOS 13 |
| 1018 | #define LPDDR2_MANUFACTURER_INTEL 14 |
| 1019 | #define LPDDR2_MANUFACTURER_NUMONYX 254 |
| 1020 | #define LPDDR2_MANUFACTURER_MICRON 255 |
| 1021 | |
| 1022 | /* MR8 register fields */ |
| 1023 | #define MR8_TYPE_SHIFT 0x0 |
| 1024 | #define MR8_TYPE_MASK 0x3 |
| 1025 | #define MR8_DENSITY_SHIFT 0x2 |
| 1026 | #define MR8_DENSITY_MASK (0xF << 0x2) |
| 1027 | #define MR8_IO_WIDTH_SHIFT 0x6 |
| 1028 | #define MR8_IO_WIDTH_MASK (0x3 << 0x6) |
| 1029 | |
| 1030 | struct lpddr2_addressing { |
| 1031 | u8 num_banks; |
| 1032 | u8 t_REFI_us_x10; |
| 1033 | u8 row_sz[2]; /* One entry each for x32 and x16 */ |
| 1034 | u8 col_sz[2]; /* One entry each for x32 and x16 */ |
| 1035 | }; |
| 1036 | |
| 1037 | /* Structure for timings from the DDR datasheet */ |
| 1038 | struct lpddr2_ac_timings { |
| 1039 | u32 max_freq; |
| 1040 | u8 RL; |
| 1041 | u8 tRPab; |
| 1042 | u8 tRCD; |
| 1043 | u8 tWR; |
| 1044 | u8 tRASmin; |
| 1045 | u8 tRRD; |
| 1046 | u8 tWTRx2; |
| 1047 | u8 tXSR; |
| 1048 | u8 tXPx2; |
| 1049 | u8 tRFCab; |
| 1050 | u8 tRTPx2; |
| 1051 | u8 tCKE; |
| 1052 | u8 tCKESR; |
| 1053 | u8 tZQCS; |
| 1054 | u32 tZQCL; |
| 1055 | u32 tZQINIT; |
| 1056 | u8 tDQSCKMAXx2; |
| 1057 | u8 tRASmax; |
| 1058 | u8 tFAW; |
| 1059 | |
| 1060 | }; |
| 1061 | |
| 1062 | /* |
| 1063 | * Min tCK values for some of the parameters: |
| 1064 | * If the calculated clock cycles for the respective parameter is |
| 1065 | * less than the corresponding min tCK value, we need to set the min |
| 1066 | * tCK value. This may happen at lower frequencies. |
| 1067 | */ |
| 1068 | struct lpddr2_min_tck { |
| 1069 | u32 tRL; |
| 1070 | u32 tRP_AB; |
| 1071 | u32 tRCD; |
| 1072 | u32 tWR; |
| 1073 | u32 tRAS_MIN; |
| 1074 | u32 tRRD; |
| 1075 | u32 tWTR; |
| 1076 | u32 tXP; |
| 1077 | u32 tRTP; |
| 1078 | u8 tCKE; |
| 1079 | u32 tCKESR; |
| 1080 | u32 tFAW; |
| 1081 | }; |
| 1082 | |
| 1083 | struct lpddr2_device_details { |
| 1084 | u8 type; |
| 1085 | u8 density; |
| 1086 | u8 io_width; |
| 1087 | u8 manufacturer; |
| 1088 | }; |
| 1089 | |
| 1090 | struct lpddr2_device_timings { |
| 1091 | const struct lpddr2_ac_timings **ac_timings; |
| 1092 | const struct lpddr2_min_tck *min_tck; |
| 1093 | }; |
| 1094 | |
| 1095 | /* Details of the devices connected to each chip-select of an EMIF instance */ |
| 1096 | struct emif_device_details { |
| 1097 | const struct lpddr2_device_details *cs0_device_details; |
| 1098 | const struct lpddr2_device_details *cs1_device_details; |
| 1099 | const struct lpddr2_device_timings *cs0_device_timings; |
| 1100 | const struct lpddr2_device_timings *cs1_device_timings; |
| 1101 | }; |
| 1102 | |
| 1103 | /* |
| 1104 | * Structure containing shadow of important registers in EMIF |
| 1105 | * The calculation function fills in this structure to be later used for |
| 1106 | * initialization and DVFS |
| 1107 | */ |
| 1108 | struct emif_regs { |
| 1109 | u32 freq; |
| 1110 | u32 sdram_config_init; |
| 1111 | u32 sdram_config; |
| 1112 | u32 ref_ctrl; |
| 1113 | u32 sdram_tim1; |
| 1114 | u32 sdram_tim2; |
| 1115 | u32 sdram_tim3; |
| 1116 | u32 read_idle_ctrl; |
| 1117 | u32 zq_config; |
| 1118 | u32 temp_alert_config; |
| 1119 | u32 emif_ddr_phy_ctlr_1_init; |
| 1120 | u32 emif_ddr_phy_ctlr_1; |
SRICHARAN R | 3d53496 | 2012-03-12 02:25:37 +0000 | [diff] [blame] | 1121 | u32 emif_ddr_ext_phy_ctrl_1; |
| 1122 | u32 emif_ddr_ext_phy_ctrl_2; |
| 1123 | u32 emif_ddr_ext_phy_ctrl_3; |
| 1124 | u32 emif_ddr_ext_phy_ctrl_4; |
| 1125 | u32 emif_ddr_ext_phy_ctrl_5; |
Lokesh Vutla | c5b931a | 2012-05-22 00:03:24 +0000 | [diff] [blame] | 1126 | u32 emif_rd_wr_lvl_rmp_win; |
| 1127 | u32 emif_rd_wr_lvl_rmp_ctl; |
| 1128 | u32 emif_rd_wr_lvl_ctl; |
| 1129 | u32 emif_rd_wr_exec_thresh; |
Sricharan | 62a8650 | 2011-11-15 09:50:00 -0500 | [diff] [blame] | 1130 | }; |
| 1131 | |
| 1132 | /* assert macros */ |
| 1133 | #if defined(DEBUG) |
| 1134 | #define emif_assert(c) ({ if (!(c)) for (;;); }) |
| 1135 | #else |
| 1136 | #define emif_assert(c) ({ if (0) hang(); }) |
| 1137 | #endif |
| 1138 | |
| 1139 | #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS |
| 1140 | void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs); |
| 1141 | void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs); |
| 1142 | #else |
| 1143 | struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs, |
| 1144 | struct lpddr2_device_details *lpddr2_dev_details); |
| 1145 | void emif_get_device_timings(u32 emif_nr, |
| 1146 | const struct lpddr2_device_timings **cs0_device_timings, |
| 1147 | const struct lpddr2_device_timings **cs1_device_timings); |
| 1148 | #endif |
| 1149 | |
SRICHARAN R | b9f10a5 | 2012-06-04 03:40:23 +0000 | [diff] [blame] | 1150 | void do_ext_phy_settings(u32 base, const struct emif_regs *regs); |
| 1151 | |
Sricharan | 62a8650 | 2011-11-15 09:50:00 -0500 | [diff] [blame] | 1152 | #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS |
| 1153 | extern u32 *const T_num; |
| 1154 | extern u32 *const T_den; |
| 1155 | extern u32 *const emif_sizes; |
| 1156 | #endif |
| 1157 | |
Lokesh Vutla | 0f42de6 | 2012-05-22 00:03:25 +0000 | [diff] [blame] | 1158 | void config_data_eye_leveling_samples(u32 emif_base); |
Sricharan | 62a8650 | 2011-11-15 09:50:00 -0500 | [diff] [blame] | 1159 | #endif |