| commit | c5b931afda5d504e276e52f108c9be4d62fa96c2 | [log] [tgz] |
|---|---|---|
| author | Lokesh Vutla <lokeshvutla@ti.com> | Tue May 22 00:03:24 2012 +0000 |
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | Sat Jul 07 14:07:23 2012 +0200 |
| tree | c549887069235d35144830a8ec0bcf9346c1d1ca | |
| parent | ff7b2a967562ce0d15339ed121f41c8e4cee3ceb [diff] |
OMAP5: ADD precalculated timings for ddr3 Adding precalculated timings for ddr3 with 1cs adding required registers for ddr3 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>