Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Jon Medhurst \(Tixy\) | 413ca3d | 2016-06-23 13:37:32 +0100 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2016 Linaro |
| 4 | * Jon Medhurst <tixy@linaro.org> |
| 5 | * |
| 6 | * TC2 specific code for Versatile Express. |
Jon Medhurst \(Tixy\) | 413ca3d | 2016-06-23 13:37:32 +0100 | [diff] [blame] | 7 | */ |
| 8 | |
Sudeep Holla | b1bb4d3 | 2016-09-23 17:38:39 +0100 | [diff] [blame] | 9 | #include <asm/armv7.h> |
Jon Medhurst \(Tixy\) | 413ca3d | 2016-06-23 13:37:32 +0100 | [diff] [blame] | 10 | #include <asm/io.h> |
Sudeep Holla | b1bb4d3 | 2016-09-23 17:38:39 +0100 | [diff] [blame] | 11 | #include <asm/u-boot.h> |
| 12 | #include <common.h> |
Masahiro Yamada | 75f82d0 | 2018-03-05 01:20:11 +0900 | [diff] [blame] | 13 | #include <linux/libfdt.h> |
Jon Medhurst \(Tixy\) | 413ca3d | 2016-06-23 13:37:32 +0100 | [diff] [blame] | 14 | |
| 15 | #define SCC_BASE 0x7fff0000 |
| 16 | |
| 17 | bool armv7_boot_nonsec_default(void) |
| 18 | { |
| 19 | #ifdef CONFIG_ARMV7_BOOT_SEC_DEFAULT |
Heinrich Schuchardt | e6f33bf | 2018-04-10 23:11:53 +0200 | [diff] [blame] | 20 | return false; |
Jon Medhurst \(Tixy\) | 413ca3d | 2016-06-23 13:37:32 +0100 | [diff] [blame] | 21 | #else |
| 22 | /* |
| 23 | * The Serial Configuration Controller (SCC) register at address 0x700 |
| 24 | * contains flags for configuring the behaviour of the Boot Monitor |
| 25 | * (which CPUs execute from reset). Two of these bits are of interest: |
| 26 | * |
| 27 | * bit 12 = Use per-cpu mailboxes for power management |
| 28 | * bit 13 = Power down the non-boot cluster |
| 29 | * |
| 30 | * It is only when both of these are false that U-Boot's current |
| 31 | * implementation of 'nonsec' mode can work as expected because we |
| 32 | * rely on getting all CPUs to execute _nonsec_init, so let's check that. |
| 33 | */ |
| 34 | return (readl((u32 *)(SCC_BASE + 0x700)) & ((1 << 12) | (1 << 13))) == 0; |
| 35 | #endif |
| 36 | } |
Sudeep Holla | b1bb4d3 | 2016-09-23 17:38:39 +0100 | [diff] [blame] | 37 | |
| 38 | #ifdef CONFIG_OF_BOARD_SETUP |
Masahiro Yamada | f7ed78b | 2020-06-26 15:13:33 +0900 | [diff] [blame] | 39 | int ft_board_setup(void *fdt, struct bd_info *bd) |
Sudeep Holla | b1bb4d3 | 2016-09-23 17:38:39 +0100 | [diff] [blame] | 40 | { |
| 41 | int offset, tmp, len; |
| 42 | const struct fdt_property *prop; |
| 43 | const char *cci_compatible = "arm,cci-400-ctrl-if"; |
| 44 | |
| 45 | #ifdef CONFIG_ARMV7_NONSEC |
| 46 | if (!armv7_boot_nonsec()) |
| 47 | return 0; |
| 48 | #else |
| 49 | return 0; |
| 50 | #endif |
| 51 | /* Booting in nonsec mode, disable CCI access */ |
| 52 | offset = fdt_path_offset(fdt, "/cpus"); |
| 53 | if (offset < 0) { |
| 54 | printf("couldn't find /cpus\n"); |
| 55 | return offset; |
| 56 | } |
| 57 | |
| 58 | /* delete cci-control-port in each cpu node */ |
| 59 | for (tmp = fdt_first_subnode(fdt, offset); tmp >= 0; |
| 60 | tmp = fdt_next_subnode(fdt, tmp)) |
| 61 | fdt_delprop(fdt, tmp, "cci-control-port"); |
| 62 | |
| 63 | /* disable all ace cci slave ports */ |
| 64 | offset = fdt_node_offset_by_prop_value(fdt, offset, "compatible", |
| 65 | cci_compatible, 20); |
| 66 | while (offset > 0) { |
| 67 | prop = fdt_get_property(fdt, offset, "interface-type", |
| 68 | &len); |
| 69 | if (!prop) |
| 70 | continue; |
| 71 | if (len < 4) |
| 72 | continue; |
| 73 | if (strcmp(prop->data, "ace")) |
| 74 | continue; |
| 75 | |
| 76 | fdt_setprop_string(fdt, offset, "status", "disabled"); |
| 77 | |
| 78 | offset = fdt_node_offset_by_prop_value(fdt, offset, "compatible", |
| 79 | cci_compatible, 20); |
| 80 | } |
| 81 | |
| 82 | return 0; |
| 83 | } |
| 84 | #endif /* CONFIG_OF_BOARD_SETUP */ |