| Yanhong Wang | 5a85d05 | 2023-03-29 11:42:13 +0800 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0+ |
| 2 | |||||
| 3 | config SPL_CLK_JH7110 | ||||
| 4 | bool "SPL clock support for JH7110" | ||||
| 5 | depends on STARFIVE_JH7110 && SPL | ||||
| 6 | select SPL_CLK | ||||
| 7 | select SPL_CLK_CCF | ||||
| 8 | help | ||||
| 9 | This enables SPL DM support for clock driver in JH7110. | ||||
| 10 | |||||
| 11 | config CLK_JH7110 | ||||
| 12 | bool "StarFive JH7110 clock support" | ||||
| 13 | depends on STARFIVE_JH7110 | ||||
| 14 | select CLK | ||||
| 15 | select CLK_CCF | ||||
| 16 | help | ||||
| 17 | This enables support clock driver for StarFive JH7110 SoC platform. | ||||