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git01.mediatek.com / filogic / uboot / f78eff68ef5da51f78582c4177ed824057bfe38f / . / arch / arm / mach-uniphier / clk / pll-ld4.c
blob: c66031bdd05a13b70fa9901b3d64d34edabef02a [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]2/*
3 * Copyright (C) 2013-2014 Panasonic Corporation
4 * Copyright (C) 2015-2016 Socionext Inc.
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]5 */
6
Masahiro Yamadaeb6aeca2017-01-21 18:05:25 +0900[diff] [blame]7#include <linux/delay.h>
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]8#include <linux/io.h>
9
10#include "../init.h"
11#include "../sc-regs.h"
12#include "../sg-regs.h"
13#include "pll.h"
14
15static void upll_init(void)
16{
17 u32 tmp, clk_mode_upll, clk_mode_axosel;
18
Masahiro Yamada76b31242019-07-10 20:07:40 +0900[diff] [blame]19 tmp = readl(sg_base + SG_PINMON0);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]20 clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
21 clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
22
23 /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]24 tmp = readl(sc_base + SC_UPLLCTRL);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]25 tmp &= ~0x18000000;
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]26 writel(tmp, sc_base + SC_UPLLCTRL);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]27
28 if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
29 if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
30 clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
31 /* AXO: 25MHz */
32 tmp &= ~0x07ffffff;
33 tmp |= 0x0228f5c0;
34 } else {
35 /* AXO: default 24.576MHz */
36 tmp &= ~0x07ffffff;
37 tmp |= 0x02328000;
38 }
39 }
40
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]41 writel(tmp, sc_base + SC_UPLLCTRL);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]42
43 /* set 1 to K_LD(UPLLCTRL.bit[27]) */
44 tmp |= 0x08000000;
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]45 writel(tmp, sc_base + SC_UPLLCTRL);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]46
47 /* wait 10 usec */
48 udelay(10);
49
50 /* set 1 to SNRT(UPLLCTRL.bit[28]) */
51 tmp |= 0x10000000;
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]52 writel(tmp, sc_base + SC_UPLLCTRL);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]53}
54
55static void vpll_init(void)
56{
57 u32 tmp, clk_mode_axosel;
58
Masahiro Yamada76b31242019-07-10 20:07:40 +0900[diff] [blame]59 tmp = readl(sg_base + SG_PINMON0);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]60 clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
61
62 /* set 1 to VPLA27WP and VPLA27WP */
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]63 tmp = readl(sc_base + SC_VPLL27ACTRL);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]64 tmp |= 0x00000001;
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]65 writel(tmp, sc_base + SC_VPLL27ACTRL);
66 tmp = readl(sc_base + SC_VPLL27BCTRL);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]67 tmp |= 0x00000001;
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]68 writel(tmp, sc_base + SC_VPLL27BCTRL);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]69
70 /* Set 0 to VPLA_K_LD and VPLB_K_LD */
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]71 tmp = readl(sc_base + SC_VPLL27ACTRL3);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]72 tmp &= ~0x10000000;
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]73 writel(tmp, sc_base + SC_VPLL27ACTRL3);
74 tmp = readl(sc_base + SC_VPLL27BCTRL3);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]75 tmp &= ~0x10000000;
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]76 writel(tmp, sc_base + SC_VPLL27BCTRL3);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]77
78 /* Set 0 to VPLA_SNRST and VPLB_SNRST */
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]79 tmp = readl(sc_base + SC_VPLL27ACTRL2);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]80 tmp &= ~0x10000000;
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]81 writel(tmp, sc_base + SC_VPLL27ACTRL2);
82 tmp = readl(sc_base + SC_VPLL27BCTRL2);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]83 tmp &= ~0x10000000;
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]84 writel(tmp, sc_base + SC_VPLL27BCTRL2);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]85
86 /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]87 tmp = readl(sc_base + SC_VPLL27ACTRL2);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]88 tmp &= ~0x0000007f;
89 tmp |= 0x00000020;
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]90 writel(tmp, sc_base + SC_VPLL27ACTRL2);
91 tmp = readl(sc_base + SC_VPLL27BCTRL2);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]92 tmp &= ~0x0000007f;
93 tmp |= 0x00000020;
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]94 writel(tmp, sc_base + SC_VPLL27BCTRL2);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]95
96 if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
97 clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
98 /* AXO: 25MHz */
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]99 tmp = readl(sc_base + SC_VPLL27ACTRL3);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]100 tmp &= ~0x000fffff;
101 tmp |= 0x00066664;
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]102 writel(tmp, sc_base + SC_VPLL27ACTRL3);
103 tmp = readl(sc_base + SC_VPLL27BCTRL3);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]104 tmp &= ~0x000fffff;
105 tmp |= 0x00066664;
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]106 writel(tmp, sc_base + SC_VPLL27BCTRL3);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]107 } else {
108 /* AXO: default 24.576MHz */
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]109 tmp = readl(sc_base + SC_VPLL27ACTRL3);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]110 tmp &= ~0x000fffff;
111 tmp |= 0x000f5800;
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]112 writel(tmp, sc_base + SC_VPLL27ACTRL3);
113 tmp = readl(sc_base + SC_VPLL27BCTRL3);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]114 tmp &= ~0x000fffff;
115 tmp |= 0x000f5800;
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]116 writel(tmp, sc_base + SC_VPLL27BCTRL3);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]117 }
118
119 /* Set 1 to VPLA_K_LD and VPLB_K_LD */
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]120 tmp = readl(sc_base + SC_VPLL27ACTRL3);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]121 tmp |= 0x10000000;
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]122 writel(tmp, sc_base + SC_VPLL27ACTRL3);
123 tmp = readl(sc_base + SC_VPLL27BCTRL3);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]124 tmp |= 0x10000000;
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]125 writel(tmp, sc_base + SC_VPLL27BCTRL3);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]126
127 /* wait 10 usec */
128 udelay(10);
129
130 /* Set 0 to VPLA_SNRST and VPLB_SNRST */
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]131 tmp = readl(sc_base + SC_VPLL27ACTRL2);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]132 tmp |= 0x10000000;
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]133 writel(tmp, sc_base + SC_VPLL27ACTRL2);
134 tmp = readl(sc_base + SC_VPLL27BCTRL2);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]135 tmp |= 0x10000000;
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]136 writel(tmp, sc_base + SC_VPLL27BCTRL2);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]137
138 /* set 0 to VPLA27WP and VPLA27WP */
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]139 tmp = readl(sc_base + SC_VPLL27ACTRL);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]140 tmp &= ~0x00000001;
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]141 writel(tmp, sc_base + SC_VPLL27ACTRL);
142 tmp = readl(sc_base + SC_VPLL27BCTRL);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]143 tmp |= ~0x00000001;
Masahiro Yamadac84024c2019-07-10 20:07:41 +0900[diff] [blame]144 writel(tmp, sc_base + SC_VPLL27BCTRL);
Masahiro Yamada9d6652c2016-09-17 03:33:09 +0900[diff] [blame]145}
146
147void uniphier_ld4_pll_init(void)
148{
149 upll_init();
150 vpll_init();
151 uniphier_ld4_dpll_ssc_en();
152}