ARM: uniphier: de-couple SC macros into base address and offset
The SC_* macros represent the address of SysCtrl registers.
For a planned new SoC, its base address will be changed.
Turn the SC_* macros into the offset from the base address.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
diff --git a/arch/arm/mach-uniphier/clk/pll-ld4.c b/arch/arm/mach-uniphier/clk/pll-ld4.c
index 34f1c9c..c66031b 100644
--- a/arch/arm/mach-uniphier/clk/pll-ld4.c
+++ b/arch/arm/mach-uniphier/clk/pll-ld4.c
@@ -21,9 +21,9 @@
clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
/* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
- tmp = readl(SC_UPLLCTRL);
+ tmp = readl(sc_base + SC_UPLLCTRL);
tmp &= ~0x18000000;
- writel(tmp, SC_UPLLCTRL);
+ writel(tmp, sc_base + SC_UPLLCTRL);
if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
@@ -38,18 +38,18 @@
}
}
- writel(tmp, SC_UPLLCTRL);
+ writel(tmp, sc_base + SC_UPLLCTRL);
/* set 1 to K_LD(UPLLCTRL.bit[27]) */
tmp |= 0x08000000;
- writel(tmp, SC_UPLLCTRL);
+ writel(tmp, sc_base + SC_UPLLCTRL);
/* wait 10 usec */
udelay(10);
/* set 1 to SNRT(UPLLCTRL.bit[28]) */
tmp |= 0x10000000;
- writel(tmp, SC_UPLLCTRL);
+ writel(tmp, sc_base + SC_UPLLCTRL);
}
static void vpll_init(void)
@@ -60,88 +60,88 @@
clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
/* set 1 to VPLA27WP and VPLA27WP */
- tmp = readl(SC_VPLL27ACTRL);
+ tmp = readl(sc_base + SC_VPLL27ACTRL);
tmp |= 0x00000001;
- writel(tmp, SC_VPLL27ACTRL);
- tmp = readl(SC_VPLL27BCTRL);
+ writel(tmp, sc_base + SC_VPLL27ACTRL);
+ tmp = readl(sc_base + SC_VPLL27BCTRL);
tmp |= 0x00000001;
- writel(tmp, SC_VPLL27BCTRL);
+ writel(tmp, sc_base + SC_VPLL27BCTRL);
/* Set 0 to VPLA_K_LD and VPLB_K_LD */
- tmp = readl(SC_VPLL27ACTRL3);
+ tmp = readl(sc_base + SC_VPLL27ACTRL3);
tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
+ writel(tmp, sc_base + SC_VPLL27ACTRL3);
+ tmp = readl(sc_base + SC_VPLL27BCTRL3);
tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27BCTRL3);
+ writel(tmp, sc_base + SC_VPLL27BCTRL3);
/* Set 0 to VPLA_SNRST and VPLB_SNRST */
- tmp = readl(SC_VPLL27ACTRL2);
+ tmp = readl(sc_base + SC_VPLL27ACTRL2);
tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
+ writel(tmp, sc_base + SC_VPLL27ACTRL2);
+ tmp = readl(sc_base + SC_VPLL27BCTRL2);
tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27BCTRL2);
+ writel(tmp, sc_base + SC_VPLL27BCTRL2);
/* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
- tmp = readl(SC_VPLL27ACTRL2);
+ tmp = readl(sc_base + SC_VPLL27ACTRL2);
tmp &= ~0x0000007f;
tmp |= 0x00000020;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
+ writel(tmp, sc_base + SC_VPLL27ACTRL2);
+ tmp = readl(sc_base + SC_VPLL27BCTRL2);
tmp &= ~0x0000007f;
tmp |= 0x00000020;
- writel(tmp, SC_VPLL27BCTRL2);
+ writel(tmp, sc_base + SC_VPLL27BCTRL2);
if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
/* AXO: 25MHz */
- tmp = readl(SC_VPLL27ACTRL3);
+ tmp = readl(sc_base + SC_VPLL27ACTRL3);
tmp &= ~0x000fffff;
tmp |= 0x00066664;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
+ writel(tmp, sc_base + SC_VPLL27ACTRL3);
+ tmp = readl(sc_base + SC_VPLL27BCTRL3);
tmp &= ~0x000fffff;
tmp |= 0x00066664;
- writel(tmp, SC_VPLL27BCTRL3);
+ writel(tmp, sc_base + SC_VPLL27BCTRL3);
} else {
/* AXO: default 24.576MHz */
- tmp = readl(SC_VPLL27ACTRL3);
+ tmp = readl(sc_base + SC_VPLL27ACTRL3);
tmp &= ~0x000fffff;
tmp |= 0x000f5800;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
+ writel(tmp, sc_base + SC_VPLL27ACTRL3);
+ tmp = readl(sc_base + SC_VPLL27BCTRL3);
tmp &= ~0x000fffff;
tmp |= 0x000f5800;
- writel(tmp, SC_VPLL27BCTRL3);
+ writel(tmp, sc_base + SC_VPLL27BCTRL3);
}
/* Set 1 to VPLA_K_LD and VPLB_K_LD */
- tmp = readl(SC_VPLL27ACTRL3);
+ tmp = readl(sc_base + SC_VPLL27ACTRL3);
tmp |= 0x10000000;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
+ writel(tmp, sc_base + SC_VPLL27ACTRL3);
+ tmp = readl(sc_base + SC_VPLL27BCTRL3);
tmp |= 0x10000000;
- writel(tmp, SC_VPLL27BCTRL3);
+ writel(tmp, sc_base + SC_VPLL27BCTRL3);
/* wait 10 usec */
udelay(10);
/* Set 0 to VPLA_SNRST and VPLB_SNRST */
- tmp = readl(SC_VPLL27ACTRL2);
+ tmp = readl(sc_base + SC_VPLL27ACTRL2);
tmp |= 0x10000000;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
+ writel(tmp, sc_base + SC_VPLL27ACTRL2);
+ tmp = readl(sc_base + SC_VPLL27BCTRL2);
tmp |= 0x10000000;
- writel(tmp, SC_VPLL27BCTRL2);
+ writel(tmp, sc_base + SC_VPLL27BCTRL2);
/* set 0 to VPLA27WP and VPLA27WP */
- tmp = readl(SC_VPLL27ACTRL);
+ tmp = readl(sc_base + SC_VPLL27ACTRL);
tmp &= ~0x00000001;
- writel(tmp, SC_VPLL27ACTRL);
- tmp = readl(SC_VPLL27BCTRL);
+ writel(tmp, sc_base + SC_VPLL27ACTRL);
+ tmp = readl(sc_base + SC_VPLL27BCTRL);
tmp |= ~0x00000001;
- writel(tmp, SC_VPLL27BCTRL);
+ writel(tmp, sc_base + SC_VPLL27BCTRL);
}
void uniphier_ld4_pll_init(void)