ARM: uniphier: de-couple SC macros into base address and offset
The SC_* macros represent the address of SysCtrl registers.
For a planned new SoC, its base address will be changed.
Turn the SC_* macros into the offset from the base address.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
diff --git a/arch/arm/mach-uniphier/clk/clk-dram-ld4.c b/arch/arm/mach-uniphier/clk/clk-dram-ld4.c
index 39cde44..c796d36 100644
--- a/arch/arm/mach-uniphier/clk/clk-dram-ld4.c
+++ b/arch/arm/mach-uniphier/clk/clk-dram-ld4.c
@@ -16,14 +16,14 @@
u32 tmp;
/* deassert reset */
- tmp = readl(SC_RSTCTRL);
+ tmp = readl(sc_base + SC_RSTCTRL);
tmp |= SC_RSTCTRL_NRST_UMC1 | SC_RSTCTRL_NRST_UMC0;
- writel(tmp, SC_RSTCTRL);
- readl(SC_RSTCTRL); /* dummy read */
+ writel(tmp, sc_base + SC_RSTCTRL);
+ readl(sc_base + SC_RSTCTRL); /* dummy read */
/* provide clocks */
- tmp = readl(SC_CLKCTRL);
+ tmp = readl(sc_base + SC_CLKCTRL);
tmp |= SC_CLKCTRL_CEN_UMC;
- writel(tmp, SC_CLKCTRL);
- readl(SC_CLKCTRL); /* dummy read */
+ writel(tmp, sc_base + SC_CLKCTRL);
+ readl(sc_base + SC_CLKCTRL); /* dummy read */
}
diff --git a/arch/arm/mach-uniphier/clk/clk-dram-pro5.c b/arch/arm/mach-uniphier/clk/clk-dram-pro5.c
index 7674ceb..808d1eb 100644
--- a/arch/arm/mach-uniphier/clk/clk-dram-pro5.c
+++ b/arch/arm/mach-uniphier/clk/clk-dram-pro5.c
@@ -18,17 +18,17 @@
* UMCA1, UMC31: Ch0 (WIO1)
* UMCA0, UMC30: Ch0 (WIO0)
*/
- tmp = readl(SC_RSTCTRL4);
+ tmp = readl(sc_base + SC_RSTCTRL4);
tmp |= SC_RSTCTRL4_NRST_UMCSB | SC_RSTCTRL4_NRST_UMCA2 |
SC_RSTCTRL4_NRST_UMCA1 | SC_RSTCTRL4_NRST_UMCA0 |
SC_RSTCTRL4_NRST_UMC31 | SC_RSTCTRL4_NRST_UMC30;
- writel(tmp, SC_RSTCTRL4);
- readl(SC_RSTCTRL4); /* dummy read */
+ writel(tmp, sc_base + SC_RSTCTRL4);
+ readl(sc_base + SC_RSTCTRL4); /* dummy read */
/* provide clocks */
- tmp = readl(SC_CLKCTRL4);
+ tmp = readl(sc_base + SC_CLKCTRL4);
tmp |= SC_CLKCTRL4_CEN_UMCSB | SC_CLKCTRL4_CEN_UMC1 |
SC_CLKCTRL4_CEN_UMC0;
- writel(tmp, SC_CLKCTRL4);
- readl(SC_CLKCTRL4); /* dummy read */
+ writel(tmp, sc_base + SC_CLKCTRL4);
+ readl(sc_base + SC_CLKCTRL4); /* dummy read */
}
diff --git a/arch/arm/mach-uniphier/clk/clk-dram-pxs2.c b/arch/arm/mach-uniphier/clk/clk-dram-pxs2.c
index ad4e83a..b78bd01 100644
--- a/arch/arm/mach-uniphier/clk/clk-dram-pxs2.c
+++ b/arch/arm/mach-uniphier/clk/clk-dram-pxs2.c
@@ -15,18 +15,18 @@
u32 tmp;
/* deassert reset */
- tmp = readl(SC_RSTCTRL4);
+ tmp = readl(sc_base + SC_RSTCTRL4);
tmp |= SC_RSTCTRL4_NRST_UMCSB | SC_RSTCTRL4_NRST_UMCA2 |
SC_RSTCTRL4_NRST_UMCA1 | SC_RSTCTRL4_NRST_UMCA0 |
SC_RSTCTRL4_NRST_UMC32 | SC_RSTCTRL4_NRST_UMC31 |
SC_RSTCTRL4_NRST_UMC30;
- writel(tmp, SC_RSTCTRL4);
- readl(SC_RSTCTRL4); /* dummy read */
+ writel(tmp, sc_base + SC_RSTCTRL4);
+ readl(sc_base + SC_RSTCTRL4); /* dummy read */
/* provide clocks */
- tmp = readl(SC_CLKCTRL4);
+ tmp = readl(sc_base + SC_CLKCTRL4);
tmp |= SC_CLKCTRL4_CEN_UMCSB | SC_CLKCTRL4_CEN_UMC2 |
SC_CLKCTRL4_CEN_UMC1 | SC_CLKCTRL4_CEN_UMC0;
- writel(tmp, SC_CLKCTRL4);
- readl(SC_CLKCTRL4); /* dummy read */
+ writel(tmp, sc_base + SC_CLKCTRL4);
+ readl(sc_base + SC_CLKCTRL4); /* dummy read */
}
diff --git a/arch/arm/mach-uniphier/clk/clk-early-ld4.c b/arch/arm/mach-uniphier/clk/clk-early-ld4.c
index eb36a9e..f32f78d 100644
--- a/arch/arm/mach-uniphier/clk/clk-early-ld4.c
+++ b/arch/arm/mach-uniphier/clk/clk-early-ld4.c
@@ -17,14 +17,14 @@
/* deassert reset */
if (spl_boot_device() != BOOT_DEVICE_NAND) {
- tmp = readl(SC_RSTCTRL);
+ tmp = readl(sc_base + SC_RSTCTRL);
tmp &= ~SC_RSTCTRL_NRST_NAND;
- writel(tmp, SC_RSTCTRL);
+ writel(tmp, sc_base + SC_RSTCTRL);
};
/* provide clocks */
- tmp = readl(SC_CLKCTRL);
+ tmp = readl(sc_base + SC_CLKCTRL);
tmp |= SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
- writel(tmp, SC_CLKCTRL);
- readl(SC_CLKCTRL); /* dummy read */
+ writel(tmp, sc_base + SC_CLKCTRL);
+ readl(sc_base + SC_CLKCTRL); /* dummy read */
}
diff --git a/arch/arm/mach-uniphier/clk/clk-ld20.c b/arch/arm/mach-uniphier/clk/clk-ld20.c
index 02a14dd..397b2d7 100644
--- a/arch/arm/mach-uniphier/clk/clk-ld20.c
+++ b/arch/arm/mach-uniphier/clk/clk-ld20.c
@@ -15,13 +15,13 @@
{
u32 tmp;
- tmp = readl(SC_RSTCTRL6);
+ tmp = readl(sc_base + SC_RSTCTRL6);
tmp |= BIT(8); /* Mali */
- writel(tmp, SC_RSTCTRL6);
+ writel(tmp, sc_base + SC_RSTCTRL6);
- tmp = readl(SC_CLKCTRL6);
+ tmp = readl(sc_base + SC_CLKCTRL6);
tmp |= BIT(8); /* Mali */
- writel(tmp, SC_CLKCTRL6);
+ writel(tmp, sc_base + SC_CLKCTRL6);
/* TODO: use "mmc-pwrseq-emmc" */
writel(1, SDCTRL_EMMC_HW_RESET);
diff --git a/arch/arm/mach-uniphier/clk/clk-ld4.c b/arch/arm/mach-uniphier/clk/clk-ld4.c
index 9c88cde..0393942 100644
--- a/arch/arm/mach-uniphier/clk/clk-ld4.c
+++ b/arch/arm/mach-uniphier/clk/clk-ld4.c
@@ -15,18 +15,18 @@
u32 tmp;
/* deassert reset */
- tmp = readl(SC_RSTCTRL);
+ tmp = readl(sc_base + SC_RSTCTRL);
#ifdef CONFIG_NAND_DENALI
tmp |= SC_RSTCTRL_NRST_NAND;
#endif
- writel(tmp, SC_RSTCTRL);
- readl(SC_RSTCTRL); /* dummy read */
+ writel(tmp, sc_base + SC_RSTCTRL);
+ readl(sc_base + SC_RSTCTRL); /* dummy read */
/* provide clocks */
- tmp = readl(SC_CLKCTRL);
+ tmp = readl(sc_base + SC_CLKCTRL);
#ifdef CONFIG_NAND_DENALI
tmp |= SC_CLKCTRL_CEN_NAND;
#endif
- writel(tmp, SC_CLKCTRL);
- readl(SC_CLKCTRL); /* dummy read */
+ writel(tmp, sc_base + SC_CLKCTRL);
+ readl(sc_base + SC_CLKCTRL); /* dummy read */
}
diff --git a/arch/arm/mach-uniphier/clk/clk-pro4.c b/arch/arm/mach-uniphier/clk/clk-pro4.c
index 32d44c0..2b364dc 100644
--- a/arch/arm/mach-uniphier/clk/clk-pro4.c
+++ b/arch/arm/mach-uniphier/clk/clk-pro4.c
@@ -15,7 +15,7 @@
u32 tmp;
/* deassert reset */
- tmp = readl(SC_RSTCTRL);
+ tmp = readl(sc_base + SC_RSTCTRL);
#ifdef CONFIG_USB_DWC3_UNIPHIER
tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_USB3C0 |
SC_RSTCTRL_NRST_GIO;
@@ -23,18 +23,18 @@
#ifdef CONFIG_NAND_DENALI
tmp |= SC_RSTCTRL_NRST_NAND;
#endif
- writel(tmp, SC_RSTCTRL);
- readl(SC_RSTCTRL); /* dummy read */
+ writel(tmp, sc_base + SC_RSTCTRL);
+ readl(sc_base + SC_RSTCTRL); /* dummy read */
#ifdef CONFIG_USB_DWC3_UNIPHIER
- tmp = readl(SC_RSTCTRL2);
+ tmp = readl(sc_base + SC_RSTCTRL2);
tmp |= SC_RSTCTRL2_NRST_USB3B1 | SC_RSTCTRL2_NRST_USB3C1;
- writel(tmp, SC_RSTCTRL2);
- readl(SC_RSTCTRL2); /* dummy read */
+ writel(tmp, sc_base + SC_RSTCTRL2);
+ readl(sc_base + SC_RSTCTRL2); /* dummy read */
#endif
/* provide clocks */
- tmp = readl(SC_CLKCTRL);
+ tmp = readl(sc_base + SC_CLKCTRL);
#ifdef CONFIG_USB_DWC3_UNIPHIER
tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
SC_CLKCTRL_CEN_GIO;
@@ -42,6 +42,6 @@
#ifdef CONFIG_NAND_DENALI
tmp |= SC_CLKCTRL_CEN_NAND;
#endif
- writel(tmp, SC_CLKCTRL);
- readl(SC_CLKCTRL); /* dummy read */
+ writel(tmp, sc_base + SC_CLKCTRL);
+ readl(sc_base + SC_CLKCTRL); /* dummy read */
}
diff --git a/arch/arm/mach-uniphier/clk/clk-pro5.c b/arch/arm/mach-uniphier/clk/clk-pro5.c
index 338d73d..874964b 100644
--- a/arch/arm/mach-uniphier/clk/clk-pro5.c
+++ b/arch/arm/mach-uniphier/clk/clk-pro5.c
@@ -13,25 +13,25 @@
u32 tmp;
/* deassert reset */
- tmp = readl(SC_RSTCTRL);
+ tmp = readl(sc_base + SC_RSTCTRL);
#ifdef CONFIG_USB_DWC3_UNIPHIER
tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_GIO;
#endif
#ifdef CONFIG_NAND_DENALI
tmp |= SC_RSTCTRL_NRST_NAND;
#endif
- writel(tmp, SC_RSTCTRL);
- readl(SC_RSTCTRL); /* dummy read */
+ writel(tmp, sc_base + SC_RSTCTRL);
+ readl(sc_base + SC_RSTCTRL); /* dummy read */
#ifdef CONFIG_USB_DWC3_UNIPHIER
- tmp = readl(SC_RSTCTRL2);
+ tmp = readl(sc_base + SC_RSTCTRL2);
tmp |= SC_RSTCTRL2_NRST_USB3B1;
- writel(tmp, SC_RSTCTRL2);
- readl(SC_RSTCTRL2); /* dummy read */
+ writel(tmp, sc_base + SC_RSTCTRL2);
+ readl(sc_base + SC_RSTCTRL2); /* dummy read */
#endif
/* provide clocks */
- tmp = readl(SC_CLKCTRL);
+ tmp = readl(sc_base + SC_CLKCTRL);
#ifdef CONFIG_USB_DWC3_UNIPHIER
tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
SC_CLKCTRL_CEN_GIO;
@@ -39,6 +39,6 @@
#ifdef CONFIG_NAND_DENALI
tmp |= SC_CLKCTRL_CEN_NAND;
#endif
- writel(tmp, SC_CLKCTRL);
- readl(SC_CLKCTRL); /* dummy read */
+ writel(tmp, sc_base + SC_CLKCTRL);
+ readl(sc_base + SC_CLKCTRL); /* dummy read */
}
diff --git a/arch/arm/mach-uniphier/clk/clk-pxs2.c b/arch/arm/mach-uniphier/clk/clk-pxs2.c
index afa12fa..8cb4f87 100644
--- a/arch/arm/mach-uniphier/clk/clk-pxs2.c
+++ b/arch/arm/mach-uniphier/clk/clk-pxs2.c
@@ -14,29 +14,29 @@
u32 tmp;
/* deassert reset */
- tmp = readl(SC_RSTCTRL);
+ tmp = readl(sc_base + SC_RSTCTRL);
#ifdef CONFIG_USB_DWC3_UNIPHIER
tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_GIO;
#endif
#ifdef CONFIG_NAND_DENALI
tmp |= SC_RSTCTRL_NRST_NAND;
#endif
- writel(tmp, SC_RSTCTRL);
- readl(SC_RSTCTRL); /* dummy read */
+ writel(tmp, sc_base + SC_RSTCTRL);
+ readl(sc_base + SC_RSTCTRL); /* dummy read */
#ifdef CONFIG_USB_DWC3_UNIPHIER
- tmp = readl(SC_RSTCTRL2);
+ tmp = readl(sc_base + SC_RSTCTRL2);
tmp |= SC_RSTCTRL2_NRST_USB3B1;
- writel(tmp, SC_RSTCTRL2);
- readl(SC_RSTCTRL2); /* dummy read */
+ writel(tmp, sc_base + SC_RSTCTRL2);
+ readl(sc_base + SC_RSTCTRL2); /* dummy read */
- tmp = readl(SC_RSTCTRL6);
+ tmp = readl(sc_base + SC_RSTCTRL6);
tmp |= 0x37;
- writel(tmp, SC_RSTCTRL6);
+ writel(tmp, sc_base + SC_RSTCTRL6);
#endif
/* provide clocks */
- tmp = readl(SC_CLKCTRL);
+ tmp = readl(sc_base + SC_CLKCTRL);
#ifdef CONFIG_USB_DWC3_UNIPHIER
tmp |= BIT(20) | BIT(19) | SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
SC_CLKCTRL_CEN_GIO;
@@ -44,6 +44,6 @@
#ifdef CONFIG_NAND_DENALI
tmp |= SC_CLKCTRL_CEN_NAND;
#endif
- writel(tmp, SC_CLKCTRL);
- readl(SC_CLKCTRL); /* dummy read */
+ writel(tmp, sc_base + SC_CLKCTRL);
+ readl(sc_base + SC_CLKCTRL); /* dummy read */
}
diff --git a/arch/arm/mach-uniphier/clk/clk-pxs3.c b/arch/arm/mach-uniphier/clk/clk-pxs3.c
index 73824e9..33b9c5b 100644
--- a/arch/arm/mach-uniphier/clk/clk-pxs3.c
+++ b/arch/arm/mach-uniphier/clk/clk-pxs3.c
@@ -15,13 +15,13 @@
{
u32 tmp;
- tmp = readl(SC_RSTCTRL6);
+ tmp = readl(sc_base + SC_RSTCTRL6);
tmp |= BIT(8); /* Mali */
- writel(tmp, SC_RSTCTRL6);
+ writel(tmp, sc_base + SC_RSTCTRL6);
- tmp = readl(SC_CLKCTRL6);
+ tmp = readl(sc_base + SC_CLKCTRL6);
tmp |= BIT(8); /* Mali */
- writel(tmp, SC_CLKCTRL6);
+ writel(tmp, sc_base + SC_CLKCTRL6);
/* TODO: use "mmc-pwrseq-emmc" */
writel(1, SDCTRL_EMMC_HW_RESET);
diff --git a/arch/arm/mach-uniphier/clk/dpll-ld4.c b/arch/arm/mach-uniphier/clk/dpll-ld4.c
index 4b9ec07..72fe8db 100644
--- a/arch/arm/mach-uniphier/clk/dpll-ld4.c
+++ b/arch/arm/mach-uniphier/clk/dpll-ld4.c
@@ -23,7 +23,7 @@
* Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
* to FOUT (DPLLCTRL.bit[29:20])
*/
- tmp = readl(SC_DPLLCTRL);
+ tmp = readl(sc_base + SC_DPLLCTRL);
tmp &= ~0x000f0000;
switch (dram_freq) {
case 1333:
@@ -42,11 +42,11 @@
#else
tmp |= SC_DPLLCTRL_SSC_RATE;
#endif
- writel(tmp, SC_DPLLCTRL);
+ writel(tmp, sc_base + SC_DPLLCTRL);
- tmp = readl(SC_DPLLCTRL2);
+ tmp = readl(sc_base + SC_DPLLCTRL2);
tmp |= SC_DPLLCTRL2_NRSTDS;
- writel(tmp, SC_DPLLCTRL2);
+ writel(tmp, sc_base + SC_DPLLCTRL2);
/* Wait 500 usec until dpll gets stable */
udelay(500);
diff --git a/arch/arm/mach-uniphier/clk/dpll-pro4.c b/arch/arm/mach-uniphier/clk/dpll-pro4.c
index 2965946..6259495 100644
--- a/arch/arm/mach-uniphier/clk/dpll-pro4.c
+++ b/arch/arm/mach-uniphier/clk/dpll-pro4.c
@@ -23,7 +23,7 @@
* Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
* to FOUT ( DPLLCTRL.bit[29:20] )
*/
- tmp = readl(SC_DPLLCTRL);
+ tmp = readl(sc_base + SC_DPLLCTRL);
tmp &= ~(0x000f0000);
switch (dram_freq) {
case 1333:
@@ -46,11 +46,11 @@
#else
tmp |= 0x00008000;
#endif
- writel(tmp, SC_DPLLCTRL);
+ writel(tmp, sc_base + SC_DPLLCTRL);
- tmp = readl(SC_DPLLCTRL2);
+ tmp = readl(sc_base + SC_DPLLCTRL2);
tmp |= SC_DPLLCTRL2_NRSTDS;
- writel(tmp, SC_DPLLCTRL2);
+ writel(tmp, sc_base + SC_DPLLCTRL2);
/* Wait until dpll gets stable */
udelay(500);
diff --git a/arch/arm/mach-uniphier/clk/dpll-sld8.c b/arch/arm/mach-uniphier/clk/dpll-sld8.c
index 1d7b752..1ac52d1 100644
--- a/arch/arm/mach-uniphier/clk/dpll-sld8.c
+++ b/arch/arm/mach-uniphier/clk/dpll-sld8.c
@@ -22,10 +22,10 @@
* [4] ICPD_TEST 0x1
* [3:0] ICPD 0xb
*/
- tmp = readl(SC_DPLLCTRL3);
+ tmp = readl(sc_base + SC_DPLLCTRL3);
tmp &= ~0x00ff0717;
tmp |= 0x00d0061b;
- writel(tmp, SC_DPLLCTRL3);
+ writel(tmp, sc_base + SC_DPLLCTRL3);
/*
* Set DPLL SSC parameters for DPLLCTRL
@@ -33,14 +33,14 @@
* [29:20] SSC_UPCNT 132 (0x084) 132 (0x084)
* [14:0] SSC_dK 6335(0x18bf) 12710(0x31a6)
*/
- tmp = readl(SC_DPLLCTRL);
+ tmp = readl(sc_base + SC_DPLLCTRL);
tmp &= ~0x3ff07fff;
#ifdef DPLL_SSC_RATE_1PER
tmp |= 0x084018bf;
#else
tmp |= 0x084031a6;
#endif
- writel(tmp, SC_DPLLCTRL);
+ writel(tmp, sc_base + SC_DPLLCTRL);
/*
* Set DPLL SSC parameters for DPLLCTRL2
@@ -49,10 +49,10 @@
* [26:20] SSC_M 79 (0x4f)
* [19:0] SSC_K 964689 (0xeb851)
*/
- tmp = readl(SC_DPLLCTRL2);
+ tmp = readl(sc_base + SC_DPLLCTRL2);
tmp &= ~0xefffffff;
tmp |= 0x0cfeb851;
- writel(tmp, SC_DPLLCTRL2);
+ writel(tmp, sc_base + SC_DPLLCTRL2);
/* Wait 500 usec until dpll gets stable */
udelay(500);
diff --git a/arch/arm/mach-uniphier/clk/dpll-tail.c b/arch/arm/mach-uniphier/clk/dpll-tail.c
index 7f434f6..6ba5a36 100644
--- a/arch/arm/mach-uniphier/clk/dpll-tail.c
+++ b/arch/arm/mach-uniphier/clk/dpll-tail.c
@@ -14,7 +14,7 @@
{
u32 tmp;
- tmp = readl(SC_DPLLCTRL);
+ tmp = readl(sc_base + SC_DPLLCTRL);
tmp |= SC_DPLLCTRL_SSC_EN;
- writel(tmp, SC_DPLLCTRL);
+ writel(tmp, sc_base + SC_DPLLCTRL);
}
diff --git a/arch/arm/mach-uniphier/clk/pll-base-ld20.c b/arch/arm/mach-uniphier/clk/pll-base-ld20.c
index 67b8ee7..ea96d73 100644
--- a/arch/arm/mach-uniphier/clk/pll-base-ld20.c
+++ b/arch/arm/mach-uniphier/clk/pll-base-ld20.c
@@ -12,6 +12,7 @@
#include <linux/io.h>
#include <linux/sizes.h>
+#include "../sc64-regs.h"
#include "pll.h"
/* PLL type: SSC */
@@ -31,13 +32,9 @@
int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq,
unsigned int ssc_rate, unsigned int divn)
{
- void __iomem *base;
+ void __iomem *base = sc_base + reg_base;
u32 tmp;
- base = ioremap(reg_base, SZ_16);
- if (!base)
- return -ENOMEM;
-
if (freq != UNIPHIER_PLL_FREQ_DEFAULT) {
tmp = readl(base); /* SSCPLLCTRL */
tmp &= ~SC_PLLCTRL_SSC_DK_MASK;
@@ -60,57 +57,39 @@
tmp |= SC_PLLCTRL2_NRSTDS;
writel(tmp, base + 4);
- iounmap(base);
-
return 0;
}
int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base)
{
- void __iomem *base;
+ void __iomem *base = sc_base + reg_base;
u32 tmp;
- base = ioremap(reg_base, SZ_16);
- if (!base)
- return -ENOMEM;
-
tmp = readl(base); /* SSCPLLCTRL */
tmp |= SC_PLLCTRL_SSC_EN;
writel(tmp, base);
- iounmap(base);
-
return 0;
}
int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi)
{
- void __iomem *base;
+ void __iomem *base = sc_base + reg_base;
u32 tmp;
- base = ioremap(reg_base, SZ_16);
- if (!base)
- return -ENOMEM;
-
tmp = readl(base + 8); /* SSCPLLCTRL3 */
tmp &= ~SC_PLLCTRL3_REGI_MASK;
tmp |= FIELD_PREP(SC_PLLCTRL3_REGI_MASK, regi);
writel(tmp, base + 8);
- iounmap(base);
-
return 0;
}
int uniphier_ld20_vpll27_init(unsigned long reg_base)
{
- void __iomem *base;
+ void __iomem *base = sc_base + reg_base;
u32 tmp;
- base = ioremap(reg_base, SZ_16);
- if (!base)
- return -ENOMEM;
-
tmp = readl(base); /* VPLL27CTRL */
tmp |= SC_VPLL27CTRL_WP; /* write protect off */
writel(tmp, base);
@@ -123,25 +102,17 @@
tmp &= ~SC_VPLL27CTRL_WP; /* write protect on */
writel(tmp, base);
- iounmap(base);
-
return 0;
}
int uniphier_ld20_dspll_init(unsigned long reg_base)
{
- void __iomem *base;
+ void __iomem *base = sc_base + reg_base;
u32 tmp;
- base = ioremap(reg_base, SZ_16);
- if (!base)
- return -ENOMEM;
-
tmp = readl(base + 4); /* DSPLLCTRL2 */
tmp |= SC_DSPLLCTRL2_K_LD;
writel(tmp, base + 4);
- iounmap(base);
-
return 0;
}
diff --git a/arch/arm/mach-uniphier/clk/pll-ld11.c b/arch/arm/mach-uniphier/clk/pll-ld11.c
index fd724f3..7f07e3e 100644
--- a/arch/arm/mach-uniphier/clk/pll-ld11.c
+++ b/arch/arm/mach-uniphier/clk/pll-ld11.c
@@ -11,15 +11,15 @@
#include "pll.h"
/* PLL type: SSC */
-#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* CPU/ARM */
-#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* misc */
-#define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* DSP */
-#define SC_VSPLLCTRL (SC_BASE_ADDR | 0x1440) /* Video codec, VPE etc. */
-#define SC_DPLLCTRL (SC_BASE_ADDR | 0x1460) /* DDR memory */
+#define SC_CPLLCTRL 0x1400 /* CPU/ARM */
+#define SC_SPLLCTRL 0x1410 /* misc */
+#define SC_MPLLCTRL 0x1430 /* DSP */
+#define SC_VSPLLCTRL 0x1440 /* Video codec, VPE etc. */
+#define SC_DPLLCTRL 0x1460 /* DDR memory */
/* PLL type: VPLL27 */
-#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500)
-#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520)
+#define SC_VPLL27FCTRL 0x1500
+#define SC_VPLL27ACTRL 0x1520
void uniphier_ld11_pll_init(void)
{
@@ -40,6 +40,6 @@
uniphier_ld20_vpll27_init(SC_VPLL27FCTRL);
uniphier_ld20_vpll27_init(SC_VPLL27ACTRL);
- writel(0, SC_CA53_GEARSET); /* Gear0: CPLL/2 */
- writel(SC_CA_GEARUPD, SC_CA53_GEARUPD);
+ writel(0, sc_base + SC_CA53_GEARSET); /* Gear0: CPLL/2 */
+ writel(SC_CA_GEARUPD, sc_base + SC_CA53_GEARUPD);
}
diff --git a/arch/arm/mach-uniphier/clk/pll-ld20.c b/arch/arm/mach-uniphier/clk/pll-ld20.c
index 682bd1e..04b3312 100644
--- a/arch/arm/mach-uniphier/clk/pll-ld20.c
+++ b/arch/arm/mach-uniphier/clk/pll-ld20.c
@@ -11,23 +11,23 @@
#include "pll.h"
/* PLL type: SSC */
-#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* CPU/ARM */
-#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* misc */
-#define SC_SPLL2CTRL (SC_BASE_ADDR | 0x1420) /* DSP */
-#define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* Video codec */
-#define SC_VPPLLCTRL (SC_BASE_ADDR | 0x1440) /* VPE etc. */
-#define SC_GPPLLCTRL (SC_BASE_ADDR | 0x1450) /* GPU/Mali */
-#define SC_DPLL0CTRL (SC_BASE_ADDR | 0x1460) /* DDR memory 0 */
-#define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1470) /* DDR memory 1 */
-#define SC_DPLL2CTRL (SC_BASE_ADDR | 0x1480) /* DDR memory 2 */
+#define SC_CPLLCTRL 0x1400 /* CPU/ARM */
+#define SC_SPLLCTRL 0x1410 /* misc */
+#define SC_SPLL2CTRL 0x1420 /* DSP */
+#define SC_MPLLCTRL 0x1430 /* Video codec */
+#define SC_VPPLLCTRL 0x1440 /* VPE etc. */
+#define SC_GPPLLCTRL 0x1450 /* GPU/Mali */
+#define SC_DPLL0CTRL 0x1460 /* DDR memory 0 */
+#define SC_DPLL1CTRL 0x1470 /* DDR memory 1 */
+#define SC_DPLL2CTRL 0x1480 /* DDR memory 2 */
/* PLL type: VPLL27 */
-#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500)
-#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520)
+#define SC_VPLL27FCTRL 0x1500
+#define SC_VPLL27ACTRL 0x1520
/* PLL type: DSPLL */
-#define SC_VPLL8KCTRL (SC_BASE_ADDR | 0x1540)
-#define SC_A2PLLCTRL (SC_BASE_ADDR | 0x15C0)
+#define SC_VPLL8KCTRL 0x1540
+#define SC_A2PLLCTRL 0x15C0
void uniphier_ld20_pll_init(void)
{
diff --git a/arch/arm/mach-uniphier/clk/pll-ld4.c b/arch/arm/mach-uniphier/clk/pll-ld4.c
index 34f1c9c..c66031b 100644
--- a/arch/arm/mach-uniphier/clk/pll-ld4.c
+++ b/arch/arm/mach-uniphier/clk/pll-ld4.c
@@ -21,9 +21,9 @@
clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
/* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
- tmp = readl(SC_UPLLCTRL);
+ tmp = readl(sc_base + SC_UPLLCTRL);
tmp &= ~0x18000000;
- writel(tmp, SC_UPLLCTRL);
+ writel(tmp, sc_base + SC_UPLLCTRL);
if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
@@ -38,18 +38,18 @@
}
}
- writel(tmp, SC_UPLLCTRL);
+ writel(tmp, sc_base + SC_UPLLCTRL);
/* set 1 to K_LD(UPLLCTRL.bit[27]) */
tmp |= 0x08000000;
- writel(tmp, SC_UPLLCTRL);
+ writel(tmp, sc_base + SC_UPLLCTRL);
/* wait 10 usec */
udelay(10);
/* set 1 to SNRT(UPLLCTRL.bit[28]) */
tmp |= 0x10000000;
- writel(tmp, SC_UPLLCTRL);
+ writel(tmp, sc_base + SC_UPLLCTRL);
}
static void vpll_init(void)
@@ -60,88 +60,88 @@
clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
/* set 1 to VPLA27WP and VPLA27WP */
- tmp = readl(SC_VPLL27ACTRL);
+ tmp = readl(sc_base + SC_VPLL27ACTRL);
tmp |= 0x00000001;
- writel(tmp, SC_VPLL27ACTRL);
- tmp = readl(SC_VPLL27BCTRL);
+ writel(tmp, sc_base + SC_VPLL27ACTRL);
+ tmp = readl(sc_base + SC_VPLL27BCTRL);
tmp |= 0x00000001;
- writel(tmp, SC_VPLL27BCTRL);
+ writel(tmp, sc_base + SC_VPLL27BCTRL);
/* Set 0 to VPLA_K_LD and VPLB_K_LD */
- tmp = readl(SC_VPLL27ACTRL3);
+ tmp = readl(sc_base + SC_VPLL27ACTRL3);
tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
+ writel(tmp, sc_base + SC_VPLL27ACTRL3);
+ tmp = readl(sc_base + SC_VPLL27BCTRL3);
tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27BCTRL3);
+ writel(tmp, sc_base + SC_VPLL27BCTRL3);
/* Set 0 to VPLA_SNRST and VPLB_SNRST */
- tmp = readl(SC_VPLL27ACTRL2);
+ tmp = readl(sc_base + SC_VPLL27ACTRL2);
tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
+ writel(tmp, sc_base + SC_VPLL27ACTRL2);
+ tmp = readl(sc_base + SC_VPLL27BCTRL2);
tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27BCTRL2);
+ writel(tmp, sc_base + SC_VPLL27BCTRL2);
/* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
- tmp = readl(SC_VPLL27ACTRL2);
+ tmp = readl(sc_base + SC_VPLL27ACTRL2);
tmp &= ~0x0000007f;
tmp |= 0x00000020;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
+ writel(tmp, sc_base + SC_VPLL27ACTRL2);
+ tmp = readl(sc_base + SC_VPLL27BCTRL2);
tmp &= ~0x0000007f;
tmp |= 0x00000020;
- writel(tmp, SC_VPLL27BCTRL2);
+ writel(tmp, sc_base + SC_VPLL27BCTRL2);
if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
/* AXO: 25MHz */
- tmp = readl(SC_VPLL27ACTRL3);
+ tmp = readl(sc_base + SC_VPLL27ACTRL3);
tmp &= ~0x000fffff;
tmp |= 0x00066664;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
+ writel(tmp, sc_base + SC_VPLL27ACTRL3);
+ tmp = readl(sc_base + SC_VPLL27BCTRL3);
tmp &= ~0x000fffff;
tmp |= 0x00066664;
- writel(tmp, SC_VPLL27BCTRL3);
+ writel(tmp, sc_base + SC_VPLL27BCTRL3);
} else {
/* AXO: default 24.576MHz */
- tmp = readl(SC_VPLL27ACTRL3);
+ tmp = readl(sc_base + SC_VPLL27ACTRL3);
tmp &= ~0x000fffff;
tmp |= 0x000f5800;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
+ writel(tmp, sc_base + SC_VPLL27ACTRL3);
+ tmp = readl(sc_base + SC_VPLL27BCTRL3);
tmp &= ~0x000fffff;
tmp |= 0x000f5800;
- writel(tmp, SC_VPLL27BCTRL3);
+ writel(tmp, sc_base + SC_VPLL27BCTRL3);
}
/* Set 1 to VPLA_K_LD and VPLB_K_LD */
- tmp = readl(SC_VPLL27ACTRL3);
+ tmp = readl(sc_base + SC_VPLL27ACTRL3);
tmp |= 0x10000000;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
+ writel(tmp, sc_base + SC_VPLL27ACTRL3);
+ tmp = readl(sc_base + SC_VPLL27BCTRL3);
tmp |= 0x10000000;
- writel(tmp, SC_VPLL27BCTRL3);
+ writel(tmp, sc_base + SC_VPLL27BCTRL3);
/* wait 10 usec */
udelay(10);
/* Set 0 to VPLA_SNRST and VPLB_SNRST */
- tmp = readl(SC_VPLL27ACTRL2);
+ tmp = readl(sc_base + SC_VPLL27ACTRL2);
tmp |= 0x10000000;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
+ writel(tmp, sc_base + SC_VPLL27ACTRL2);
+ tmp = readl(sc_base + SC_VPLL27BCTRL2);
tmp |= 0x10000000;
- writel(tmp, SC_VPLL27BCTRL2);
+ writel(tmp, sc_base + SC_VPLL27BCTRL2);
/* set 0 to VPLA27WP and VPLA27WP */
- tmp = readl(SC_VPLL27ACTRL);
+ tmp = readl(sc_base + SC_VPLL27ACTRL);
tmp &= ~0x00000001;
- writel(tmp, SC_VPLL27ACTRL);
- tmp = readl(SC_VPLL27BCTRL);
+ writel(tmp, sc_base + SC_VPLL27ACTRL);
+ tmp = readl(sc_base + SC_VPLL27BCTRL);
tmp |= ~0x00000001;
- writel(tmp, SC_VPLL27BCTRL);
+ writel(tmp, sc_base + SC_VPLL27BCTRL);
}
void uniphier_ld4_pll_init(void)
diff --git a/arch/arm/mach-uniphier/clk/pll-pro4.c b/arch/arm/mach-uniphier/clk/pll-pro4.c
index 312a5fc..b7dc3e2 100644
--- a/arch/arm/mach-uniphier/clk/pll-pro4.c
+++ b/arch/arm/mach-uniphier/clk/pll-pro4.c
@@ -26,80 +26,80 @@
return;
/* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
- tmp = readl(SC_VPLL27ACTRL);
+ tmp = readl(sc_base + SC_VPLL27ACTRL);
tmp |= 0x00000001;
- writel(tmp, SC_VPLL27ACTRL);
- tmp = readl(SC_VPLL27BCTRL);
+ writel(tmp, sc_base + SC_VPLL27ACTRL);
+ tmp = readl(sc_base + SC_VPLL27BCTRL);
tmp |= 0x00000001;
- writel(tmp, SC_VPLL27BCTRL);
+ writel(tmp, sc_base + SC_VPLL27BCTRL);
/* Unset VPLA_K_LD and VPLB_K_LD bit */
- tmp = readl(SC_VPLL27ACTRL3);
+ tmp = readl(sc_base + SC_VPLL27ACTRL3);
tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
+ writel(tmp, sc_base + SC_VPLL27ACTRL3);
+ tmp = readl(sc_base + SC_VPLL27BCTRL3);
tmp &= ~0x10000000;
- writel(tmp, SC_VPLL27BCTRL3);
+ writel(tmp, sc_base + SC_VPLL27BCTRL3);
/* Set VPLA_M and VPLB_M to 0x20 */
- tmp = readl(SC_VPLL27ACTRL2);
+ tmp = readl(sc_base + SC_VPLL27ACTRL2);
tmp &= ~0x0000007f;
tmp |= 0x00000020;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
+ writel(tmp, sc_base + SC_VPLL27ACTRL2);
+ tmp = readl(sc_base + SC_VPLL27BCTRL2);
tmp &= ~0x0000007f;
tmp |= 0x00000020;
- writel(tmp, SC_VPLL27BCTRL2);
+ writel(tmp, sc_base + SC_VPLL27BCTRL2);
if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) {
/* Set VPLA_K and VPLB_K for AXO: 25MHz */
- tmp = readl(SC_VPLL27ACTRL3);
+ tmp = readl(sc_base + SC_VPLL27ACTRL3);
tmp &= ~0x000fffff;
tmp |= 0x00066666;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
+ writel(tmp, sc_base + SC_VPLL27ACTRL3);
+ tmp = readl(sc_base + SC_VPLL27BCTRL3);
tmp &= ~0x000fffff;
tmp |= 0x00066666;
- writel(tmp, SC_VPLL27BCTRL3);
+ writel(tmp, sc_base + SC_VPLL27BCTRL3);
} else {
/* Set VPLA_K and VPLB_K for AXO: 24.576 MHz */
- tmp = readl(SC_VPLL27ACTRL3);
+ tmp = readl(sc_base + SC_VPLL27ACTRL3);
tmp &= ~0x000fffff;
tmp |= 0x000f5800;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
+ writel(tmp, sc_base + SC_VPLL27ACTRL3);
+ tmp = readl(sc_base + SC_VPLL27BCTRL3);
tmp &= ~0x000fffff;
tmp |= 0x000f5800;
- writel(tmp, SC_VPLL27BCTRL3);
+ writel(tmp, sc_base + SC_VPLL27BCTRL3);
}
/* wait 1 usec */
udelay(1);
/* Set VPLA_K_LD and VPLB_K_LD to load K parameters */
- tmp = readl(SC_VPLL27ACTRL3);
+ tmp = readl(sc_base + SC_VPLL27ACTRL3);
tmp |= 0x10000000;
- writel(tmp, SC_VPLL27ACTRL3);
- tmp = readl(SC_VPLL27BCTRL3);
+ writel(tmp, sc_base + SC_VPLL27ACTRL3);
+ tmp = readl(sc_base + SC_VPLL27BCTRL3);
tmp |= 0x10000000;
- writel(tmp, SC_VPLL27BCTRL3);
+ writel(tmp, sc_base + SC_VPLL27BCTRL3);
/* Unset VPLA_SNRST and VPLB_SNRST bit */
- tmp = readl(SC_VPLL27ACTRL2);
+ tmp = readl(sc_base + SC_VPLL27ACTRL2);
tmp |= 0x10000000;
- writel(tmp, SC_VPLL27ACTRL2);
- tmp = readl(SC_VPLL27BCTRL2);
+ writel(tmp, sc_base + SC_VPLL27ACTRL2);
+ tmp = readl(sc_base + SC_VPLL27BCTRL2);
tmp |= 0x10000000;
- writel(tmp, SC_VPLL27BCTRL2);
+ writel(tmp, sc_base + SC_VPLL27BCTRL2);
/* Enable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
- tmp = readl(SC_VPLL27ACTRL);
+ tmp = readl(sc_base + SC_VPLL27ACTRL);
tmp &= ~0x00000001;
- writel(tmp, SC_VPLL27ACTRL);
- tmp = readl(SC_VPLL27BCTRL);
+ writel(tmp, sc_base + SC_VPLL27ACTRL);
+ tmp = readl(sc_base + SC_VPLL27BCTRL);
tmp &= ~0x00000001;
- writel(tmp, SC_VPLL27BCTRL);
+ writel(tmp, sc_base + SC_VPLL27BCTRL);
}
void uniphier_pro4_pll_init(void)
diff --git a/arch/arm/mach-uniphier/clk/pll-pxs3.c b/arch/arm/mach-uniphier/clk/pll-pxs3.c
index 5a1b1d2..278f530 100644
--- a/arch/arm/mach-uniphier/clk/pll-pxs3.c
+++ b/arch/arm/mach-uniphier/clk/pll-pxs3.c
@@ -10,25 +10,25 @@
#include "pll.h"
/* PLL type: SSC */
-#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* CPU/ARM */
-#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* misc */
-#define SC_SPLL2CTRL (SC_BASE_ADDR | 0x1420) /* DSP */
-#define SC_VPPLLCTRL (SC_BASE_ADDR | 0x1430) /* VPE */
-#define SC_VGPLLCTRL (SC_BASE_ADDR | 0x1440)
-#define SC_DECPLLCTRL (SC_BASE_ADDR | 0x1450)
-#define SC_ENCPLLCTRL (SC_BASE_ADDR | 0x1460)
-#define SC_PXFPLLCTRL (SC_BASE_ADDR | 0x1470)
-#define SC_DPLL0CTRL (SC_BASE_ADDR | 0x1480) /* DDR memory 0 */
-#define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1490) /* DDR memory 1 */
-#define SC_DPLL2CTRL (SC_BASE_ADDR | 0x14a0) /* DDR memory 2 */
-#define SC_VSPLLCTRL (SC_BASE_ADDR | 0x14c0)
+#define SC_CPLLCTRL 0x1400 /* CPU/ARM */
+#define SC_SPLLCTRL 0x1410 /* misc */
+#define SC_SPLL2CTRL 0x1420 /* DSP */
+#define SC_VPPLLCTRL 0x1430 /* VPE */
+#define SC_VGPLLCTRL 0x1440
+#define SC_DECPLLCTRL 0x1450
+#define SC_ENCPLLCTRL 0x1460
+#define SC_PXFPLLCTRL 0x1470
+#define SC_DPLL0CTRL 0x1480 /* DDR memory 0 */
+#define SC_DPLL1CTRL 0x1490 /* DDR memory 1 */
+#define SC_DPLL2CTRL 0x14a0 /* DDR memory 2 */
+#define SC_VSPLLCTRL 0x14c0
/* PLL type: VPLL27 */
-#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500)
-#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520)
+#define SC_VPLL27FCTRL 0x1500
+#define SC_VPLL27ACTRL 0x1520
/* PLL type: DSPLL */
-#define SC_VPLL8KCTRL (SC_BASE_ADDR | 0x1540)
+#define SC_VPLL8KCTRL 0x1540
void uniphier_pxs3_pll_init(void)
{