| York Sun | 149eb33 | 2016-09-26 08:09:27 -0700 | [diff] [blame] | 1 | config ARCH_LS1021A |
| York Sun | fcd0e74 | 2016-10-04 14:31:47 -0700 | [diff] [blame] | 2 | bool |
| York Sun | 149eb33 | 2016-09-26 08:09:27 -0700 | [diff] [blame] | 3 | select SYS_FSL_ERRATUM_A010315 |
| York Sun | 6b62ef0 | 2016-10-04 18:01:34 -0700 | [diff] [blame] | 4 | select SYS_FSL_SRDS_1 |
| 5 | select SYS_HAS_SERDES |
| York Sun | f64fc5c | 2016-10-04 18:04:37 -0700 | [diff] [blame] | 6 | select SYS_FSL_DDR_BE |
| 7 | select SYS_FSL_DDR_VER_50 |
| York Sun | 4de7e93 | 2016-09-26 08:09:29 -0700 | [diff] [blame] | 8 | |
| York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 9 | menu "LS102xA architecture" |
| 10 | depends on ARCH_LS1021A |
| 11 | |
| York Sun | 4de7e93 | 2016-09-26 08:09:29 -0700 | [diff] [blame] | 12 | config LS1_DEEP_SLEEP |
| York Sun | fcd0e74 | 2016-10-04 14:31:47 -0700 | [diff] [blame] | 13 | bool "Deep sleep" |
| 14 | depends on ARCH_LS1021A |
| York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 15 | |
| York Sun | f188d22 | 2016-10-04 14:45:01 -0700 | [diff] [blame] | 16 | config MAX_CPUS |
| 17 | int "Maximum number of CPUs permitted for LS102xA" |
| 18 | depends on ARCH_LS1021A |
| 19 | default 2 |
| 20 | help |
| 21 | Set this number to the maximum number of possible CPUs in the SoC. |
| 22 | SoCs may have multiple clusters with each cluster may have multiple |
| 23 | ports. If some ports are reserved but higher ports are used for |
| 24 | cores, count the reserved ports. This will allocate enough memory |
| 25 | in spin table to properly handle all cores. |
| 26 | |
| York Sun | f64fc5c | 2016-10-04 18:04:37 -0700 | [diff] [blame] | 27 | config NUM_DDR_CONTROLLERS |
| 28 | int "Maximum DDR controllers" |
| 29 | default 1 |
| 30 | |
| York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 31 | config SYS_FSL_ERRATUM_A010315 |
| 32 | bool "Workaround for PCIe erratum A010315" |
| 33 | |
| York Sun | 6b62ef0 | 2016-10-04 18:01:34 -0700 | [diff] [blame] | 34 | config SYS_FSL_SRDS_1 |
| 35 | bool |
| 36 | |
| 37 | config SYS_FSL_SRDS_2 |
| 38 | bool |
| 39 | |
| 40 | config SYS_HAS_SERDES |
| 41 | bool |
| York Sun | f64fc5c | 2016-10-04 18:04:37 -0700 | [diff] [blame] | 42 | |
| 43 | config SYS_FSL_DDR |
| 44 | bool "Freescale DDR driver" |
| 45 | help |
| 46 | Select Freescale General DDR driver, shared between most Freescale |
| 47 | PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM- |
| 48 | based Layerscape SoCs (such as ls2080a). |
| 49 | |
| 50 | config SYS_FSL_DDR_BE |
| 51 | bool |
| 52 | default y |
| 53 | help |
| 54 | Access DDR registers in big-endian. |
| 55 | |
| 56 | config SYS_FSL_DDR_VER |
| 57 | int |
| 58 | default 50 if SYS_FSL_DDR_VER_50 |
| 59 | |
| 60 | config SYS_FSL_DDR_VER_50 |
| 61 | bool |
| 62 | |
| 63 | config SYS_FSL_DDRC_ARM_GEN3 |
| 64 | bool |
| 65 | |
| 66 | config SYS_FSL_DDRC_GEN4 |
| 67 | bool |
| 68 | |
| 69 | config SYS_FSL_DDR3 |
| 70 | bool "Freescale DDR3 controller" |
| 71 | depends on !SYS_FSL_DDR4 |
| 72 | select SYS_FSL_DDR |
| 73 | select SYS_FSL_DDRC_ARM_GEN3 |
| 74 | help |
| 75 | Enable Freescale DDR3 controller on ARM-based SoCs. |
| 76 | |
| 77 | config SYS_FSL_DDR4 |
| 78 | bool "Freescale DDR4 controller" |
| 79 | select SYS_FSL_DDR |
| 80 | select SYS_FSL_DDRC_GEN4 |
| 81 | help |
| 82 | Enable Freescale DDR4 controller. |
| York Sun | 6b62ef0 | 2016-10-04 18:01:34 -0700 | [diff] [blame] | 83 | |
| York Sun | e7310a3 | 2016-10-04 14:45:54 -0700 | [diff] [blame] | 84 | config SYS_FSL_IFC_BANK_COUNT |
| 85 | int "Maximum banks of Integrated flash controller" |
| 86 | depends on ARCH_LS1021A |
| 87 | default 8 |
| 88 | |
| York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 89 | endmenu |