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git01.mediatek.com / filogic / uboot / f6a9929a3a568a3d40c04019743b5dfa1c0c038c / . / configs / nanopi-r2s-rk3328_defconfig
blob: 4dfb7782d98bd18042a4807c27bc22b216eb33f5 [file] [log] [blame]
David Bauerdcde9f62021-01-07 00:06:11 +0100[diff] [blame]1CONFIG_ARM=y
Tom Rinie1e85442021-08-27 21:18:30 -0400[diff] [blame]2CONFIG_SKIP_LOWLEVEL_INIT=y
Peng Fanc8a61c02022-04-13 17:47:20 +0800[diff] [blame]3CONFIG_COUNTER_FREQUENCY=24000000
David Bauerdcde9f62021-01-07 00:06:11 +0100[diff] [blame]4CONFIG_ARCH_ROCKCHIP=y
5CONFIG_SYS_TEXT_BASE=0x00200000
Simon Glass035939e2021-07-10 21:14:30 -0600[diff] [blame]6CONFIG_SPL_GPIO=y
Tom Rinib2e0b322021-01-29 13:56:04 -0500[diff] [blame]7CONFIG_NR_DRAM_BANKS=1
David Bauerdcde9f62021-01-07 00:06:11 +0100[diff] [blame]8CONFIG_ENV_OFFSET=0x3F8000
Tom Rinia20e51f2021-06-28 10:17:29 -0400[diff] [blame]9CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2s"
David Bauerdcde9f62021-01-07 00:06:11 +0100[diff] [blame]10CONFIG_ROCKCHIP_RK3328=y
11CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
12CONFIG_TPL_LIBCOMMON_SUPPORT=y
13CONFIG_TPL_LIBGENERIC_SUPPORT=y
Simon Glass284cb9c2021-07-10 21:14:31 -0600[diff] [blame]14CONFIG_SPL_DRIVERS_MISC=y
David Bauerdcde9f62021-01-07 00:06:11 +0100[diff] [blame]15CONFIG_SPL_STACK_R_ADDR=0x600000
David Bauerdcde9f62021-01-07 00:06:11 +0100[diff] [blame]16CONFIG_DEBUG_UART_BASE=0xFF130000
17CONFIG_DEBUG_UART_CLOCK=24000000
Tom Rini4b2fcb32022-04-08 13:36:51 -0400[diff] [blame]18CONFIG_SYS_LOAD_ADDR=0x800800
Tom Rinie0a54502022-07-25 17:19:18 -0400[diff] [blame]19CONFIG_TPL_MAX_SIZE=0x40000
David Bauerdcde9f62021-01-07 00:06:11 +0100[diff] [blame]20CONFIG_DEBUG_UART=y
Tom Rini4ddbade2022-05-25 12:16:03 -0400[diff] [blame]21CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
22CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
David Bauerdcde9f62021-01-07 00:06:11 +0100[diff] [blame]23CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
24# CONFIG_ANDROID_BOOT_IMAGE is not set
25CONFIG_FIT=y
26CONFIG_FIT_VERBOSE=y
27CONFIG_SPL_LOAD_FIT=y
28CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2s.dtb"
David Bauerdcde9f62021-01-07 00:06:11 +0100[diff] [blame]29# CONFIG_DISPLAY_CPUINFO is not set
30CONFIG_DISPLAY_BOARDINFO_LATE=y
Tom Rinib2e0b322021-01-29 13:56:04 -0500[diff] [blame]31CONFIG_MISC_INIT_R=y
Tom Riniabb0f522022-05-16 17:20:26 -0400[diff] [blame]32CONFIG_SPL_MAX_SIZE=0x40000
33CONFIG_SPL_PAD_TO=0x7f8000
Tom Rini65aa1242022-05-27 10:19:45 -0400[diff] [blame]34CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
35CONFIG_SPL_BSS_START_ADDR=0x2000000
Tom Rini0cb89e72022-05-19 15:09:22 -0400[diff] [blame]36CONFIG_SPL_BSS_MAX_SIZE=0x2000
David Bauerdcde9f62021-01-07 00:06:11 +0100[diff] [blame]37# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
Tom Rini8a14ac42022-05-26 13:13:21 -0400[diff] [blame]38# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
39CONFIG_SPL_STACK=0x400000
David Bauerdcde9f62021-01-07 00:06:11 +0100[diff] [blame]40CONFIG_SPL_STACK_R=y
Simon Glassbccfc2e2021-07-10 21:14:36 -0600[diff] [blame]41CONFIG_SPL_I2C=y
Simon Glasse91ac4c2021-07-10 21:14:24 -0600[diff] [blame]42CONFIG_SPL_POWER=y
David Bauerdcde9f62021-01-07 00:06:11 +0100[diff] [blame]43CONFIG_SPL_ATF=y
44CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
Tom Rini2c3c2822022-06-06 12:13:29 -0400[diff] [blame]45CONFIG_TPL_SYS_MALLOC_SIMPLE=y
David Bauerdcde9f62021-01-07 00:06:11 +0100[diff] [blame]46CONFIG_CMD_BOOTZ=y
47CONFIG_CMD_GPT=y
48CONFIG_CMD_MMC=y
49CONFIG_CMD_USB=y
50# CONFIG_CMD_SETEXPR is not set
51CONFIG_CMD_TIME=y
52CONFIG_SPL_OF_CONTROL=y
53CONFIG_TPL_OF_CONTROL=y
David Bauerdcde9f62021-01-07 00:06:11 +0100[diff] [blame]54CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
55CONFIG_TPL_OF_PLATDATA=y
56CONFIG_ENV_IS_IN_MMC=y
57CONFIG_SYS_RELOC_GD_ENV_ADDR=y
Tom Rinib7f02a62022-07-04 08:15:34 -0400[diff] [blame]58CONFIG_SYS_MMC_ENV_DEV=1
David Bauerdcde9f62021-01-07 00:06:11 +0100[diff] [blame]59CONFIG_NET_RANDOM_ETHADDR=y
60CONFIG_TPL_DM=y
61CONFIG_REGMAP=y
62CONFIG_SPL_REGMAP=y
63CONFIG_TPL_REGMAP=y
64CONFIG_SYSCON=y
65CONFIG_SPL_SYSCON=y
66CONFIG_TPL_SYSCON=y
67CONFIG_CLK=y
68CONFIG_SPL_CLK=y
69CONFIG_FASTBOOT_BUF_ADDR=0x800800
70CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
71CONFIG_ROCKCHIP_GPIO=y
72CONFIG_SYS_I2C_ROCKCHIP=y
73CONFIG_MMC_DW=y
74CONFIG_MMC_DW_ROCKCHIP=y
75CONFIG_SF_DEFAULT_SPEED=20000000
David Bauerdcde9f62021-01-07 00:06:11 +0100[diff] [blame]76CONFIG_ETH_DESIGNWARE=y
77CONFIG_GMAC_ROCKCHIP=y
78CONFIG_PINCTRL=y
79CONFIG_SPL_PINCTRL=y
80CONFIG_DM_PMIC=y
81CONFIG_PMIC_RK8XX=y
Simon Glass6343ffb2021-08-08 12:20:25 -0600[diff] [blame]82CONFIG_SPL_PMIC_RK8XX=y
David Bauerdcde9f62021-01-07 00:06:11 +0100[diff] [blame]83CONFIG_SPL_DM_REGULATOR=y
84CONFIG_REGULATOR_PWM=y
85CONFIG_DM_REGULATOR_FIXED=y
86CONFIG_SPL_DM_REGULATOR_FIXED=y
87CONFIG_REGULATOR_RK8XX=y
88CONFIG_PWM_ROCKCHIP=y
89CONFIG_RAM=y
90CONFIG_SPL_RAM=y
91CONFIG_TPL_RAM=y
92CONFIG_DM_RESET=y
93CONFIG_BAUDRATE=1500000
94CONFIG_DEBUG_UART_SHIFT=2
Tom Rinib2e0b322021-01-29 13:56:04 -0500[diff] [blame]95CONFIG_SYSINFO=y
David Bauerdcde9f62021-01-07 00:06:11 +0100[diff] [blame]96CONFIG_SYSRESET=y
97# CONFIG_TPL_SYSRESET is not set
98CONFIG_USB=y
99CONFIG_USB_XHCI_HCD=y
100CONFIG_USB_XHCI_DWC3=y
101CONFIG_USB_EHCI_HCD=y
102CONFIG_USB_EHCI_GENERIC=y
103CONFIG_USB_OHCI_HCD=y
104CONFIG_USB_OHCI_GENERIC=y
Tom Rini112d2e02022-06-25 11:02:31 -0400[diff] [blame]105CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1
David Bauerdcde9f62021-01-07 00:06:11 +0100[diff] [blame]106CONFIG_USB_DWC2=y
107CONFIG_USB_DWC3=y
108# CONFIG_USB_DWC3_GADGET is not set
109CONFIG_USB_GADGET=y
110CONFIG_USB_GADGET_DWC2_OTG=y
111CONFIG_SPL_TINY_MEMSET=y
112CONFIG_TPL_TINY_MEMSET=y
113CONFIG_ERRNO_STR=y