| David Bauer | dcde9f6 | 2021-01-07 00:06:11 +0100 | [diff] [blame] | 1 | CONFIG_ARM=y |
| Tom Rini | e1e8544 | 2021-08-27 21:18:30 -0400 | [diff] [blame] | 2 | CONFIG_SKIP_LOWLEVEL_INIT=y |
| David Bauer | dcde9f6 | 2021-01-07 00:06:11 +0100 | [diff] [blame] | 3 | CONFIG_ARCH_ROCKCHIP=y |
| 4 | CONFIG_SYS_TEXT_BASE=0x00200000 |
| Simon Glass | 035939e | 2021-07-10 21:14:30 -0600 | [diff] [blame] | 5 | CONFIG_SPL_GPIO=y |
| Tom Rini | b2e0b32 | 2021-01-29 13:56:04 -0500 | [diff] [blame] | 6 | CONFIG_NR_DRAM_BANKS=1 |
| David Bauer | dcde9f6 | 2021-01-07 00:06:11 +0100 | [diff] [blame] | 7 | CONFIG_ENV_OFFSET=0x3F8000 |
| Tom Rini | a20e51f | 2021-06-28 10:17:29 -0400 | [diff] [blame] | 8 | CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2s" |
| David Bauer | dcde9f6 | 2021-01-07 00:06:11 +0100 | [diff] [blame] | 9 | CONFIG_ROCKCHIP_RK3328=y |
| 10 | CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y |
| 11 | CONFIG_TPL_LIBCOMMON_SUPPORT=y |
| 12 | CONFIG_TPL_LIBGENERIC_SUPPORT=y |
| Simon Glass | 284cb9c | 2021-07-10 21:14:31 -0600 | [diff] [blame] | 13 | CONFIG_SPL_DRIVERS_MISC=y |
| David Bauer | dcde9f6 | 2021-01-07 00:06:11 +0100 | [diff] [blame] | 14 | CONFIG_SPL_STACK_R_ADDR=0x600000 |
| David Bauer | dcde9f6 | 2021-01-07 00:06:11 +0100 | [diff] [blame] | 15 | CONFIG_DEBUG_UART_BASE=0xFF130000 |
| 16 | CONFIG_DEBUG_UART_CLOCK=24000000 |
| David Bauer | dcde9f6 | 2021-01-07 00:06:11 +0100 | [diff] [blame] | 17 | CONFIG_DEBUG_UART=y |
| 18 | CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 |
| Tom Rini | 0997ee0 | 2021-08-23 10:25:31 -0400 | [diff] [blame] | 19 | CONFIG_SYS_LOAD_ADDR=0x800800 |
| David Bauer | dcde9f6 | 2021-01-07 00:06:11 +0100 | [diff] [blame] | 20 | # CONFIG_ANDROID_BOOT_IMAGE is not set |
| 21 | CONFIG_FIT=y |
| 22 | CONFIG_FIT_VERBOSE=y |
| 23 | CONFIG_SPL_LOAD_FIT=y |
| 24 | CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2s.dtb" |
| David Bauer | dcde9f6 | 2021-01-07 00:06:11 +0100 | [diff] [blame] | 25 | # CONFIG_DISPLAY_CPUINFO is not set |
| 26 | CONFIG_DISPLAY_BOARDINFO_LATE=y |
| Tom Rini | b2e0b32 | 2021-01-29 13:56:04 -0500 | [diff] [blame] | 27 | CONFIG_MISC_INIT_R=y |
| David Bauer | dcde9f6 | 2021-01-07 00:06:11 +0100 | [diff] [blame] | 28 | # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set |
| 29 | CONFIG_TPL_SYS_MALLOC_SIMPLE=y |
| 30 | CONFIG_SPL_STACK_R=y |
| Simon Glass | bccfc2e | 2021-07-10 21:14:36 -0600 | [diff] [blame] | 31 | CONFIG_SPL_I2C=y |
| Simon Glass | e91ac4c | 2021-07-10 21:14:24 -0600 | [diff] [blame] | 32 | CONFIG_SPL_POWER=y |
| David Bauer | dcde9f6 | 2021-01-07 00:06:11 +0100 | [diff] [blame] | 33 | CONFIG_SPL_ATF=y |
| 34 | CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y |
| 35 | CONFIG_CMD_BOOTZ=y |
| 36 | CONFIG_CMD_GPT=y |
| 37 | CONFIG_CMD_MMC=y |
| 38 | CONFIG_CMD_USB=y |
| 39 | # CONFIG_CMD_SETEXPR is not set |
| 40 | CONFIG_CMD_TIME=y |
| 41 | CONFIG_SPL_OF_CONTROL=y |
| 42 | CONFIG_TPL_OF_CONTROL=y |
| David Bauer | dcde9f6 | 2021-01-07 00:06:11 +0100 | [diff] [blame] | 43 | CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" |
| 44 | CONFIG_TPL_OF_PLATDATA=y |
| 45 | CONFIG_ENV_IS_IN_MMC=y |
| 46 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y |
| 47 | CONFIG_NET_RANDOM_ETHADDR=y |
| 48 | CONFIG_TPL_DM=y |
| 49 | CONFIG_REGMAP=y |
| 50 | CONFIG_SPL_REGMAP=y |
| 51 | CONFIG_TPL_REGMAP=y |
| 52 | CONFIG_SYSCON=y |
| 53 | CONFIG_SPL_SYSCON=y |
| 54 | CONFIG_TPL_SYSCON=y |
| 55 | CONFIG_CLK=y |
| 56 | CONFIG_SPL_CLK=y |
| 57 | CONFIG_FASTBOOT_BUF_ADDR=0x800800 |
| 58 | CONFIG_FASTBOOT_CMD_OEM_FORMAT=y |
| 59 | CONFIG_ROCKCHIP_GPIO=y |
| 60 | CONFIG_SYS_I2C_ROCKCHIP=y |
| 61 | CONFIG_MMC_DW=y |
| 62 | CONFIG_MMC_DW_ROCKCHIP=y |
| 63 | CONFIG_SF_DEFAULT_SPEED=20000000 |
| 64 | CONFIG_DM_ETH=y |
| 65 | CONFIG_ETH_DESIGNWARE=y |
| 66 | CONFIG_GMAC_ROCKCHIP=y |
| 67 | CONFIG_PINCTRL=y |
| 68 | CONFIG_SPL_PINCTRL=y |
| 69 | CONFIG_DM_PMIC=y |
| 70 | CONFIG_PMIC_RK8XX=y |
| Simon Glass | 6343ffb | 2021-08-08 12:20:25 -0600 | [diff] [blame^] | 71 | CONFIG_SPL_PMIC_RK8XX=y |
| David Bauer | dcde9f6 | 2021-01-07 00:06:11 +0100 | [diff] [blame] | 72 | CONFIG_SPL_DM_REGULATOR=y |
| 73 | CONFIG_REGULATOR_PWM=y |
| 74 | CONFIG_DM_REGULATOR_FIXED=y |
| 75 | CONFIG_SPL_DM_REGULATOR_FIXED=y |
| 76 | CONFIG_REGULATOR_RK8XX=y |
| 77 | CONFIG_PWM_ROCKCHIP=y |
| 78 | CONFIG_RAM=y |
| 79 | CONFIG_SPL_RAM=y |
| 80 | CONFIG_TPL_RAM=y |
| 81 | CONFIG_DM_RESET=y |
| 82 | CONFIG_BAUDRATE=1500000 |
| 83 | CONFIG_DEBUG_UART_SHIFT=2 |
| Tom Rini | b2e0b32 | 2021-01-29 13:56:04 -0500 | [diff] [blame] | 84 | CONFIG_SYSINFO=y |
| David Bauer | dcde9f6 | 2021-01-07 00:06:11 +0100 | [diff] [blame] | 85 | CONFIG_SYSRESET=y |
| 86 | # CONFIG_TPL_SYSRESET is not set |
| 87 | CONFIG_USB=y |
| 88 | CONFIG_USB_XHCI_HCD=y |
| 89 | CONFIG_USB_XHCI_DWC3=y |
| 90 | CONFIG_USB_EHCI_HCD=y |
| 91 | CONFIG_USB_EHCI_GENERIC=y |
| 92 | CONFIG_USB_OHCI_HCD=y |
| 93 | CONFIG_USB_OHCI_GENERIC=y |
| 94 | CONFIG_USB_DWC2=y |
| 95 | CONFIG_USB_DWC3=y |
| 96 | # CONFIG_USB_DWC3_GADGET is not set |
| 97 | CONFIG_USB_GADGET=y |
| 98 | CONFIG_USB_GADGET_DWC2_OTG=y |
| 99 | CONFIG_SPL_TINY_MEMSET=y |
| 100 | CONFIG_TPL_TINY_MEMSET=y |
| 101 | CONFIG_ERRNO_STR=y |